CN219873494U

CN219873494U - Packaging structure

Info

Publication number: CN219873494U
Application number: CN202322468569.8U
Authority: CN
Inventors: 孟怀宇; 沈亦晨; 严其新
Original assignee: Beijing Guangzhiyuan Technology Co ltd
Current assignee: Beijing Guangzhiyuan Technology Co ltd
Priority date: 2023-09-12
Filing date: 2023-09-12
Publication date: 2023-10-20
Anticipated expiration: 2033-09-12

Abstract

The utility model provides a packaging structure, which comprises: a first semiconductor chip having opposite first and second surfaces, the first surface being provided with an optical coupling region and a non-optical coupling region, wherein the optical coupling region is surrounded by the non-optical coupling region, and an optical coupling interface is provided in the optical coupling region; a protective structure disposed on a non-light coupling region of a periphery of the light coupling region of the first surface and surrounding the light coupling region; a plastic layer covering the non-light coupling region of the first surface and being blocked outside the light coupling region by a protective structure. Through the protection structure, when the plastic sealing layer is manufactured on the non-optical coupling area of the first semiconductor chip, the upper surface of the optical coupling area is not covered by the plastic sealing layer, the optical coupling interface in the optical coupling area is protected from being polluted by organic matters in the plastic sealing layer, meanwhile, the surface purity of the optical coupling area is guaranteed, and the follow-up optical coupling interface can maintain higher coupling efficiency with external light input.

Description

Packaging structure

Technical Field

The utility model relates to the field of semiconductor packaging, in particular to a packaging structure.

Background

With the increasing development of semiconductor technology, a package structure having a high integration density is increasingly important. For example, stacking of chips with each other may be achieved using a 3D package structure.

Electronic integrated circuit (Electronic integrated circuit, EIC) chips and photonic integrated circuit (Photonic integrated circuit, PIC) chips in the existing silicon optical chips adopt different wafer generation process steps, and chip-level interconnection (such as wire bonding or flip-chip interconnection) is adopted to realize connection between the electronic integrated circuit chips and the photonic integrated circuit chips, so that a three-dimensional interconnection structure is formed.

In the three-dimensional packaging of the photonic integrated circuit chip and the electronic integrated circuit chip, in order to avoid the dislocation or failure of the connection points of the photonic integrated circuit chip and the electronic integrated circuit chip caused by warping when the photonic integrated circuit chip is thinned, or in order to make the packaging of the photonic integrated circuit chip and the electronic integrated circuit chip have higher strength, a plastic sealing layer is generally required to be formed on the surface of the photonic integrated circuit chip. However, the photonic integrated circuit chip has an optical fiber coupling interface for inputting light, and directly molding the surface of the photonic integrated circuit chip may cause damage to the optical fiber coupling interface, thereby greatly increasing the insertion loss of the optical fiber coupling interface and affecting the actual use of the packaged optoelectronic chip.

The conventional 3D optoelectronic chip without plastic package has excessive warpage, low yield and cannot be applied to stacking between large-sized photonic integrated circuit chips and electronic integrated circuit chips in the stacking process of the multilayer chips, and is also unfavorable for realizing the mounting of the ultrathin photonic integrated circuit chips with through silicon vias (Through Silicon Via, TSVs) structures.

Disclosure of Invention

In order to overcome the defects in the prior art, the utility model aims to provide a packaging structure which can protect an optical coupling interface on an optical sub-assembly circuit chip while using a plastic packaging material to fix an optoelectronic integrated chip so as to improve packaging strength and avoid warping of the photonic integrated circuit chip.

The utility model adopts the following technical scheme:

according to an embodiment of the present utility model, a package structure includes:

the semiconductor device comprises a first semiconductor chip, a second semiconductor chip and a first light source, wherein the first semiconductor chip is provided with a first surface and a second surface which are opposite, an optical coupling area and a non-optical coupling area are arranged on the first surface, the optical coupling area is surrounded by the non-optical coupling area, and an optical coupling interface is arranged in the optical coupling area;

a protective structure on and surrounding the non-optical coupling region of the first surface, wherein the protective structure comprises a photoresist formed directly on the first surface or a copper structure formed by electroplating on the first surface;

a plastic layer covering the non-light coupling region of the first surface and being blocked outside the light coupling region by the protective structure.

In some embodiments of the utility model, a top surface of the protective structure remote from the first surface is flush with a top surface of the plastic layer remote from the first surface in a direction perpendicular to the first surface. In some embodiments of the utility model, the protective structure is interposed between and in contact with the plastic layer and the optical coupling region.

In some embodiments of the utility model, the package structure further comprises at least one second semiconductor chip disposed at the non-optical coupling region of the first surface and surrounded by the plastic layer. In some embodiments of the utility model, a top surface of the at least one second semiconductor chip remote from the first surface is exposed from the molding layer and is flush with a top surface of the protective structure.

In some embodiments of the utility model, the protective structure has an opening exposing the optical coupling interface. In some embodiments of the utility model, the package structure further comprises: a light guiding structure or an inverted light emitting device is arranged above the light coupling interface. In some embodiments of the utility model, the optical coupling interface has one or more grating structures.

In some embodiments of the present utility model, the first semiconductor chip has a conductive via (e.g., a through silicon via) therethrough, a first end of the conductive via being exposed from the first surface of the first semiconductor chip and electrically connected to the second semiconductor chip, and a second end of the conductive via being exposed from the second surface of the first semiconductor chip and having a conductive bump.

In some embodiments of the present utility model, the package structure further includes a package substrate on which the first semiconductor chip is mounted, and the conductive bump is electrically connected with the package substrate.

The implementation of the utility model has the following advantages:

the packaging structure provided by the embodiment of the utility model can prevent the upper surface of the optical coupling area from being covered by the plastic sealing layer, protect the optical coupling interface in the optical coupling area from being polluted by organic matters in the plastic sealing layer, ensure the surface purity of the optical coupling area, solve the problem of conflict between the plastic sealing process and the coupling space in the three-dimensional stacked packaging, and simultaneously provide protection for the chip.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present utility model, and that other embodiments may be obtained according to these drawings without inventive effort to a person skilled in the art.

Fig. 1 is a schematic cross-sectional view of a package structure according to embodiment 1 of the present utility model.

Fig. 2 is a schematic plan view of a first surface of a first semiconductor chip of a package structure according to the present utility model.

Fig. 3 is a schematic cross-sectional view of a package structure according to embodiment 2 of the present utility model.

Fig. 4 is a schematic cross-sectional view of a package structure according to embodiment 3 of the present utility model.

Description of the embodiments

The foregoing description is only an overview of the present utility model, and is intended to be implemented in accordance with the teachings of the present utility model, as well as the preferred embodiments thereof, together with the following detailed description of the utility model, given by way of illustration only, together with the accompanying drawings.

In the description of the present utility model, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to the specific circumstances.

Aiming at the problems that the existing photoelectric chip packaging mode cannot be subjected to plastic packaging, the packaging interconnection reliability is poor, the packaging area is large, the performance is poor and the like, the embodiment of the utility model provides a manufacturing method of a packaging structure with an optical interconnection interface, and the electronic integrated circuit chip and the photon integrated circuit chip are stacked and then subjected to plastic packaging, so that the packaging interconnection reliability is ensured, and meanwhile, the protection of an optical fiber coupling interface is realized.

The utility model will be further described in detail with reference to the drawings and detailed description below in order to make the objects, features and advantages of the utility model more comprehensible.

Fig. 1 shows embodiment 1 of the package structure of the present utility model. In this embodiment, the package structure includes a first semiconductor chip 101, a protection structure 103, and a plastic layer 104.

The first semiconductor chip 101 has opposite first (e.g., upper) and second (e.g., lower) surfaces. As shown in fig. 2, an optical coupling area 101-1 and a non-optical coupling area 101-2 are disposed on the first surface, wherein the optical coupling area 101-1 is surrounded by the non-optical coupling area 101-2, and an optical coupling interface 102 is disposed in the optical coupling area 101-1. The protective structure 103 is disposed on the non-light coupling region 101-2 of the periphery of the light coupling region 101-1 of the first surface, the protective structure 103 surrounding the light coupling region 101-1. Returning to fig. 1, the plastic layer 104 covers the non-light coupling region of the first surface and is blocked outside the light coupling region by the protective structure 103.

In some embodiments, the plastic layer 104 encapsulates the outer surface of the protective structure 103 away from the optical coupling region 101-1, and the plastic layer 104 does not cover the optical coupling region 101-1 and the upper surface of the protective structure 103.

In some embodiments, the first semiconductor chip 101 may be a PIC chip, which may be made of silicon, with an optical waveguide formed inside, and the optical coupling interface 102 is provided with one or more grating structures connected to the optical waveguide. And, the protective structure 103 has an opening exposing the optical coupling interface 102.

In some embodiments, the protective structure 103 is a hollow tubular structure, the cross-section of the inner and outer walls of which are any combination of circles, polygons, respectively.

In some embodiments, the protective structure 103 comprises a photoresist or a plated copper structure formed directly on the first semiconductor chip 101. As an example, the method for preparing the protective structure 103 composed of photoresist includes: and forming a photoresist layer with a thickness of about 20-150 μm on the first surface of the first semiconductor chip 101, wherein the specific thickness is determined by the thickness of a plastic sealing layer formed later, and removing the photoresist layer on the light coupling area and part of the non-light coupling area through exposure and development steps, so as to leave a circle of annular photoresist on the non-light coupling area 101-2 at the periphery of the light coupling area 101-1, thereby obtaining the protection structure 103. As another example, the method of manufacturing the protective structure 103 composed of electroplated copper includes: forming a nano-copper seed layer on the first surface of the first semiconductor chip 101, forming a photoresist layer with a thickness of about 20-150 μm on the copper seed layer, wherein the specific thickness is determined by the thickness of a subsequently formed plastic layer, removing a circle of annular photoresist layer on the non-optical coupling area 101-2 at the periphery of the optical coupling area 101-1 through exposure and development steps, leaving the rest of photoresist layer, forming an annular gap on the non-optical coupling area 101-2 at the periphery of the optical coupling area 101-1, forming electroplated copper in the annular gap by using the first semiconductor chip 101 as an electrode through an electroplating method, and then removing the rest of photoresist and seed layer to obtain the protection structure 103. Since the protection structure 103 of the present utility model is directly formed on the first surface of the first semiconductor chip 101, the alignment mismatch of the position thereof depends on the alignment accuracy of photolithography, because the alignment accuracy of the position of the protection structure 103 can be controlled in the range of 1 μm, the alignment accuracy of the protection structure 103 is greatly improved.

In some embodiments, a top surface of the protective structure 103, which is remote from the first surface, is flush with a top surface of the plastic layer 104, which is remote from the first surface, in a direction perpendicular to the first surface of the first semiconductor chip 101. In other words, on the first surface of the first semiconductor chip 101, the height of the protection structure 103 is substantially the same as the height (or thickness) of the plastic layer 104. The protective structure 103 is interposed between the plastic layer 104 and the optical coupling region and is in contact with the plastic layer 104. As an example, the preparation method of the plastic sealing layer 104 includes: providing a plastic package mold, wherein a release film is arranged on the inner surface of a cavity of the plastic package mold, the plastic package mold with the release film arranged on the inner surface is inverted and pressed on the upper surface of the first semiconductor chip 101, and the upper surface of the annular protection structure 103 is tightly attached to the inner surface of the plastic package mold. Through the molding compound injection opening, a molding compound is injected onto the non-optical coupling region 101-2 of the first semiconductor chip 101. Because the annular protection structure 103 is tightly attached to the plastic packaging mold, the plastic packaging material enters the non-optical coupling area 101-2 through injection, so that no injection of the plastic packaging material exists in the optical coupling area 101-1, and the surface of the optical coupling area 101-1 is kept clean. The optical coupling interface is beneficial to maintaining higher coupling efficiency with external light input.

Fig. 3 shows embodiment 2 of the package structure of the present utility model. Embodiment 2 has a similar structure to embodiment 1, the main difference between the two is that the package structure of embodiment 2 further comprises at least one second semiconductor chip 105, and the at least one second semiconductor chip 105 is disposed in the non-light coupling region of the first surface of the first semiconductor chip 101 and surrounded by the plastic sealing layer 104. Specifically, the plastic layer 104 encapsulates the side surface of the at least one second semiconductor chip 105, and exposes the upper surface of the at least one second semiconductor chip 105 for heat dissipation.

In some embodiments, the first semiconductor chip 101 is a silicon-based optical chip (e.g., PIC chip, photonic wafer, etc.), and the second semiconductor chip 105 may be an electrical chip, such as an EIC chip.

Specifically, when the first semiconductor chip 101 is a silicon-based optical chip, a plurality of conductive vias 109 are fabricated in the substrate in the first semiconductor chip 101, and the conductive vias may be fabricated using a "through silicon via" (Through Silicon Via, TSV), which is a high-density packaging technology, is gradually replacing the wire bonding technology that is mature in the current technology, and is considered as a fourth generation packaging technology. The TSV technology realizes vertical electrical interconnection of through-silicon vias by filling conductive substances such as copper, tungsten, polysilicon, and the like. The through silicon via technology can reduce interconnection length, signal delay, capacitance/inductance and low power consumption and high-speed communication between chips through vertical interconnection, increase broadband and realize miniaturization of device integration. The TSV process may include deep silicon etching to form micro holes or blind holes, deposition of insulating layer/barrier layer/seed layer, deep hole filling, chemical mechanical polishing, thinning, redistribution lead preparation, etc., and the process method of forming conductive vias in the optical chip includes, but is not limited to, laser etching, deep reactive ion etching, etc., and filling of conductive material (e.g., metal) after forming the conductive vias using, for example, deep hole filling, etc. The present utility model is not described in detail herein.

At least a portion of the plurality of conductive vias 109 have first ends exposed from the first surface of the first semiconductor chip 101 and electrically connected to the second semiconductor chip 105, and second ends exposed from the second surface of the first semiconductor chip and have conductive bumps 110, such as pads (e.g., C4 bumps) or solder balls, etc. In some embodiments, a first end of the conductive via 109 exposed from the first surface of the first semiconductor chip 101 is bonded to the second semiconductor chip 105. The conductive bump 110 at the second end of the conductive via 109 exposed from the second surface of the first semiconductor chip 101 is electrically connected to an external electrical connection point.

In some embodiments, a top surface of the at least one second semiconductor chip 105 remote from the first surface of the first semiconductor chip 101 is substantially flush with a top surface of the protective structure 103. In some embodiments, a top surface of the at least one second semiconductor chip 105 remote from the first surface of the first semiconductor chip 101 is substantially flush with a top surface of the molding layer 104. In some embodiments, the top surface of the at least one second semiconductor chip 105, which is remote from the first surface of the first semiconductor chip 101, the top surface of the protective structure 103, and the top surface of the molding layer 104 are substantially flush. Thereby, protection of the second semiconductor chip 105 by the plastic sealing layer 104 can be achieved, and the package structure is easy to assemble with other electrical components in application by adopting the flush structure.

Fig. 4 shows embodiment 3 of the package structure of the present utility model. Embodiment 3 has a similar structure to embodiment 2, and the main difference between the two is that the package structure of embodiment 3 further includes a package substrate 106, the first semiconductor chip 101 is mounted on the package substrate 106, and the conductive bump 110 is electrically connected to the package substrate 106. Specifically, a pad 111 is formed on the upper surface of the package substrate 106, the conductive bump 110 of the first semiconductor chip 101 is bonded to the pad 111, and a molding material 108 is filled between the first semiconductor chip 101 and the package substrate 106, thereby mounting the first semiconductor chip 101 on the package substrate 106. Wherein the conductive path of the second semiconductor chip 105 to the package substrate 106 includes a conductive via 109, a conductive bump 110, and a pad 111.

In some embodiments, the package structure further comprises a light guiding structure 107 disposed over the light coupling interface 102. The light guiding structure 107 is for example an optical fiber or an array of optical fibers.

In some embodiments, a light emitting device (not shown) may be inverted over the light coupling interface 102 in place of the light guiding structure 107. The light emitting device is, for example, a semiconductor laser or the like.

It will be appreciated by those skilled in the art that the foregoing disclosure is merely illustrative of the present utility model and that no limitation on the scope of the claimed utility model is intended, as defined by the appended claims and equivalents thereof.

Claims

1. A package structure, comprising:

2. The package structure of claim 1, wherein,

the top surface of the protective structure, which is away from the first surface, is flush with the top surface of the plastic layer, which is away from the first surface, in a direction perpendicular to the first surface.

3. The package structure of claim 2, wherein,

the protective structure is interposed between and in contact with the plastic sealing layer and the optical coupling region.

4. The package structure according to any one of claim 1 to 3,

the package structure further includes at least one second semiconductor chip disposed at the non-optical coupling region of the first surface and surrounded by the plastic layer.

5. The package structure of claim 4, wherein,

a top surface of the at least one second semiconductor chip remote from the first surface is exposed from the molding layer and is flush with a top surface of the protective structure.

6. The package structure of claim 1, wherein,

the protective structure has an opening exposing the optical coupling interface.

7. The package structure of claim 6, further comprising:

a light guiding structure or an inverted light emitting device is arranged above the light coupling interface.

8. The package structure of claim 1, 6 or 7,

the optical coupling interface has one or more grating structures.

9. The package structure of claim 4, wherein,

the first semiconductor chip is provided with a through conductive through hole, a first end of the conductive through hole is exposed from the first surface of the first semiconductor chip and is electrically connected with the second semiconductor chip, and a second end of the conductive through hole is exposed from the second surface of the first semiconductor chip and is provided with a conductive bump.

10. The package structure of claim 9, further comprising a package substrate, the first semiconductor chip being mounted on the package substrate, and the conductive bump being electrically connected to the package substrate.