WO2023174186A1

WO2023174186A1 - Manufacturing method for packaging structure, and packaging structure

Info

Publication number: WO2023174186A1
Application number: PCT/CN2023/080944
Authority: WO
Inventors: 王宏杰; 孟怀宇; 沈亦晨
Original assignee: 上海曦智科技有限公司
Priority date: 2022-03-18
Filing date: 2023-03-10
Publication date: 2023-09-21
Also published as: CN114823358A; TW202339023A

Abstract

Disclosed are a manufacturing method for a packaging structure, and a packaging structure. The method comprises: providing a semiconductor die, the semiconductor die comprising a plurality of first semiconductor chips, and the plurality of first semiconductor chips on the semiconductor die forming an integral structure; and for each of the first semiconductor chips, manufacturing, on a non-optical coupling area of the first semiconductor chip, an optical coupling area protection ring surrounding an optical coupling area, so that when a plastic packaging layer is manufactured on the non-optical coupling area of the first semiconductor chip, the upper surface of the optical coupling area is not covered by the plastic packaging layer, an optical coupling interface in the optical coupling area is protected from being contaminated by an organic matter in the plastic packaging layer, and the surface purity of the optical coupling area is ensured, thereby facilitating the optical coupling interface maintaining high coupling efficiency with an optical fiber array in the subsequent process.

Description

Manufacturing method and packaging structure of packaging structure

This application claims priority to the Chinese patent application submitted to the China Patent Office on March 18, 2022, with the application number 202210272769.3 and the invention title "Method for making a packaging structure and packaging structure", the entire content of which is incorporated into this application by reference. middle.

Technical field

The present application relates to the field of semiconductor packaging, and more specifically, to a manufacturing method and packaging structure of a packaging structure.

Background technique

With the increasing development of semiconductor technology, packaging structures with high integration density are becoming more and more important. For example, 3D packaging structures can be used to stack chips on top of each other.

Currently, the electrical chip (Electronic Integrated Circuit Chip, EIC, Electronic integrated chip) and the optical chip (Photonic Integrated Circuit Chip, PIC, Photonic integrated chip) among the existing silicon photonic chips adopt different wafer generation processes and adopt the chip level. Interconnection (such as wire bonding or flip-chip interconnection) is used to realize the connection between the electrical chip (EIC) and the optical chip (PIC) to form a three-dimensional interconnection structure.

In the three-dimensional packaging of optical chips (PIC) and electrical chips (EIC), in order to avoid warping caused by thinning the optical chip (PIC), which may lead to misalignment or failure of the connection points between the optical chip (PIC) and the electrical chip (EIC), Or in order to make the packaging of the optical chip (PIC) and the electrical chip (EIC) have higher strength, it is usually necessary to form a plastic sealing layer on the surface of the optical chip (PIC). However, the optical chip (PIC) has a fiber coupling interface for input light. Directly molding the surface of the optical chip (PIC) will cause damage to the fiber coupling interface, resulting in a significant increase in the insertion loss of the fiber coupling interface and affecting the optoelectronic chip. actual use.

However, traditional 3D optoelectronic chips without plastic packaging suffer from excessive warpage during the multi-layer chip stacking process, low yield, and cannot be applied to the stacking between large-size photonic integrated circuit chips and electronic integrated circuit chips. It is also not conducive to implementation. Mounting of ultra-thin photonic integrated circuit chips with "Through Silicon Via" (TSV) structure.

technical problem

Embodiments of the present application provide a manufacturing method and packaging structure of a packaging structure to solve the problem of using plastic packaging materials to fix photonic integrated circuit chips-electronic integrated circuit chips to improve packaging strength and avoid warping of the photonic integrated circuit chips. The optical fiber coupling interface interface on the photonic integrated circuit chip forms a protection to prevent the optical coupling interface interface on the photonic integrated circuit chip from being contaminated by organic matter in the plastic sealing layer.

Technical solutions

Embodiments of the present application provide a method for manufacturing a packaging structure and a packaging structure.

In a first aspect, embodiments of the present application provide a method for manufacturing a packaging structure, including: providing a semiconductor wafer, the semiconductor wafer including a plurality of first semiconductor chips, each of the first semiconductor chips having an opposite first surface and A second surface, a light coupling area and a non-light coupling area surrounding the light coupling area are provided on the first surface, and an light coupling interface is provided in the light coupling area; for each of the first semiconductor chips, Provide at least one second semiconductor chip and a light coupling area protection ring corresponding to the first semiconductor chip, and fix the at least one second semiconductor chip and the light coupling area protection ring to all parts of the first semiconductor chip respectively. on the non-light coupling area of the first surface, wherein the light coupling area protective ring surrounds the light coupling area; a plastic encapsulation layer is produced, and the plastic encapsulation layer covers the at least one second semiconductor chip and the The light coupling area protection ring is away from the outer surface of the light coupling area and the plastic sealing layer does not cover the area other than the light coupling area protection ring.

In some embodiments, in a direction perpendicular to the first surface, the light coupling region protection ring is away from a top surface of the first surface and the at least one second semiconductor chip is away from a top surface of the first surface. The top surface is flush.

In some embodiments, the manufacturing of the plastic packaging layer includes: providing a plastic packaging mold, the plastic packaging mold having a plurality of U-shaped cavities corresponding to the plurality of first semiconductor chips, and in each of the cavities A gel-like plastic sealing material is provided in a preset area of the body; the plastic sealing mold provided with the gel-like plastic sealing material is inverted and pressed on the first surface of the semiconductor wafer to form the plastic sealing layer.

In some embodiments, the preparation of the plastic sealing layer further includes: when the plastic sealing mold is inverted and pressed onto the semiconductor wafer, the top surface of the light coupling area protection ring away from the first surface and The bottom of the cavity fits.

In some embodiments, the preparation of the plastic sealing layer further includes: before setting the gel-like plastic sealing material Before, a glue-repellent layer is provided at the bottom of each cavity, and the glue-like plastic sealing material is provided in the preset area of the glue-repellent layer.

In some embodiments, the preparation of the plastic sealing layer further includes: when the plastic sealing mold is inverted and pressed onto the semiconductor wafer, the top surface of the light coupling area protection ring away from the first surface and The glue-repellent layer is attached.

In some embodiments, after forming the molding layer, the molding mold is removed.

In some embodiments, after removing the plastic mold, the semiconductor wafer is cut to obtain a plurality of separate chip packaging components. Each of the chip packaging components includes a first semiconductor chip, a corresponding at least one first semiconductor chip, and a first semiconductor chip. 2. Semiconductor chip, optical coupling area protection ring and plastic sealing layer.

In some embodiments, after obtaining a plurality of separate chip packaging components, each of the chip packaging components is mounted on a corresponding packaging substrate; and a light guide structure or a laser chip is mounted on the first semiconductor on the optical coupling interface of the chip.

In some embodiments, before fixing the at least one second semiconductor chip and the light coupling area guard ring on the non-light coupling area of the first surface of the corresponding first semiconductor chip, A plurality of conductive channels are made in each first semiconductor chip, and both sides of each conductive channel are exposed from both sides of the first semiconductor chip.

In some embodiments, after exposing both side surfaces of each conductive channel from the surface of the first semiconductor chip, first conductive bumps are formed on the exposed one side surface of each conductive channel.

In some embodiments, after forming a first conductive bump on the exposed side surface of each conductive channel, the side surface of each first semiconductor chip close to the first conductive bump is connected to a first conductive bump. The two carrier substrates are temporarily bonded; and, second conductive bumps are formed on the exposed other side surface of each conductive channel of each first semiconductor chip.

In some embodiments, after forming a second conductive bump on the exposed other side surface of each conductive channel of each first semiconductor chip, the first semiconductor chip is placed close to the second conductive bump. One side surface of the bump is temporarily bonded to the first carrier substrate; and the second carrier substrate is debonded.

The first semiconductor chip is a photonic integrated circuit chip, and the second semiconductor chip is an electronic integrated circuit chip.

In some embodiments, the light coupling area protection ring is a hollow tubular structure or a hollow cup-shaped structure with a top cover.

In some embodiments, the light coupling region protection ring includes at least one of metal, ceramic, and silicon.

In a second aspect, embodiments of the present application further provide a packaging structure, including: a first semiconductor chip, the first semiconductor chip having an opposite first surface and a second surface, and an optical coupling region is provided on the first surface. and a non-optical coupling area surrounding the optical coupling area, an optical coupling interface is provided in the optical coupling area; at least one second semiconductor chip and an optical coupling area protection ring, the at least one second semiconductor chip and the optical coupling area Coupling area protection rings are respectively fixed on the non-light coupling areas of the first surface, wherein the light coupling area protection rings surround the light coupling area; a plastic sealing layer covers the at least one The second semiconductor chip and the light coupling area protection ring are away from the outer surface of the light coupling area and the plastic sealing layer does not cover the area occupied by the light coupling area protection ring.

In some embodiments, in a direction perpendicular to the first surface, the top surface of the light coupling area protection ring away from the first surface is flush with the top surface of the plastic sealing layer away from the first surface. .

In some embodiments, the top surface of the at least one second semiconductor chip away from the first surface is exposed outside the plastic encapsulation layer, and in a direction perpendicular to the first surface, the light coupling region A top surface of the protective ring away from the first surface is flush with a top surface of the at least one second semiconductor chip away from the first surface.

In some embodiments, the light coupling area protection ring is a hollow tubular structure or a cup-shaped structure with a hollow structure and a top cover.

In some embodiments, when the light coupling area protection ring has a cup-shaped structure, its hollow structure and the top cover are bonded through an adhesive layer.

beneficial effects

The manufacturing method and packaging structure of the packaging structure according to the embodiment of the present invention can prevent the upper surface of the optical coupling area from being covered by the plastic sealing layer, protect the optical coupling interface in the optical coupling area from being contaminated by organic matter in the plastic sealing layer, and at the same time ensure The surface of the optical coupling area is pure, which is conducive to the subsequent optical coupling interface and the fiber array. Maintain high coupling efficiency.

Various aspects, features, advantages, etc. of the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The above aspects, features, advantages, etc. of the present invention will become clearer from the following detailed description in conjunction with the accompanying drawings.

Reference is made to the following description and to the accompanying drawings, specific embodiments of the invention are disclosed in detail and illustrate the manner in which the principles of the invention may be employed. It should be understood that embodiments of the invention are not thereby limited in scope. Embodiments of the present invention include numerous alterations, modifications and equivalents within the spirit and scope of the appended claims.

Features described and/or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in the other embodiments, or in place of features in the other embodiments .

It should be emphasized that the term "comprising" when used herein refers to the presence of features, integers, steps or components but does not exclude the presence or addition of one or more other features, integers, steps or components.

Description of the drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without exerting creative efforts.

FIG. 1 is a flow chart of a method for manufacturing a packaging structure according to an embodiment of the present invention.

2A-2C are schematic diagrams of the manufacturing process of a packaging structure manufacturing method according to an embodiment of the present invention.

FIG. 3 is a schematic plan view of a first semiconductor chip provided according to an embodiment of the present invention.

FIG. 4 is a schematic top structural view of a packaging structure with a semiconductor chip provided according to an embodiment of the present invention.

5A-5B are schematic diagrams of the manufacturing process of making a plastic sealing layer according to an embodiment of the present invention.

6A-6B are schematic diagrams of the manufacturing process of making a plastic sealing layer according to another embodiment of the present invention.

Figures 7-8 illustrate the manufacturing process of a method for manufacturing a packaging structure according to an embodiment of the present invention. Schematic diagram.

FIG. 9 is a schematic diagram of a chip-scale packaging structure according to an embodiment of the present invention.

FIG. 10 is a schematic diagram of the connection between a chip-scale packaging structure and a packaging substrate according to an embodiment of the present invention.

11A-11C are schematic diagrams of the manufacturing process of a method for manufacturing a packaging structure according to another embodiment of the present invention.

Embodiments of the invention

The above description is only an overview of the technical solution of the present invention. In order to have a clearer understanding of the technical means of the present invention, it can be implemented according to the content of the description, and in order to make the above and other objects, features and advantages of the present invention more obvious and understandable. , the following is a detailed description of the preferred embodiments, together with the accompanying drawings.

In the description of the present invention, it should be noted that, unless otherwise clearly stated and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. Connection, or integral connection; it can be mechanical connection, electrical connection or mutual communication; it can be direct connection, or indirect connection through an intermediary, it can be internal connection of two elements or interaction of two elements relation. The meaning of chip in this article may include bare chips. When it comes to method steps, the sequence illustrated in this article represents an exemplary solution, but does not represent a limitation on the sequence. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

In view of the problems that existing optoelectronic chip packaging methods cannot perform plastic packaging, poor reliability of packaging interconnection, large packaging area, and poor performance, embodiments of the present invention propose a packaging structure with an optical interconnection interface The manufacturing method adopts the method of stacking the electrical chip and the optical chip and then plastic packaging, which ensures the reliability of the package interconnection and at the same time realizes the protection of the optical fiber coupling interface.

In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments.

FIG. 1 is a flow chart of a method for manufacturing a packaging structure according to an embodiment of the present invention. The manufacturing method of the packaging structure includes:

S101, provide a semiconductor wafer, the semiconductor wafer includes a plurality of first semiconductor chips, each The first semiconductor chip has an opposite first surface and a second surface. A light coupling area and a non-light coupling area surrounding the light coupling area are provided on the first surface. A light coupling area is provided in the light coupling area. coupling interface;

S102. For each first semiconductor chip, provide at least one second semiconductor chip and a light coupling area protection ring corresponding to the first semiconductor chip, and connect the at least one second semiconductor chip and the light coupling area Protective rings are respectively fixed on the non-light coupling areas of the first surface of the first semiconductor chip, wherein the light coupling area protection rings surround the light coupling areas;

S103. Make a plastic encapsulation layer. The plastic encapsulation layer covers the at least one second semiconductor chip and the optical coupling area protection ring away from the outer surface of the optical coupling area. The plastic encapsulation layer does not cover the optical coupling area protection ring. The area occupied by the ring.

2A-2C are schematic diagrams of the manufacturing process of a packaging structure manufacturing method according to an embodiment of the present invention. FIG. 3 is a schematic plan view of a first semiconductor chip provided according to an embodiment of the present invention. FIG. 4 is a schematic top view of a packaging structure with a semiconductor chip according to an embodiment of the present invention. The embodiment of the present invention will be described in detail below with reference to FIGS. 2A-2C, 3 and 4.

In the embodiment of the present invention, for example, the first semiconductor chip 102 is an optical chip (photonic integrated circuit chip, PIC), where the optical chip uses photons as information carriers to process information and transmit data. , which may be a silicon-based optical chip, and the second semiconductor chip 103 is an electrical chip (electronic integrated circuit chip, EIC), wherein the electrical chip uses electrons as the information carrier to process information and transmit data, For example, silicon-based electrical chips, germanium-based electrical chips or compound semiconductor electrical chips, the integration of optical chips and electrical chips can be achieved by stacking the first semiconductor chip 102 and the second semiconductor chip 103 .

Illustratively, please refer to FIG. 2A . First, a first carrier substrate 200 and a semiconductor wafer 100 having a plurality of first semiconductor chips 102 located on the first carrier substrate 200 are provided. Each of the first semiconductor chips 102 is The chip 102 has an opposite first surface 102a and a second surface 102b, and the second surface 102b is temporarily bonded to the first carrier substrate 200 through a bonding glue 201.

Exemplarily, as shown in FIG. 3 , a light coupling region 1024 and a non-light coupling region 1025 surrounding the light coupling region 1024 are provided on the first surface 102 a of the first semiconductor chip 102 . The light coupling region 1024 An optical coupling interface 104 is provided inside, and the light provided by the external light source can pass through the optical fiber array. (Fiber Array, FA) is input into the optical coupling interface 104, for example, coupled into the first semiconductor chip 102 through a grating coupler in the optical coupling interface 104. It should be noted that in other embodiments, other optical interconnection interfaces or devices for transmitting optical signals may also be provided in the optical coupling interface 104 accordingly.

As shown in FIG. 2B to FIG. 2C and FIG. 4 , for each first semiconductor chip 102 , at least one second semiconductor chip 103 corresponding to the first semiconductor chip 102 and the optical coupling region protection ring 400 are provided, and The at least one second semiconductor chip 103 and the light coupling area protection ring 400 are respectively fixed on the non-light coupling area 1025 of the first surface 102a of the first semiconductor chip 102, for example, welding or other methods may be used. The optical coupling area protection ring 400 surrounds the optical coupling area 1024.

It should be noted that the embodiment of the present invention illustrates that one second semiconductor chip 103 is formed above the first semiconductor chip 102. In actual use, there may be more than one second semiconductor chip 103. For example, 2, 3, 4 or more, you can choose flexibly according to actual needs.

Since the plastic sealing layer and the like include organic materials, organic matter contacting the optical coupling area 1024 will cause organic matter residues, which will affect the coupling efficiency of the optical coupling interface 104 , resulting in serious light loss and affecting the operation of the first semiconductor chip 102 . In order to protect the optical coupling interface 104 in the optical coupling area 1024, embodiments of the present invention fabricate an optical coupling area protection ring 400 surrounding the optical coupling area 1024 around the optical coupling area 1024. For example, the light coupling area protection ring 400 is a hollow tubular structure or a hollow cup-shaped structure with a top cover. When the plastic sealing layer is subsequently made, due to the existence of the light coupling area protection ring 400, the light coupling area protection ring 400 can be Let the upper surface of the light coupling region not be covered by the plastic sealing layer, so that the plastic sealing layer only covers the at least one second semiconductor chip 103 and the outer surface of the light coupling region protection ring 400 away from the light coupling region 1024 and covers everything except The non-optical coupling area 1025 outside the area occupied by the optical coupling area protection ring 400 not only protects the optical coupling interface 104 in the optical coupling area 1024 from being contaminated by organic matter in the plastic layer, but also ensures the surface of the optical coupling area 1024 Pure, which helps the subsequent optical coupling interface 104 maintain a higher coupling efficiency with the optical fiber array. In addition, due to the existence of the optical coupling area protection ring 400, it is also avoided that in the traditional plastic packaging process, because the plastic layer covers the top of the optical coupling area 1024, the plastic layer needs to be laser-opened in the later stage to expose the light. Coupling region 1024.

It should be understood that if the optical coupling area protection ring 400 has a hollow cup-shaped structure with a top cover, At this time, after the production of the plastic sealing layer is completed, the top cover needs to be removed to expose the light coupling area 1024, so as to facilitate subsequent input of light from an external light source into the first semiconductor chip 102 through the light coupling interface 104. When the coupling area protection ring 400 has a cup-shaped structure, its hollow structure and the top cover are bonded through an adhesive layer. The adhesive layer can be removed by illumination, heating, etc., so that the optical coupling can be better protected. area 1024, and the optical coupling area 1024 can be subsequently packaged conveniently. If the light coupling area protection ring 400 has a hollow tubular structure, the light coupling area 1024 can be directly exposed.

Optionally, the optical coupling area protection ring 400 includes at least one of metal, ceramic, and silicon. Preferably, the optical coupling area protection ring 400 is made of a material with a thermal expansion coefficient and stiffness similar to those of the first semiconductor chip 102, such as ceramics or silicon. The light coupling area protection ring 400 is fixed on the non-light coupling area 1025 of the first surface 102a of the first semiconductor chip 102 by substrate bonding or colloid bonding.

Optionally, there may be no limit on the order in which the at least one second semiconductor chip 103 and the optical coupling region guard ring 400 are fixed.

Further, in a direction perpendicular to the first surface 102a, the light coupling area protection ring 400 is away from the top surface of the first surface 102a and the at least one second semiconductor chip 103 is away from the first surface. The top surface of 102a is flush.

As shown in FIG. 5A , in one embodiment of the present invention, the production of the plastic packaging layer includes: providing a plastic packaging mold 800 , the plastic packaging mold 800 has a plurality of first semiconductor chips 102 corresponding to each other in a one-to-one manner. In the U-shaped cavity 801, a gel-like plastic sealing material 1061, such as plastic sealant, etc., is provided at a preset area in each cavity 801; then, the plastic mold mold provided with the gel-like plastic sealing material 1061 is 800 is inverted and pressed on the side surface of the semiconductor wafer 100 facing away from the first carrier substrate 200 to form the plastic sealing layer 106 .

For example, the preset area refers to placing plastic glue in the area outside the corresponding light coupling area protection ring 400 and light coupling area 1024 of each cavity 801, and using the plastic glue to prevent random fluid movement. The characteristics of gravity drop can ensure that the plastic sealant is evenly filled into the gaps that need to be filled during the process of inverting and pressing the plastic mold 800 provided with the plastic sealant, and can also ensure that the optical coupling area 1024 The plastic sealant will not fall out, thereby protecting the optical coupling interface 104 in the optical coupling area 1024 from being contaminated by the plastic sealant. Subsequently, by heating and solidifying the plastic sealant, you can obtain A 3D chip stack packaging structure in which the optical coupling area 1024 is not covered by the plastic encapsulation layer 106 .

For example, the inner wall of the U-shaped cavity is smooth. For example, the internal structure of the U-shaped cavity can be designed according to the shape of the plastic sealing layer to be formed. This embodiment of the present invention is not limited here.

As shown in FIG. 5B , when the plastic mold 800 is inverted and pressed onto the semiconductor wafer 100 , the top surface of the optical coupling area protection ring 400 away from the first surface 102 a is in contact with the cavity. The bottom of 801 is attached, so that after the glue-like molding material 1061 is cured to form the molding layer 106, the light coupling area protection ring 400 is moved away from the The top surface of the first surface 102a is flush with the top surface of the plastic sealing layer 106 away from the first surface 102a. Moreover, in the embodiment of the present invention, the top surface of the optical coupling area protection ring 400 away from the first surface 102a is flush with the top surface of the at least one second semiconductor chip 103 away from the first surface 102a. , therefore, after the molding layer is formed, the top surface of the at least one second semiconductor chip 103 away from the first surface 102a can be exposed outside the molding layer 106 , which is not only beneficial to the volume of the packaging structure Being smaller is also beneficial to the heat dissipation of the at least one second semiconductor chip 103 . At the same time, it also saves the subsequent thinning process of the plastic encapsulation layer 106 to expose the top surface of the at least one second semiconductor chip 103 away from the first surface 102a, which is beneficial to the simplification of the manufacturing process and the manufacturing cost. of reduction.

As shown in Figure 6A, in another embodiment of the present invention, compared to Figure 5A, the preparation of the plastic sealing layer further includes: before disposing the gel-like plastic sealing material 1061, at the bottom of each cavity 801 A glue-repellent layer 901 is provided, and the glue-like plastic sealing material 1061 is provided at the preset area of the glue-repellent layer 901 .

As shown in FIG. 6B , when the plastic mold 800 is inverted and pressed onto the semiconductor wafer 100 , the top surface of the light coupling area protection ring 400 away from the first surface 102 a is in contact with the glue-repellent Layer 901 fit.

For example, the preset area refers to the area outside the corresponding light coupling area protection ring 400 and light coupling area 1024 of each cavity 801 in which the plastic sealant is disposed. For example, the material of the glue-repellent layer 901 is Teflon, etc. The glue-repellent layer 901 has glue-repellent properties, that is, it has repellency to colloids. In this way, the pre-position of the glue-repellent layer 901 Where the gel-like plastic sealing material 1061 is provided in an area Finally, after the plastic sealing mold 800 provided with plastic sealant is inverted and pressed, the plastic sealant will not adhere to the surface of the rubber-repellent layer 901 and the side wall near the bottom of the cavity 801, and it will also facilitate plastic sealing. After solidification, the glue is separated from the plastic sealing mold 800 .

7-8 are schematic diagrams of the manufacturing process of a method for manufacturing a packaging structure according to an embodiment of the present invention. FIG. 9 is a schematic diagram of a chip-scale packaging structure according to an embodiment of the present invention. FIG. 10 is a schematic diagram of the connection between a chip-scale packaging structure and a packaging substrate according to an embodiment of the present invention.

As shown in FIG. 7 , the method of manufacturing the packaging structure further includes: removing the plastic mold 800 after forming the plastic layer 106 .

As shown in FIG. 8 , the method of manufacturing the packaging structure further includes: debonding the first carrier substrate 200 after removing the plastic mold 800 .

Further, after the first carrier substrate 200 is debonded, the semiconductor wafer 100 is front-side cut, that is, the side of the semiconductor wafer 100 with the plastic sealing layer 106 is cut to obtain a plurality of separated chips. Package component 1000; As shown in FIG. 9 , each chip package component 1000 has a first semiconductor chip 102 , corresponding at least one second semiconductor chip 103 , an optical coupling area protection ring 400 and a plastic encapsulation layer 106 . At this time, due to the existence of the plastic sealing layer 106, the surface strength of the semiconductor wafer 100 is improved. Therefore, even when the semiconductor wafer 100 is front-cut, the semiconductor wafer 100 is less likely to be chipped due to cutting. risk of fragmentation.

Subsequently, as shown in FIG. 10 , each of the chip packaging components 1000 is mounted on the corresponding packaging substrate 700 . Specifically, the second conductive bump 1023 on the chip package assembly 1000 having at least one second conductive bump 1023 is bonded to an electrical connection point (not shown) on the packaging substrate 700 . According to actual needs, additional discrete devices such as capacitors, resistors, and inductors can be mounted or integrated on the packaging substrate 700 .

Continuing to refer to FIG. 10 , after at least one chip package component 1000 having second conductive bumps 1023 is bonded to electrical connection points on the packaging substrate 700 , the light guide structure 600 or the laser chip is mounted to the optical coupling interface. 104 on.

Illustratively, the light guide structure 600 is a fiber array (Fiber Array, FA). Optionally, the light guide structure 600 can be a prism, which guides the laser beam to the optical coupling interface 104 through a laser integration method. Specifically, the laser beam emitted by the laser chip passes through the lens and is incident on the prism, and the prism will The laser beam is coupled into the first semiconductor chip 102 through the optical coupling interface 104 .

Alternatively, the laser chip can be installed directly above the optical coupling interface 104 so that the laser beam emitted by the laser chip is aimed at the optical coupling interface 104 and the laser beam can be directly coupled to the first semiconductor chip 102 . Installing the laser chip above the optical coupling interface 104 can greatly simplify the device structure and improve the integration level.

As shown in FIGS. 11A to 11C , the manufacturing method of the packaging structure provided by the embodiment of the present invention further includes: fixing the at least one second semiconductor chip 103 and the optical coupling area protection ring 400 to the corresponding first Before forming on the non-light coupling area 1025 of the first surface 102a of the semiconductor chip 102, a plurality of conductive channels 1021 are made in each first semiconductor chip 102, and both sides of each conductive channel 1021 are They are respectively exposed from both sides of the first semiconductor chip 102 . The conductive channel 1021 can be formed by connecting multiple sections of conductive layers and manufactured separately in multiple processes.

Specifically, when the first semiconductor chip 102 is a silicon-based optical chip, a plurality of conductive vias are made in the substrate in the first semiconductor chip 102, and the conductive vias may be manufactured using "through silicon vias" (through silicon vias). Through Silicon Via (TSV) technology, TSV is a high-density packaging technology that is gradually replacing the current relatively mature wire bonding technology and is considered a fourth-generation packaging technology. TSV technology realizes the vertical electrical interconnection of through silicon holes by filling them with conductive materials such as copper, tungsten, and polysilicon. Through silicon via technology can reduce interconnect length, reduce signal delay, reduce capacitance/inductance through vertical interconnection, achieve low power consumption and high-speed communication between chips, increase bandwidth and achieve miniaturization of device integration. The TSV process can include deep silicon etching to form microvias or blind vias, deposition of insulating layers/barrier layers/seed layers, deep hole filling, chemical mechanical polishing, thinning, and redistribution lead preparation and other process technologies in optical chips. Process methods for forming conductive vias include but are not limited to laser etching, deep reactive ion etching, etc. After forming the conductive vias, processes such as deep hole filling are used to fill the conductive material (eg, metal). The present invention will not be described in detail here.

As shown in FIG. 11A , after both side surfaces of each conductive channel 1021 are exposed from the surface of the first semiconductor chip 102 , a first conductive channel is formed on the exposed side surface of each conductive channel 1021 . Bump1022. The first conductive bumps 1022 are, for example, pads (metal bumps) or solder balls. First conductive bumps 1022 are made on the exposed surface of each conductive channel 1021 to achieve The conductive channel 1021 is electrically connected to an external electrical connection point. The first surface 102 a of the first semiconductor chip 102 having at least one first conductive bump 1022 is temporarily bonded to the second carrier substrate 300 through the bonding glue 301 .

As shown in FIG. 11B , after the first semiconductor chip 102 having at least one first conductive bump 1022 is temporarily bonded to the second carrier substrate 300 , each of the conductive channels 1021 of the first semiconductor chip 102 Second conductive bumps 1023 are formed on the exposed other side surface.

As shown in FIG. 11C , after the second conductive bumps 1023 are formed on the other side surface of each conductive channel 1021 of the first semiconductor chip 102 where the conductive channels 1021 are exposed, the third conductive bump 1023 will be provided with at least one second conductive bump 1023 . The second surface 102b of a semiconductor chip 102 is temporarily bonded to the first carrier substrate 200 through the bonding glue 201, and the second carrier substrate 300 is debonded, thereby obtaining the first carrier substrate 200 as shown in FIG. 2A and a structure composed of a semiconductor wafer 100 including a plurality of first semiconductor chips.

Specifically, as shown in FIGS. 2A-2C , a plurality of third conductive bumps 1032 are made on one side of the second semiconductor chip 103 , wherein the plurality of third conductive bumps 1032 are connected to each of the The first conductive bumps 1022 on the conductive channel 1021 correspond one to one. Each third conductive bump 1032 is bonded to the corresponding first conductive bump 1022 to fixedly connect the second semiconductor chip 103 and the first semiconductor chip 102 together.

In this embodiment of the present invention, the second semiconductor chip 103 is soldered to the first semiconductor chip 102 using flip-chip soldering. Each third conductive bump 1032 is bonded to the corresponding first conductive bump 1022 by thermal compression bonding (TCB), reflow soldering, or laser bonding. Or metal direct bonding, etc. If the second semiconductor chip 103 has metal solder balls or metal bumps, an underfill process is also required. It should be understood that according to actual needs, multiple second semiconductor chips 103 can also be connected to the same first semiconductor chip 102.

It should be noted that the one-to-one correspondence between the plurality of third conductive bumps 1032 and the first conductive bumps 1022 on each of the conductive channels 1021 is for the purpose of one-to-one correspondence when the electrical signal terminals are connected, and is not completely It is limited to a one-to-one correspondence between the upper and lower projection positions. It should be understood that when the plurality of third conductive bumps 1032 also correspond to the first conductive bumps 1022 and lower projection positions on each of the conductive channels 1021, the first semiconductor chip 102 and the second semiconductor chip 103 Up and down vertically mutually The required connection distance is the shortest. Therefore, it is possible to avoid problems such as large impedance caused by too long connection lines between the first semiconductor chip 102 and the second semiconductor chip 103, which limits the current passing ability. , thereby reducing the losses in the upper and lower interconnections between the first semiconductor chip 102 and the second semiconductor chip 103 .

According to another aspect of the embodiment of the present invention, a packaging structure is also provided.

Continuing to refer to Figures 3 and 9, the packaging structure provided by the embodiment of the present invention includes: a first semiconductor chip 102, at least one second semiconductor chip 103, an optical coupling area protection ring 400, and a plastic sealing layer 106. The first semiconductor chip 102 has an opposite first surface 102a and a second surface 102b. A light coupling region 1024 and a non-light coupling region 1025 surrounding the light coupling region 1024 are provided on the first surface 102a. An optical coupling interface 104 is provided in the coupling area 1024; the at least one second semiconductor chip 103 and the optical coupling area protection ring 400 are respectively fixed on the non-optical coupling area 1025 of the first surface 102a; wherein, The light coupling area protection ring 400 surrounds the light coupling area 1024; the plastic encapsulation layer 106 covers the at least one second semiconductor chip 103 and the light coupling area protection ring 400 is away from the outside of the light coupling area 1024. surface and does not cover the area occupied by the light coupling area protection ring 400 .

Further, in a direction perpendicular to the first surface 102a, the light coupling area protection ring 400 is away from the top surface of the first surface 102a and the plastic sealing layer 106 is away from the top surface of the first surface 102a. Flush.

Further, the top surface of the at least one second semiconductor chip 103 away from the first surface 102a is exposed outside the plastic encapsulation layer 106, and in a direction perpendicular to the first surface 102a, the light coupling The top surface of the area protection ring 400 away from the first surface 102a is flush with the top surface of the at least one second semiconductor chip 103 away from the first surface 102a.

For example, the optical coupling area protection ring 400 is a hollow tubular structure or a hollow cup-shaped structure with a top cover.

It can be seen from the above that the manufacturing method and packaging structure of the packaging structure provided by the embodiment of the present invention include: providing a semiconductor wafer, the semiconductor wafer includes a plurality of first semiconductor chips, and a plurality of first semiconductor chips on the semiconductor wafer. The semiconductor chip forms an integral structure, and for each first semiconductor chip, an optical coupling area protection ring surrounding the optical coupling area is made on the non-optical coupling area of the first semiconductor chip, so that the non-optical coupling area of the first semiconductor chip When making a plastic sealing layer on the optical coupling area, make sure that the upper surface of the optical coupling area is not covered by the plastic sealing layer. This not only protects the optical coupling interface in the optical coupling area from being contaminated by organic matter in the plastic sealing layer, but also ensures that the surface of the optical coupling area is pure and has This is conducive to the subsequent optical coupling interface being able to maintain a high coupling efficiency with the optical fiber array.

Those skilled in the art should understand that what is disclosed above is only the implementation mode of the present invention. Of course, it cannot be used to limit the scope of the patent protection claimed by the present invention. Equivalent changes made according to the implementation mode of the present invention still belong to the rights of the present invention. The scope of the requirements.

Claims

A method of manufacturing a packaging structure, characterized in that the method includes:

A semiconductor wafer is provided, the semiconductor wafer includes a plurality of first semiconductor chips, each of the first semiconductor chips has an opposite first surface and a second surface, the first surface is provided with a light coupling region and surrounds the a non-optical coupling area of the optical coupling area, with an optical coupling interface provided in the optical coupling area;

For each of the first semiconductor chips, at least one second semiconductor chip and a light coupling area protection ring corresponding to the first semiconductor chip are provided, and the at least one second semiconductor chip and the light coupling area protection ring are respectively fixed on the non-light coupling area of the first surface of the first semiconductor chip, wherein the light coupling area protection ring surrounds the light coupling area;

Make a plastic sealing layer, the plastic sealing layer covers the at least one second semiconductor chip and the outer surface of the light coupling region protection ring away from the light coupling region, and the plastic sealing layer does not cover the light coupling region protection ring. occupy area.
The method of manufacturing a packaging structure according to claim 1, wherein in a direction perpendicular to the first surface, the light coupling area protection ring is away from the top surface of the first surface and the at least one A top surface of the second semiconductor chip away from the first surface is flush.
The method of manufacturing a packaging structure according to claim 2, wherein the manufacturing of the plastic sealing layer includes:

A plastic packaging mold is provided, and the plastic packaging mold has a plurality of U-shaped cavities corresponding to the plurality of first semiconductor chips,

Set a gel-like plastic sealing material at a preset area in each cavity;

The plastic mold provided with the glue-like plastic material is inverted and pressed on the first surface of the semiconductor wafer to form the plastic layer.
The method of making a packaging structure according to claim 3, wherein said making the plastic sealing layer further includes:

When the plastic mold is inverted and pressed onto the semiconductor wafer, the top surface of the light coupling area protection ring away from the first surface is in contact with the bottom of the cavity.
The method of making a packaging structure according to claim 3, wherein said making the plastic sealing layer further includes:

Before disposing the gel-like plastic sealing material, a gel-repellent layer is disposed at the bottom of each cavity, and The glue-like plastic sealing material is disposed in the preset area of the glue-repellent layer.
The method of manufacturing a packaging structure according to claim 5, wherein said manufacturing the plastic sealing layer further includes:

When the plastic mold is inverted and pressed onto the semiconductor wafer, the top surface of the light coupling area protection ring away from the first surface is attached to the glue-repellent layer.
The method for manufacturing a packaging structure according to claim 3, wherein the method further includes:

After forming the plastic sealing layer, the plastic sealing mold is removed.
The method of manufacturing a packaging structure according to claim 7, wherein the method further includes:

After removing the plastic mold, the semiconductor wafer is cut to obtain a plurality of separate chip packaging components. Each of the chip packaging components includes a first semiconductor chip, a corresponding at least one second semiconductor chip, an optical coupling Protective ring and plastic sealing layer.
The method for manufacturing a packaging structure according to claim 8, wherein the method further includes:

After obtaining a plurality of separate chip packaging components, each of the chip packaging components is mounted on a corresponding packaging substrate; and

Mount a light guide structure or a laser chip onto the optical coupling interface of the first semiconductor chip.
The method of manufacturing a packaging structure according to claim 1, wherein the method further includes:

Before fixing the at least one second semiconductor chip and the light-coupling area protective ring on the non-light-coupling area of the first surface of the corresponding first semiconductor chip, each first A plurality of conductive channels are made in the semiconductor chip, and both sides of each conductive channel are exposed from both sides of the first semiconductor chip.
The method of manufacturing a packaging structure according to claim 10, characterized in that the method further includes:

After exposing two side surfaces of each conductive channel from the surface of the first semiconductor chip, first conductive bumps are formed on the exposed one side surface of each conductive channel.
The method for manufacturing a packaging structure according to claim 11, wherein the method further includes:

After forming first conductive bumps on the exposed side surface of each conductive channel, temporarily bonding the side surface of each first semiconductor chip close to the first conductive bumps with the second carrier substrate. together; and,

A second conductive bump is formed on the exposed other side surface of each conductive channel of each first semiconductor chip.
The method of manufacturing a packaging structure according to claim 12, wherein the method further includes:

After forming a second conductive bump on the exposed other side surface of each conductive channel of each first semiconductor chip, place the first semiconductor chip close to the side surface of the second conductive bump. Temporarily bonding to the first carrier substrate; and,

The second carrier substrate is debonded.
The method of manufacturing a packaging structure as claimed in claim 1, characterized in that:

The first semiconductor chip is a photonic integrated circuit chip, and the second semiconductor chip is an electronic integrated circuit chip.
The method of manufacturing a packaging structure as claimed in claim 1, characterized in that:

The optical coupling area protection ring is a hollow tubular structure or a hollow cup-shaped structure with a top cover.
The method of manufacturing a packaging structure as claimed in claim 15, characterized in that:

The light coupling area protection ring includes any one of metal, ceramic, and silicon.
A packaging structure, characterized by including:

A first semiconductor chip, the first semiconductor chip has an opposite first surface and a second surface, a light coupling region and a non-light coupling region surrounding the light coupling region are provided on the first surface, the light coupling region There is an optical coupling interface in the area;

At least one second semiconductor chip and the light coupling area protection ring, the at least one second semiconductor chip and the light coupling area protection ring are respectively fixed on the non-light coupling area of the first surface, wherein, An optical coupling area protective ring surrounds the optical coupling area;

A plastic encapsulation layer covering the at least one second semiconductor chip and the optical coupling area to protect the The guard ring is away from the outer surface of the light coupling area and the plastic sealing layer does not cover the area occupied by the light coupling area guard ring.
The packaging structure according to claim 17, characterized in that:

In a direction perpendicular to the first surface, the top surface of the light coupling area protection ring away from the first surface is flush with the top surface of the plastic sealing layer away from the first surface.
The packaging structure according to claim 17, characterized in that:

The top surface of the at least one second semiconductor chip away from the first surface is exposed outside the plastic encapsulation layer, and in a direction perpendicular to the first surface, the light coupling area protection ring is away from the first surface. A top surface of one surface is flush with a top surface of the at least one second semiconductor chip away from the first surface.
The packaging structure according to claim 17, characterized in that:

The optical coupling area protection ring is a hollow tubular structure or a cup-shaped structure with a hollow structure and a top cover.
The packaging structure according to claim 20, characterized in that:

The light coupling area protection ring includes at least one material selected from metal, ceramic, and silicon.
The packaging structure of claim 20, wherein when the light coupling area protection ring has a cup-shaped structure, its hollow structure and the top cover are bonded through an adhesive layer.