WO2023174186A1 - Procédé de fabrication de structure d'encapsulation, et structure d'encapsulation - Google Patents

Procédé de fabrication de structure d'encapsulation, et structure d'encapsulation Download PDF

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Publication number
WO2023174186A1
WO2023174186A1 PCT/CN2023/080944 CN2023080944W WO2023174186A1 WO 2023174186 A1 WO2023174186 A1 WO 2023174186A1 CN 2023080944 W CN2023080944 W CN 2023080944W WO 2023174186 A1 WO2023174186 A1 WO 2023174186A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor chip
coupling area
light coupling
packaging structure
protection ring
Prior art date
Application number
PCT/CN2023/080944
Other languages
English (en)
Chinese (zh)
Inventor
王宏杰
孟怀宇
沈亦晨
Original Assignee
上海曦智科技有限公司
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Application filed by 上海曦智科技有限公司 filed Critical 上海曦智科技有限公司
Publication of WO2023174186A1 publication Critical patent/WO2023174186A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Definitions

  • the present application relates to the field of semiconductor packaging, and more specifically, to a manufacturing method and packaging structure of a packaging structure.
  • packaging structures with high integration density are becoming more and more important.
  • 3D packaging structures can be used to stack chips on top of each other.
  • the electrical chip (Electronic Integrated Circuit Chip, EIC, Electronic integrated chip) and the optical chip (Photonic Integrated Circuit Chip, PIC, Photonic integrated chip) among the existing silicon photonic chips adopt different wafer generation processes and adopt the chip level.
  • Interconnection (such as wire bonding or flip-chip interconnection) is used to realize the connection between the electrical chip (EIC) and the optical chip (PIC) to form a three-dimensional interconnection structure.
  • optical chip In the three-dimensional packaging of optical chips (PIC) and electrical chips (EIC), in order to avoid warping caused by thinning the optical chip (PIC), which may lead to misalignment or failure of the connection points between the optical chip (PIC) and the electrical chip (EIC), Or in order to make the packaging of the optical chip (PIC) and the electrical chip (EIC) have higher strength, it is usually necessary to form a plastic sealing layer on the surface of the optical chip (PIC).
  • the optical chip (PIC) has a fiber coupling interface for input light. Directly molding the surface of the optical chip (PIC) will cause damage to the fiber coupling interface, resulting in a significant increase in the insertion loss of the fiber coupling interface and affecting the optoelectronic chip. actual use.
  • Embodiments of the present application provide a manufacturing method and packaging structure of a packaging structure to solve the problem of using plastic packaging materials to fix photonic integrated circuit chips-electronic integrated circuit chips to improve packaging strength and avoid warping of the photonic integrated circuit chips.
  • the optical fiber coupling interface interface on the photonic integrated circuit chip forms a protection to prevent the optical coupling interface interface on the photonic integrated circuit chip from being contaminated by organic matter in the plastic sealing layer.
  • Embodiments of the present application provide a method for manufacturing a packaging structure and a packaging structure.
  • embodiments of the present application provide a method for manufacturing a packaging structure, including: providing a semiconductor wafer, the semiconductor wafer including a plurality of first semiconductor chips, each of the first semiconductor chips having an opposite first surface and A second surface, a light coupling area and a non-light coupling area surrounding the light coupling area are provided on the first surface, and an light coupling interface is provided in the light coupling area; for each of the first semiconductor chips, Provide at least one second semiconductor chip and a light coupling area protection ring corresponding to the first semiconductor chip, and fix the at least one second semiconductor chip and the light coupling area protection ring to all parts of the first semiconductor chip respectively.
  • the light coupling area protective ring surrounds the light coupling area; a plastic encapsulation layer is produced, and the plastic encapsulation layer covers the at least one second semiconductor chip and the The light coupling area protection ring is away from the outer surface of the light coupling area and the plastic sealing layer does not cover the area other than the light coupling area protection ring.
  • the light coupling region protection ring in a direction perpendicular to the first surface, is away from a top surface of the first surface and the at least one second semiconductor chip is away from a top surface of the first surface.
  • the top surface is flush.
  • the manufacturing of the plastic packaging layer includes: providing a plastic packaging mold, the plastic packaging mold having a plurality of U-shaped cavities corresponding to the plurality of first semiconductor chips, and in each of the cavities A gel-like plastic sealing material is provided in a preset area of the body; the plastic sealing mold provided with the gel-like plastic sealing material is inverted and pressed on the first surface of the semiconductor wafer to form the plastic sealing layer.
  • the preparation of the plastic sealing layer further includes: when the plastic sealing mold is inverted and pressed onto the semiconductor wafer, the top surface of the light coupling area protection ring away from the first surface and The bottom of the cavity fits.
  • the preparation of the plastic sealing layer further includes: before setting the gel-like plastic sealing material Before, a glue-repellent layer is provided at the bottom of each cavity, and the glue-like plastic sealing material is provided in the preset area of the glue-repellent layer.
  • the preparation of the plastic sealing layer further includes: when the plastic sealing mold is inverted and pressed onto the semiconductor wafer, the top surface of the light coupling area protection ring away from the first surface and The glue-repellent layer is attached.
  • the molding mold is removed.
  • the semiconductor wafer is cut to obtain a plurality of separate chip packaging components.
  • Each of the chip packaging components includes a first semiconductor chip, a corresponding at least one first semiconductor chip, and a first semiconductor chip. 2.
  • each of the chip packaging components is mounted on a corresponding packaging substrate; and a light guide structure or a laser chip is mounted on the first semiconductor on the optical coupling interface of the chip.
  • a plurality of conductive channels are made in each first semiconductor chip, and both sides of each conductive channel are exposed from both sides of the first semiconductor chip.
  • first conductive bumps are formed on the exposed one side surface of each conductive channel.
  • the side surface of each first semiconductor chip close to the first conductive bump is connected to a first conductive bump.
  • the two carrier substrates are temporarily bonded; and, second conductive bumps are formed on the exposed other side surface of each conductive channel of each first semiconductor chip.
  • the first semiconductor chip is placed close to the second conductive bump.
  • One side surface of the bump is temporarily bonded to the first carrier substrate; and the second carrier substrate is debonded.
  • the first semiconductor chip is a photonic integrated circuit chip
  • the second semiconductor chip is an electronic integrated circuit chip.
  • the light coupling area protection ring is a hollow tubular structure or a hollow cup-shaped structure with a top cover.
  • the light coupling region protection ring includes at least one of metal, ceramic, and silicon.
  • embodiments of the present application further provide a packaging structure, including: a first semiconductor chip, the first semiconductor chip having an opposite first surface and a second surface, and an optical coupling region is provided on the first surface. and a non-optical coupling area surrounding the optical coupling area, an optical coupling interface is provided in the optical coupling area; at least one second semiconductor chip and an optical coupling area protection ring, the at least one second semiconductor chip and the optical coupling area Coupling area protection rings are respectively fixed on the non-light coupling areas of the first surface, wherein the light coupling area protection rings surround the light coupling area; a plastic sealing layer covers the at least one The second semiconductor chip and the light coupling area protection ring are away from the outer surface of the light coupling area and the plastic sealing layer does not cover the area occupied by the light coupling area protection ring.
  • the top surface of the light coupling area protection ring away from the first surface is flush with the top surface of the plastic sealing layer away from the first surface.
  • the top surface of the at least one second semiconductor chip away from the first surface is exposed outside the plastic encapsulation layer, and in a direction perpendicular to the first surface, the light coupling region A top surface of the protective ring away from the first surface is flush with a top surface of the at least one second semiconductor chip away from the first surface.
  • the light coupling area protection ring is a hollow tubular structure or a cup-shaped structure with a hollow structure and a top cover.
  • the light coupling region protection ring includes at least one of metal, ceramic, and silicon.
  • the light coupling area protection ring when the light coupling area protection ring has a cup-shaped structure, its hollow structure and the top cover are bonded through an adhesive layer.
  • the manufacturing method and packaging structure of the packaging structure according to the embodiment of the present invention can prevent the upper surface of the optical coupling area from being covered by the plastic sealing layer, protect the optical coupling interface in the optical coupling area from being contaminated by organic matter in the plastic sealing layer, and at the same time ensure The surface of the optical coupling area is pure, which is conducive to the subsequent optical coupling interface and the fiber array. Maintain high coupling efficiency.
  • FIG. 1 is a flow chart of a method for manufacturing a packaging structure according to an embodiment of the present invention.
  • 2A-2C are schematic diagrams of the manufacturing process of a packaging structure manufacturing method according to an embodiment of the present invention.
  • FIG. 3 is a schematic plan view of a first semiconductor chip provided according to an embodiment of the present invention.
  • FIG. 4 is a schematic top structural view of a packaging structure with a semiconductor chip provided according to an embodiment of the present invention.
  • 5A-5B are schematic diagrams of the manufacturing process of making a plastic sealing layer according to an embodiment of the present invention.
  • 6A-6B are schematic diagrams of the manufacturing process of making a plastic sealing layer according to another embodiment of the present invention.
  • Figures 7-8 illustrate the manufacturing process of a method for manufacturing a packaging structure according to an embodiment of the present invention. Schematic diagram.
  • FIG. 9 is a schematic diagram of a chip-scale packaging structure according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of the connection between a chip-scale packaging structure and a packaging substrate according to an embodiment of the present invention.
  • 11A-11C are schematic diagrams of the manufacturing process of a method for manufacturing a packaging structure according to another embodiment of the present invention.
  • connection should be understood in a broad sense.
  • connection or integral connection; it can be mechanical connection, electrical connection or mutual communication; it can be direct connection, or indirect connection through an intermediary, it can be internal connection of two elements or interaction of two elements relation.
  • the meaning of chip in this article may include bare chips.
  • embodiments of the present invention propose a packaging structure with an optical interconnection interface
  • the manufacturing method adopts the method of stacking the electrical chip and the optical chip and then plastic packaging, which ensures the reliability of the package interconnection and at the same time realizes the protection of the optical fiber coupling interface.
  • FIG. 1 is a flow chart of a method for manufacturing a packaging structure according to an embodiment of the present invention.
  • the manufacturing method of the packaging structure includes:
  • the semiconductor wafer includes a plurality of first semiconductor chips, each The first semiconductor chip has an opposite first surface and a second surface. A light coupling area and a non-light coupling area surrounding the light coupling area are provided on the first surface. A light coupling area is provided in the light coupling area. coupling interface;
  • each first semiconductor chip For each first semiconductor chip, provide at least one second semiconductor chip and a light coupling area protection ring corresponding to the first semiconductor chip, and connect the at least one second semiconductor chip and the light coupling area Protective rings are respectively fixed on the non-light coupling areas of the first surface of the first semiconductor chip, wherein the light coupling area protection rings surround the light coupling areas;
  • the plastic encapsulation layer covers the at least one second semiconductor chip and the optical coupling area protection ring away from the outer surface of the optical coupling area.
  • the plastic encapsulation layer does not cover the optical coupling area protection ring. The area occupied by the ring.
  • FIGS. 2A-2C are schematic diagrams of the manufacturing process of a packaging structure manufacturing method according to an embodiment of the present invention.
  • FIG. 3 is a schematic plan view of a first semiconductor chip provided according to an embodiment of the present invention.
  • FIG. 4 is a schematic top view of a packaging structure with a semiconductor chip according to an embodiment of the present invention. The embodiment of the present invention will be described in detail below with reference to FIGS. 2A-2C, 3 and 4.
  • the first semiconductor chip 102 is an optical chip (photonic integrated circuit chip, PIC), where the optical chip uses photons as information carriers to process information and transmit data.
  • PIC photonic integrated circuit chip
  • the second semiconductor chip 103 is an electrical chip (electronic integrated circuit chip, EIC), wherein the electrical chip uses electrons as the information carrier to process information and transmit data
  • EIC electronic integrated circuit chip
  • silicon-based electrical chips, germanium-based electrical chips or compound semiconductor electrical chips the integration of optical chips and electrical chips can be achieved by stacking the first semiconductor chip 102 and the second semiconductor chip 103 .
  • a first carrier substrate 200 and a semiconductor wafer 100 having a plurality of first semiconductor chips 102 located on the first carrier substrate 200 are provided.
  • Each of the first semiconductor chips 102 is The chip 102 has an opposite first surface 102a and a second surface 102b, and the second surface 102b is temporarily bonded to the first carrier substrate 200 through a bonding glue 201.
  • a light coupling region 1024 and a non-light coupling region 1025 surrounding the light coupling region 1024 are provided on the first surface 102 a of the first semiconductor chip 102 .
  • the light coupling region 1024 An optical coupling interface 104 is provided inside, and the light provided by the external light source can pass through the optical fiber array. (Fiber Array, FA) is input into the optical coupling interface 104, for example, coupled into the first semiconductor chip 102 through a grating coupler in the optical coupling interface 104. It should be noted that in other embodiments, other optical interconnection interfaces or devices for transmitting optical signals may also be provided in the optical coupling interface 104 accordingly.
  • each first semiconductor chip 102 at least one second semiconductor chip 103 corresponding to the first semiconductor chip 102 and the optical coupling region protection ring 400 are provided, and The at least one second semiconductor chip 103 and the light coupling area protection ring 400 are respectively fixed on the non-light coupling area 1025 of the first surface 102a of the first semiconductor chip 102, for example, welding or other methods may be used.
  • the optical coupling area protection ring 400 surrounds the optical coupling area 1024.
  • the embodiment of the present invention illustrates that one second semiconductor chip 103 is formed above the first semiconductor chip 102.
  • the plastic sealing layer and the like include organic materials, organic matter contacting the optical coupling area 1024 will cause organic matter residues, which will affect the coupling efficiency of the optical coupling interface 104 , resulting in serious light loss and affecting the operation of the first semiconductor chip 102 .
  • embodiments of the present invention fabricate an optical coupling area protection ring 400 surrounding the optical coupling area 1024 around the optical coupling area 1024.
  • the light coupling area protection ring 400 is a hollow tubular structure or a hollow cup-shaped structure with a top cover.
  • the light coupling area protection ring 400 can be Let the upper surface of the light coupling region not be covered by the plastic sealing layer, so that the plastic sealing layer only covers the at least one second semiconductor chip 103 and the outer surface of the light coupling region protection ring 400 away from the light coupling region 1024 and covers everything except
  • the non-optical coupling area 1025 outside the area occupied by the optical coupling area protection ring 400 not only protects the optical coupling interface 104 in the optical coupling area 1024 from being contaminated by organic matter in the plastic layer, but also ensures the surface of the optical coupling area 1024 Pure, which helps the subsequent optical coupling interface 104 maintain a higher coupling efficiency with the optical fiber array.
  • the optical coupling area protection ring 400 has a hollow cup-shaped structure with a top cover
  • the top cover needs to be removed to expose the light coupling area 1024, so as to facilitate subsequent input of light from an external light source into the first semiconductor chip 102 through the light coupling interface 104.
  • the coupling area protection ring 400 has a cup-shaped structure
  • its hollow structure and the top cover are bonded through an adhesive layer.
  • the adhesive layer can be removed by illumination, heating, etc., so that the optical coupling can be better protected.
  • area 1024, and the optical coupling area 1024 can be subsequently packaged conveniently. If the light coupling area protection ring 400 has a hollow tubular structure, the light coupling area 1024 can be directly exposed.
  • the optical coupling area protection ring 400 includes at least one of metal, ceramic, and silicon.
  • the optical coupling area protection ring 400 is made of a material with a thermal expansion coefficient and stiffness similar to those of the first semiconductor chip 102, such as ceramics or silicon.
  • the light coupling area protection ring 400 is fixed on the non-light coupling area 1025 of the first surface 102a of the first semiconductor chip 102 by substrate bonding or colloid bonding.
  • the light coupling area protection ring 400 is away from the top surface of the first surface 102a and the at least one second semiconductor chip 103 is away from the first surface.
  • the top surface of 102a is flush.
  • 5A-5B are schematic diagrams of the manufacturing process of making a plastic sealing layer according to an embodiment of the present invention.
  • the production of the plastic packaging layer includes: providing a plastic packaging mold 800 , the plastic packaging mold 800 has a plurality of first semiconductor chips 102 corresponding to each other in a one-to-one manner.
  • a gel-like plastic sealing material 1061 such as plastic sealant, etc., is provided at a preset area in each cavity 801; then, the plastic mold mold provided with the gel-like plastic sealing material 1061 is 800 is inverted and pressed on the side surface of the semiconductor wafer 100 facing away from the first carrier substrate 200 to form the plastic sealing layer 106 .
  • the preset area refers to placing plastic glue in the area outside the corresponding light coupling area protection ring 400 and light coupling area 1024 of each cavity 801, and using the plastic glue to prevent random fluid movement.
  • the characteristics of gravity drop can ensure that the plastic sealant is evenly filled into the gaps that need to be filled during the process of inverting and pressing the plastic mold 800 provided with the plastic sealant, and can also ensure that the optical coupling area 1024 The plastic sealant will not fall out, thereby protecting the optical coupling interface 104 in the optical coupling area 1024 from being contaminated by the plastic sealant. Subsequently, by heating and solidifying the plastic sealant, you can obtain A 3D chip stack packaging structure in which the optical coupling area 1024 is not covered by the plastic encapsulation layer 106 .
  • the inner wall of the U-shaped cavity is smooth.
  • the internal structure of the U-shaped cavity can be designed according to the shape of the plastic sealing layer to be formed. This embodiment of the present invention is not limited here.
  • the top surface of the optical coupling area protection ring 400 away from the first surface 102 a is in contact with the cavity.
  • the bottom of 801 is attached, so that after the glue-like molding material 1061 is cured to form the molding layer 106, the light coupling area protection ring 400 is moved away from the The top surface of the first surface 102a is flush with the top surface of the plastic sealing layer 106 away from the first surface 102a.
  • the top surface of the optical coupling area protection ring 400 away from the first surface 102a is flush with the top surface of the at least one second semiconductor chip 103 away from the first surface 102a.
  • the top surface of the at least one second semiconductor chip 103 away from the first surface 102a can be exposed outside the molding layer 106 , which is not only beneficial to the volume of the packaging structure Being smaller is also beneficial to the heat dissipation of the at least one second semiconductor chip 103 .
  • it also saves the subsequent thinning process of the plastic encapsulation layer 106 to expose the top surface of the at least one second semiconductor chip 103 away from the first surface 102a, which is beneficial to the simplification of the manufacturing process and the manufacturing cost. of reduction.
  • 6A-6B are schematic diagrams of the manufacturing process of making a plastic sealing layer according to another embodiment of the present invention.
  • the preparation of the plastic sealing layer further includes: before disposing the gel-like plastic sealing material 1061, at the bottom of each cavity 801 A glue-repellent layer 901 is provided, and the glue-like plastic sealing material 1061 is provided at the preset area of the glue-repellent layer 901 .
  • the preset area refers to the area outside the corresponding light coupling area protection ring 400 and light coupling area 1024 of each cavity 801 in which the plastic sealant is disposed.
  • the material of the glue-repellent layer 901 is Teflon, etc.
  • the glue-repellent layer 901 has glue-repellent properties, that is, it has repellency to colloids. In this way, the pre-position of the glue-repellent layer 901 Where the gel-like plastic sealing material 1061 is provided in an area
  • the plastic sealing mold 800 provided with plastic sealant is inverted and pressed, the plastic sealant will not adhere to the surface of the rubber-repellent layer 901 and the side wall near the bottom of the cavity 801, and it will also facilitate plastic sealing. After solidification, the glue is separated from the plastic sealing mold 800 .
  • FIGS. 7-8 are schematic diagrams of the manufacturing process of a method for manufacturing a packaging structure according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a chip-scale packaging structure according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of the connection between a chip-scale packaging structure and a packaging substrate according to an embodiment of the present invention.
  • the method of manufacturing the packaging structure further includes: removing the plastic mold 800 after forming the plastic layer 106 .
  • the method of manufacturing the packaging structure further includes: debonding the first carrier substrate 200 after removing the plastic mold 800 .
  • each chip package component 1000 has a first semiconductor chip 102 , corresponding at least one second semiconductor chip 103 , an optical coupling area protection ring 400 and a plastic encapsulation layer 106 .
  • the surface strength of the semiconductor wafer 100 is improved. Therefore, even when the semiconductor wafer 100 is front-cut, the semiconductor wafer 100 is less likely to be chipped due to cutting. risk of fragmentation.
  • each of the chip packaging components 1000 is mounted on the corresponding packaging substrate 700 .
  • the second conductive bump 1023 on the chip package assembly 1000 having at least one second conductive bump 1023 is bonded to an electrical connection point (not shown) on the packaging substrate 700 .
  • additional discrete devices such as capacitors, resistors, and inductors can be mounted or integrated on the packaging substrate 700 .
  • the light guide structure 600 or the laser chip is mounted to the optical coupling interface. 104 on.
  • the light guide structure 600 is a fiber array (Fiber Array, FA).
  • the light guide structure 600 can be a prism, which guides the laser beam to the optical coupling interface 104 through a laser integration method. Specifically, the laser beam emitted by the laser chip passes through the lens and is incident on the prism, and the prism will The laser beam is coupled into the first semiconductor chip 102 through the optical coupling interface 104 .
  • the laser chip can be installed directly above the optical coupling interface 104 so that the laser beam emitted by the laser chip is aimed at the optical coupling interface 104 and the laser beam can be directly coupled to the first semiconductor chip 102 .
  • Installing the laser chip above the optical coupling interface 104 can greatly simplify the device structure and improve the integration level.
  • 11A-11C are schematic diagrams of the manufacturing process of a method for manufacturing a packaging structure according to another embodiment of the present invention.
  • the manufacturing method of the packaging structure provided by the embodiment of the present invention further includes: fixing the at least one second semiconductor chip 103 and the optical coupling area protection ring 400 to the corresponding first Before forming on the non-light coupling area 1025 of the first surface 102a of the semiconductor chip 102, a plurality of conductive channels 1021 are made in each first semiconductor chip 102, and both sides of each conductive channel 1021 are They are respectively exposed from both sides of the first semiconductor chip 102 .
  • the conductive channel 1021 can be formed by connecting multiple sections of conductive layers and manufactured separately in multiple processes.
  • the first semiconductor chip 102 is a silicon-based optical chip
  • a plurality of conductive vias are made in the substrate in the first semiconductor chip 102, and the conductive vias may be manufactured using "through silicon vias" (through silicon vias).
  • through silicon vias through silicon vias.
  • TSV Through Silicon Via
  • TSV is a high-density packaging technology that is gradually replacing the current relatively mature wire bonding technology and is considered a fourth-generation packaging technology.
  • TSV technology realizes the vertical electrical interconnection of through silicon holes by filling them with conductive materials such as copper, tungsten, and polysilicon.
  • the TSV process can include deep silicon etching to form microvias or blind vias, deposition of insulating layers/barrier layers/seed layers, deep hole filling, chemical mechanical polishing, thinning, and redistribution lead preparation and other process technologies in optical chips.
  • Process methods for forming conductive vias include but are not limited to laser etching, deep reactive ion etching, etc. After forming the conductive vias, processes such as deep hole filling are used to fill the conductive material (eg, metal). The present invention will not be described in detail here.
  • a first conductive channel is formed on the exposed side surface of each conductive channel 1021 .
  • the first conductive bumps 1022 are, for example, pads (metal bumps) or solder balls.
  • First conductive bumps 1022 are made on the exposed surface of each conductive channel 1021 to achieve The conductive channel 1021 is electrically connected to an external electrical connection point.
  • the first surface 102 a of the first semiconductor chip 102 having at least one first conductive bump 1022 is temporarily bonded to the second carrier substrate 300 through the bonding glue 301 .
  • each of the conductive channels 1021 of the first semiconductor chip 102 Second conductive bumps 1023 are formed on the exposed other side surface.
  • the third conductive bump 1023 will be provided with at least one second conductive bump 1023 .
  • the second surface 102b of a semiconductor chip 102 is temporarily bonded to the first carrier substrate 200 through the bonding glue 201, and the second carrier substrate 300 is debonded, thereby obtaining the first carrier substrate 200 as shown in FIG. 2A and a structure composed of a semiconductor wafer 100 including a plurality of first semiconductor chips.
  • a plurality of third conductive bumps 1032 are made on one side of the second semiconductor chip 103 , wherein the plurality of third conductive bumps 1032 are connected to each of the The first conductive bumps 1022 on the conductive channel 1021 correspond one to one.
  • Each third conductive bump 1032 is bonded to the corresponding first conductive bump 1022 to fixedly connect the second semiconductor chip 103 and the first semiconductor chip 102 together.
  • the second semiconductor chip 103 is soldered to the first semiconductor chip 102 using flip-chip soldering.
  • Each third conductive bump 1032 is bonded to the corresponding first conductive bump 1022 by thermal compression bonding (TCB), reflow soldering, or laser bonding. Or metal direct bonding, etc. If the second semiconductor chip 103 has metal solder balls or metal bumps, an underfill process is also required. It should be understood that according to actual needs, multiple second semiconductor chips 103 can also be connected to the same first semiconductor chip 102.
  • the one-to-one correspondence between the plurality of third conductive bumps 1032 and the first conductive bumps 1022 on each of the conductive channels 1021 is for the purpose of one-to-one correspondence when the electrical signal terminals are connected, and is not completely It is limited to a one-to-one correspondence between the upper and lower projection positions. It should be understood that when the plurality of third conductive bumps 1032 also correspond to the first conductive bumps 1022 and lower projection positions on each of the conductive channels 1021, the first semiconductor chip 102 and the second semiconductor chip 103 Up and down vertically mutually The required connection distance is the shortest.
  • a packaging structure is also provided.
  • the packaging structure provided by the embodiment of the present invention includes: a first semiconductor chip 102, at least one second semiconductor chip 103, an optical coupling area protection ring 400, and a plastic sealing layer 106.
  • the first semiconductor chip 102 has an opposite first surface 102a and a second surface 102b.
  • a light coupling region 1024 and a non-light coupling region 1025 surrounding the light coupling region 1024 are provided on the first surface 102a.
  • An optical coupling interface 104 is provided in the coupling area 1024; the at least one second semiconductor chip 103 and the optical coupling area protection ring 400 are respectively fixed on the non-optical coupling area 1025 of the first surface 102a; wherein, The light coupling area protection ring 400 surrounds the light coupling area 1024; the plastic encapsulation layer 106 covers the at least one second semiconductor chip 103 and the light coupling area protection ring 400 is away from the outside of the light coupling area 1024. surface and does not cover the area occupied by the light coupling area protection ring 400 .
  • the light coupling area protection ring 400 is away from the top surface of the first surface 102a and the plastic sealing layer 106 is away from the top surface of the first surface 102a. Flush.
  • the top surface of the at least one second semiconductor chip 103 away from the first surface 102a is exposed outside the plastic encapsulation layer 106, and in a direction perpendicular to the first surface 102a, the light coupling
  • the top surface of the area protection ring 400 away from the first surface 102a is flush with the top surface of the at least one second semiconductor chip 103 away from the first surface 102a.
  • the optical coupling area protection ring 400 is a hollow tubular structure or a hollow cup-shaped structure with a top cover.
  • the optical coupling area protection ring 400 includes at least one of metal, ceramic, and silicon.
  • the optical coupling area protection ring 400 is made of a material with a thermal expansion coefficient and stiffness similar to those of the first semiconductor chip 102, such as ceramics or silicon.
  • the light coupling area protection ring 400 is fixed on the non-light coupling area 1025 of the first surface 102a of the first semiconductor chip 102 by substrate bonding or colloid bonding.
  • the manufacturing method and packaging structure of the packaging structure include: providing a semiconductor wafer, the semiconductor wafer includes a plurality of first semiconductor chips, and a plurality of first semiconductor chips on the semiconductor wafer.
  • the semiconductor chip forms an integral structure, and for each first semiconductor chip, an optical coupling area protection ring surrounding the optical coupling area is made on the non-optical coupling area of the first semiconductor chip, so that the non-optical coupling area of the first semiconductor chip
  • a plastic sealing layer on the optical coupling area make sure that the upper surface of the optical coupling area is not covered by the plastic sealing layer.
  • optical coupling interface in the optical coupling area not only protects the optical coupling interface in the optical coupling area from being contaminated by organic matter in the plastic sealing layer, but also ensures that the surface of the optical coupling area is pure and has This is conducive to the subsequent optical coupling interface being able to maintain a high coupling efficiency with the optical fiber array.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Led Device Packages (AREA)
  • Optical Couplings Of Light Guides (AREA)

Abstract

Sont divulgués un procédé de fabrication d'une structure d'encapsulation, et une structure d'encapsulation. Le procédé consiste à : fournir un dé semi-conducteur, le dé semi-conducteur comprenant une pluralité de premières puces semi-conductrices, et la pluralité de premières puces semi-conductrices sur le dé semi-conducteur formant une structure intégrale ; et pour chacune des premières puces semi-conductrices, fabriquer, sur une zone de couplage non optique de la première puce semi-conductrice, une bague de protection de zone de couplage optique entourant une zone de couplage optique, de telle sorte que lorsqu'une couche d'encapsulation en plastique est fabriquée sur la zone de couplage non optique de la première puce semi-conductrice, la surface supérieure de la zone de couplage optique n'est pas recouverte par la couche d'encapsulation en plastique, une interface de couplage optique dans la zone de couplage optique est protégée contre une contamination par une matière organique dans la couche d'encapsulation en plastique, et la pureté de surface de la zone de couplage optique est assurée, ce qui facilite le maintien par l'interface de couplage optique d'une efficacité de couplage élevée avec un réseau de fibres optiques dans le processus ultérieur.
PCT/CN2023/080944 2022-03-18 2023-03-10 Procédé de fabrication de structure d'encapsulation, et structure d'encapsulation WO2023174186A1 (fr)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180180808A1 (en) * 2016-12-22 2018-06-28 Oracle International Corporation Wafer-level packaged optoelectronic module
CN112034567A (zh) * 2020-09-04 2020-12-04 华进半导体封装先导技术研发中心有限公司 一种光电芯片封装结构及其封装方法
CN113241329A (zh) * 2021-04-30 2021-08-10 杭州光智元科技有限公司 光电芯片的三维封装方法及封装结构
US20210313304A1 (en) * 2020-04-01 2021-10-07 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of forming the same
CN113960715A (zh) * 2021-12-23 2022-01-21 杭州光智元科技有限公司 封装结构的制作方法及封装结构
CN114823358A (zh) * 2022-03-18 2022-07-29 上海曦智科技有限公司 封装结构的制作方法及封装结构

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180180808A1 (en) * 2016-12-22 2018-06-28 Oracle International Corporation Wafer-level packaged optoelectronic module
US20210313304A1 (en) * 2020-04-01 2021-10-07 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of forming the same
CN112034567A (zh) * 2020-09-04 2020-12-04 华进半导体封装先导技术研发中心有限公司 一种光电芯片封装结构及其封装方法
CN113241329A (zh) * 2021-04-30 2021-08-10 杭州光智元科技有限公司 光电芯片的三维封装方法及封装结构
CN113960715A (zh) * 2021-12-23 2022-01-21 杭州光智元科技有限公司 封装结构的制作方法及封装结构
CN114823358A (zh) * 2022-03-18 2022-07-29 上海曦智科技有限公司 封装结构的制作方法及封装结构

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