CN103000648B - Large chip sized package and manufacture method thereof - Google Patents

Abstract

A large chip size package and a manufacturing method thereof belong to the technical field of sensors. An optical interaction area is provided in the center above the silicon substrate on the first surface of the wafer, and a metal interconnection structure is connected to the side where the optical interaction area is provided, and the I/O around the optical interaction area on the silicon substrate is connected through the metal interconnection structure to the electrode pad; the surface of the metal interconnection is provided with a protective layer, and a stepped protrusion or groove structure is formed on the protective layer; the first surface of the wafer is bonded to the glass sheet, and the glass sheet and the crystal A cavity is formed between the circles; the second surface of the wafer is provided with TSV holes, and the electrode pads are connected to the pads on the second surface of the wafer through the TSV holes through the silicon substrate, and are sequentially fabricated on the walls of the TSV holes It is used as a passivation layer and a metal lining, and the polymer material is used to fill the TSV hole; a solder mask is made on the second surface of the wafer, and solder balls are made on the pad. The invention improves the delamination problem between the glass and the silicon substrate in the existing package structure, and improves the package reliability.

Description

Large chip size package and manufacturing method thereof

technical field

The present invention relates to a large chip size package (CSP) and a method of manufacturing the same. The packaging structure and manufacturing method described above can be preferably used for image sensors or MEMS devices.

Background technique

Chip Scale Package (CSP) is a new generation of chip packaging technology, and its technical performance has been improved again. CSP packaging can make the ratio of chip area to package area exceed 1:1.14, which is quite close to the ideal situation of 1:1. The absolute size is only 32 square millimeters, about 1/3 of ordinary BGA, which is only equivalent to TSOP memory 1/6 of the chip area. Compared with the BGA package, the CSP package can increase the storage capacity by three times in the same space. The purpose of CSP is to use large chips (chips with more functions, better performance, and more complex chips) to replace the previous small chips, while the package occupies the same or smaller area of the printed board. It is precisely because of the small and thin package of CSP products that it has rapidly gained application in hand-held mobile electronic devices. CSP not only significantly reduces the size of the package, reduces the packaging cost, improves the packaging efficiency, but also meets the requirements of high-density packaging; at the same time, due to the short data transmission path and high stability, this package can reduce energy consumption. It also improves the speed and stability of data transmission.

An image sensor is a semiconductor module, a device that converts an optical image into an electronic signal that can be used for further processing or digitized and stored, or used to transfer the image to another display device for display Wait. It is widely used in digital cameras and other electro-optical devices. Image sensors are now mainly divided into charge-coupled devices (CCD) and CMOS image sensors (CIS, CMOSImageSensor). Although CCD image sensors are superior to CMOS image sensors in terms of image quality and noise, CMOS sensors can be manufactured with traditional semiconductor production techniques at lower production costs. At the same time, due to the relatively small number of components used and the short signal transmission distance, CMOS image sensors have the advantages of low power consumption, reduced capacitance, inductance, and parasitic delay.

Figure 1 shows a schematic diagram of a conventional CMOS image sensor (CIS) package. The shown CMOS sensor generally includes: a ceramic substrate 2 , an integrated circuit 4 (IC) mounted on the top surface of the ceramic substrate 2 , and an adhesive layer 3 between the integrated circuit 4 (IC) and the ceramic substrate 2 . On the surface of the integrated circuit 4 (IC), there is a prepared pad 6 on the surface of the IC, which is connected to a pad 8 on the surface of the ceramic substrate 2 through a lead 7 . The image photosensitive area 5 is located on the top of the integrated circuit 4 (IC), and the image photosensitive area 5 includes an array of optical interactive elements (such as photodiodes, photodiodes) capable of receiving light and generating electrical signals. The glass lens 10 corresponding to the optical interactive element is installed on the frame 1 , and the frame 1 is connected with the ceramic substrate 2 through an adhesive 9 .

The CMOS sensor structure shown in Figure 1 has many aspects that could be improved. First, because the package uses a bulky glass lens 10 , which is extremely unfavorable for reducing the package volume, so the micro lens 110 can be used to reduce the package volume. Second, the ceramic substrate 2 can be replaced by a silicon substrate, and the I/O (not shown) on the edge of the integrated circuit 4 (IC) is connected to the I/O on the substrate surface by making a redistribution layer (RDL) on the surface of the silicon substrate. The pads 8 are connected, which can further reduce the size of the package structure. Third, the package structure shown is not capable of using lower cost wafer-level processing and surface mount technologies.

FIG. 2 is an improved package structure of an existing CMOS image sensor (CIS) using through-silicon via (TSV) technology. In the package shown in FIG. 2 , the image sensing region 120 is first formed on the top surface of the silicon substrate 130, and the image sensing region 120 includes an optical interactive element and a transistor array (not shown in the figure) for controlling the output of the photoelectric signal. Out), a plurality of micro-lenses 110 are placed on the image sensing area 120 . Secondly, I/Os (not shown) at the edge of the image sensing region 120 are connected to through-silicon vias 170 (TSVs) by forming a redistribution layer 160 (RDL) on the top surface of the silicon substrate 130 . Finally, through silicon vias 170 (TSVs) extend from the top of the silicon substrate 130 to pads 175 on the bottom surface, on which solder balls 190 are fabricated. A solder mask 180 (SMF) is disposed on the backside of the silicon substrate 130 . The top glass sheet 150 is bonded to the silicon substrate 130 by polymer connectors 140 .

With the development of CMOS technology, the integration level is getting higher and higher, which makes the area of the image sensing area more and more small to achieve a larger area of photosensitive area, and the package structure shown in Figure 2 is increasing While the area of the sensing area increases, the delamination phenomenon between the glass sheet 150 and the silicon substrate 130 becomes more and more serious. In addition, if the through-silicon via (TSV) adopts the electroplating Cu process, the through hole needs to be firstly made of an insulating layer (it can be an oxide, such as silicon dioxide; it can also be a nitride such as silicon nitride), an isolation layer, and finally complete the electroplating Cu fills the pores. Electroplating Cu is also an expensive process.

Contents of the invention

The first aspect of the present invention is: based on the current chip size package (CSP) suitable for CMOS image sensors, an improved method is provided for the problem of easy delamination between the glass and the wafer when the chip size gradually increases. The large-size chip CSP package structure is used to improve the layering problem and improve the reliability of the package.

The large chip size package (CSP) of the present invention includes a wafer, the front side of the wafer 200 is the first surface 201 forming the image sensing area, and the negative side of the wafer 200 is the second surface 202; On the first surface 201 of the wafer 200, the center above the silicon substrate 130 is provided with an optical interaction area 210, and a metal interconnection structure 220 (IMD) is connected to the side where the optical interaction area 210 is provided. On the silicon substrate 130, the optical interaction area 210 The surrounding I/O is connected to the electrode pad 225 through the metal interconnection structure 220 (IMD); the surface of the metal interconnection structure 220 (IMD) is provided with a protective layer 230, and a stepped protrusion or groove is formed on the protective layer 230 Structure; the first surface 201 of the wafer 200 and the glass sheet 150 are bonded together through the polymer connector 140, and a cavity is formed between the glass sheet 150 and the wafer 200 through an exposure and development process; the first surface of the wafer 200 The two surfaces 202 are provided with TSV holes 260, and the electrode pads 225 are connected to the pad pads 175 on the second surface 202 of the wafer 200 through the silicon substrate 130 through the TSV holes 260, and blunt holes are sequentially formed on the walls of the TSV holes 260. layer 265 and metal liner 270, and fill the TSV hole 260 with polymer glue; finally, a solder mask 180 (SMF) is formed on the second surface 202 of the wafer 200, and solder balls 190 are formed on the pad 175.

The material of the protective layer is silicon nitride. The polymer glue is composed of resin, solvent, photosensitive compound and additives.

A second aspect of the present invention provides a method of manufacturing the large chip size package, comprising the following steps:

Step 1: Provide Wafers

The first surface of the wafer should include electrode pads formed with an image sensing area and an interconnection structure; a stepped protrusion structure is formed on the area where the outermost protective layer is bonded with glass on the first surface of the wafer.

Alternatively, the stepped protrusion structure on the first surface of the wafer may also be a groove structure.

Step 2: Make a Polymer Bonding Material on the Glass

Firstly, the glass is pretreated and cleaned, which includes pickling neutralization, plasma cleaning, etc., and then a layer of photoresist is coated on the bonding surface of the glass, and a cavity is formed in the center of the glass through the exposure and development process, and the remaining Photoresist as polymer connector;

Step 3: Bonding the glass to the wafer

By coating a layer of resin glue on the surface of the polymer spacer, and then using a bonding machine to bond the glass and the wafer together.

Step 4: Grinding and thinning the second surface of the wafer

The wafer is thinned by grinding on the second surface of the wafer.

Step 5: Form TSV holes on the second surface of the wafer

An etching window is formed by coating a layer of photoresist on the second surface of the wafer, exposing and developing. The holes are formed using a dry etching process. The dry etching process includes deep reactive ion etching (DRIE).

Step 6: Filling of TSV holes

First, a passivation layer is formed in the TSV hole and on the second surface of the wafer, and the passivation layer on the surface of the electrode pad is removed; then a metal lining is made on the surface of the passivation layer; finally, a dielectric layer is deposited on the surface of the metal lining and removed. Fill the TSV holes.

Step 7: Make the circuit layer and solder balls on the second surface of the wafer

By exposing, developing and electroplating the dielectric layer on the second surface of the wafer, a circuit layer is formed on the second surface, and the TSV is connected to the pad. Solder balls are then fabricated on the pads.

In the first step, after the previous process is completed, the photoresist is coated on the first surface of the wafer, and the etching window is formed by exposure and development. After etching, the first surface of the wafer is formed. The required stepped protrusion or groove structure.

In the third step, the polymer connector can also be selected as a dry film (DryFilm), and the dry film is composed of resin, solvent, photosensitive compound and additives, etc., and the surface of the polymer connector can be omitted. The bonding with the wafer is completed through the one-step process of applying adhesive, and the dry film used can be directly bonded with the wafer without applying adhesive, which reduces the process flow.

In the fourth step, the wafer thinning process further includes plasma etching for stress relief. After the wafer is thinned, plasma etching is used to remove the internal stress remaining in the wafer due to grinding, reduce the warpage of the wafer, and facilitate the subsequent process.

The invention effectively increases the bonding strength between the glass and the wafer by making a stepped protrusion or groove structure on the first surface of the wafer, improves the delamination between the glass and the wafer, and improves the reliability of the package. characteristics, making the package suitable for larger chip size packages. In the production method, firstly, dry film is used as the bonding material between the glass and the wafer; secondly, the stress-relief plasma etching adopted after thinning the wafer can effectively remove the internal stress in the wafer due to grinding, and improve Wafer warpage, which further facilitates subsequent process operations; finally, the process of making a metal substrate and filling the TSV holes with a dielectric (such as a polymer) is used instead of an expensive electroplating Cu process. To sum up, these steps reduce the process flow and improve the production efficiency while also reducing the production cost.

Description of drawings

Figure 1 is a schematic diagram of the structure of a traditional CMOS sensor (CIS).

FIG. 2 is a schematic structural diagram of an existing CMOS sensor (CIS).

FIG. 3( a ) is a detailed schematic diagram of a CMOS sensor (CIS) package drawn according to an embodiment of the present invention, and the bonding region on the first surface of the wafer has a stepped protrusion structure.

FIG. 3( b ) is a detailed schematic diagram of a CMOS sensor (CIS) package drawn according to an embodiment of the present invention, and the bonding region on the first surface of the wafer has a stepped groove structure.

4( a ) to ( g ) are cross-sectional schematic diagrams of the manufacturing process of a CMOS sensor (CIS) drawn according to an embodiment of the present invention.

Labels in the figure: 1. Frame, 2. Ceramic substrate, 3. Adhesive layer, 4. Integrated circuit, 5. Image photosensitive area, 6. Welding pad on the surface of IC, 7. Lead, 8. Welding pad on the surface of the substrate , 9. Adhesive, 10. Glass lens, 110. Micro lens, 120. Image sensing area, 130. Silicon substrate, 140. Polymer connector, 150. Glass sheet, 160. Redistribution layer, 170. Through-silicon via, 175. Pad pad, 180. Solder mask, 190. Solder ball, 200. Wafer, 201. First surface, 202, Second surface, 210. Optical interaction area, 220. Metal interconnection structure, 225. Electrode pad, 230. Protective layer, 260. TSV hole, 265. Passivation layer, 270. Metal lining.

detailed description

The present invention enhances the bonding force between the glass sheet 150 and the wafer 200 by making a stepped protrusion or groove structure on the first surface 201 of the wafer 200, and improves the delamination problem between the glass sheet 150 and the wafer 200 , which improves the reliability of the package and is suitable for larger size CMOS sensor (CIS) packages. FIG. 3( a ) and FIG. 3( b ) are respectively schematic diagrams of a CMOS sensor (CIS) package with stepped protrusions and grooves fabricated on the first surface 201 of the wafer.

As shown in FIG. 3(a), the large chip size package according to the embodiment of the present invention includes a wafer 200, the front side of the wafer 200 is the first surface 201 forming the image sensing area, and the negative side of the wafer 200 is The second surface 202; the upper center of the silicon substrate 130 of the first surface 201 of the wafer 200 is provided with an optical interaction area 210, and a metal interconnection structure 220 (IMD) is connected to the side where the optical interaction area 210 is provided, and the wafer 200 The I/O around the upper optical interaction area 210 is connected to the electrode pad 225 through the metal interconnect structure 220 (IMD); the surface of the metal interconnect structure 220 (IMD) is provided with a protective layer 230 (such as silicon nitride), and the protective layer 230 (such as silicon nitride) is formed with a step-like protrusion or groove structure; the protective layer 230 (such as silicon nitride) and the glass sheet 150 are bonded together through the polymer connector 140, through the exposure and development process A cavity is formed between the glass sheet 150 and the wafer 200; the second surface 202 of the wafer 200 is provided with a TSV hole 260, and the electrode pad 225 is connected to the second surface of the wafer 200 by penetrating the silicon substrate 130 through the TSV hole 260 The pad pad 175 above the TSV hole 202 is sequentially formed with a passivation layer 265 and a metal lining 270 on the wall of the TSV hole 260, and the TSV hole 260 is filled with polymer glue; finally, a solder resist is made on the second surface 202 of the wafer 200 layer 180 (SMF), and solder balls 190 are fabricated on pads 285 .

The manufacturing process of the CMOS image sensor of this embodiment will be described in detail below with reference to FIGS. 4( a ) to ( g ). 4( a ) to ( g ) are cross-sectional schematic diagrams of the manufacturing process of the CMOS sensor drawn according to the embodiment of the present invention.

Referring first to FIG. 4( a ), a wafer 200 is provided. The front side of the wafer 200 is a first surface 201 forming an image sensing area, and the negative side of the wafer 200 is a second surface 202 . Wafer 200 comprises: silicon substrate 130; Optical interaction region 210 is formed in the center above wafer 200 first surface 201 silicon substrate 130; Makes metal interconnection layer 220 (IMD) above optical interaction region 210 to make optical interaction region 210 peripheral I/O (not shown) is connected to the electrode pad 225 in the metal interconnection layer 220 (IMD), so that the image sensing area is electrically connected with the peripheral circuit; in the metal interconnection layer 220 ( IMD) outside the protective layer 230 (such as silicon nitride). Wherein, on the protective layer (such as silicon nitride) 230 of the bonding area of the glass sheet 150 on the first surface 201, a stepped protrusion or groove structure is pre-fabricated; in the optical interaction area 210, there are a plurality of photosensitive diodes in the array and corresponding A number of transistors (not shown in the figure) are connected to the photodiodes.

Next please refer to Fig. 4 (b), at first the polymer glue (such as photoresist is made up of resin, solvent, photosensitive compound and additive etc.) is coated on the glass sheet 150 after pretreatment cleaning , by exposing and developing the polymer glue, a cavity is formed on the polymer glue, and the remaining polymer glue is used as the polymer connector 140 for bonding the glass sheet 150 and the wafer 200 . Then, the glass sheet 150 and the wafer 200 are bonded together by a bonding machine.

Next, please refer to FIG. 4( c), make a TSV hole 260 on the second surface 202 of the wafer, and the TSV hole penetrates the silicon substrate 130 and is connected to the electrode pad 225, so that the electrode pad 225 can communicate with the wafer through the TSV hole 260 The second surface 202 is electrically connected.

There are the following steps in making the TSV hole 260: (a) Thinning the silicon substrate 130 on the second surface 202 of the wafer, the thickness of the wafer 200 can be reduced from 600 to 700 microns to 130 microns through a grinding process Left and right; (b) performing stress-relief plasma etching on the second surface 202 of the wafer, thereby removing the internal stress caused by grinding in the wafer 200, improving the warpage of the wafer 200, and facilitating subsequent processes; (c) forming an etching window , by coating a layer of photoresist on the second surface 202 of the wafer after thinning, and forming the required etching window through processes such as exposure and development; (d) the etching of the TSV hole 260 adopts a dry etching process (such as Deep Reactive Ion Etching (DRIE) forms holes to expose the electrode pads 225 . The formed TSV hole 260 is an oblique hole, so as to facilitate the formation of a passivation layer 265 in a subsequent process. The diameter of the TSV hole 260 connected to the electrode pad 225 may be greater than or equal to or smaller than the width of the electrode pad 225 . Next, referring to FIG. 4( d ), a passivation layer 265 is formed on the second surface 202 of the wafer, and the passivation layer on the surface of the bottom electrode pad 225 is removed to expose the electrode pad 225 .

The passivation layer 265 can be oxide (such as silicon dioxide) or nitride (such as silicon nitride). The passivation layer 265 can be formed by plasma chemical vapor deposition (PECVD). Optionally, when the aspect ratio of the TSV 260 is small (for example, about 1:1), the passivation material may also be coated on the second surface 202 of the wafer by coating.

Next, referring to FIG. 4( e ), the metal lining 270 is fabricated on the inner wall of the TSV hole 260 and the second surface 202 of the wafer.

Metal lining 270 can be made by physical vapor deposition (PVD) of aluminum, and a layer of metal lining 270 is sputtered on passivation layer 265 made in the previous step; a layer of metal lining 270 can also be formed on passivation layer 265 by electroplating. Or a conductive substrate of an alloy material.

Next please refer to FIG. 4(f), the hole is filled with a dielectric filler (such as a polymer) to complete the TSV hole 260 structure; the metal lining 270 on the second surface 200b of the wafer is etched to make it patterned to form a circuit layer ; Coating one layer of solder mask 180 (SMF) on the circuit layer to protect the circuit layer; Exposure and development of the solder mask 180 (SMF), making pad pad 175, TSV hole 260 and The land pads 175 are connected through the wiring layer. The specific steps include: (a) filling the TSV hole 260 with a dielectric filler (such as a polymer); The lining 270 is etched to form a circuit distribution pattern, (c) a circuit layer is formed on the back side of the wafer 202 by an electroplating process, (d) a solder mask 180 (SMF) is coated on the back side of the wafer 202, and the circuit layer is protected by exposure and development. Land pads 175 are formed.

Next, please refer to FIG. 4( g ), the solder balls 190 are cut into individual chips by a dicing machine.

The description of the embodiments of the invention has been made for the purpose of effectively illustrating and describing the invention, but by way of example only and should not be construed as limiting the scope of the invention as defined by the claims. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of the present invention. Protection for the present invention therefore covers modifications within the spirit and scope of the invention as defined by the claims.

Claims (6)

1. Large chip size package, characterized in that: it includes a wafer (200), the front side of the wafer (200) is the first surface (201) forming the image sensing area, the wafer (200) The negative side is the second surface (202); the center above the silicon substrate 130 in the first surface (201) of the wafer (200) is provided with an optical interaction zone (210), and the optical interaction zone (210) is provided One side is connected with a metal interconnection structure (220), and the I/O around the optical interaction area (210) on the silicon substrate (130) is connected to the electrode pad (225) through the metal interconnection structure (220); the metal interconnection structure (220) A protective layer (230) is provided on the surface, and a stepped protrusion or groove structure is formed on the protective layer (230); the first surface (201) of the wafer (200) and the glass sheet (150) pass through The polymer connectors (140) are bonded together, and a cavity formed by an exposure and development process is provided between the glass sheet (150) and the wafer (200); the second surface (202) of the wafer (200) is provided with The TSV hole (260), through the silicon substrate (130) through the TSV hole (260), the electrode pad (225) is connected to the pad pad (175) on the second surface (202) of the wafer (200), in the TSV A passivation layer (265) and a metal lining (270) are sequentially formed on the hole wall of the hole (260), and the TSV hole (260) is filled with polymer glue; A solder layer (180), solder balls 190 are formed on the pads (175). 2. The large chip size package according to claim 1, characterized in that: the material of the protective layer (230) is silicon nitride; the polymer connector (140) is made of polymer glue; Colloids are materials that include resins, solvents, photosensitive compounds, and additives. 3. A method for manufacturing the large chip size package according to claim 1, characterized in that: comprising the following steps: The first step: provide the wafer; The first surface of the wafer should include electrode pads formed with an image sensing area and an interconnection structure; a step-like protrusion structure is made on the area where the outermost protective layer on the first surface of the wafer is bonded to glass; or the The stepped protrusion structure on the first surface of the wafer is a groove structure; Step 2: Make polymer connectors on the glass; Firstly, the glass is pretreated and cleaned, which includes pickling neutralization and plasma cleaning, and then a layer of photoresist is coated on the bonding surface of the glass, and a cavity is formed in the center of the glass through the exposure and development process, and the remaining photoresist Resist as a polymer connector; Step 3: bonding the glass to the wafer; By coating a layer of resin glue on the surface of the polymer connector, and then using the bonding machine to bond the glass and the wafer together; Step 4: Grinding and thinning the second surface of the wafer; Thinning the wafer by grinding on the second surface of the wafer; Step 5: Form TSV holes on the second surface of the wafer; Coating a layer of photoresist on the second surface of the wafer, forming an etching window through exposure and development; forming holes by using a dry etching process; the dry etching process includes deep reactive ion etching; Step 6: Filling of TSV holes; First, a passivation layer is formed in the TSV hole and on the second surface of the wafer, and the passivation layer on the surface of the electrode pad is removed; then a metal lining is made on the surface of the passivation layer; finally, a dielectric layer is deposited on the surface of the metal lining and removed. Fill the TSV hole; Step 7: Make a circuit layer and solder balls on the second surface of the wafer; By exposing, developing and electroplating the dielectric layer on the second surface of the wafer, a circuit layer is formed on the second surface, and the TSV is connected to the pad; then solder balls are made on the pad. 4. A method for manufacturing a large chip size package according to claim 3, characterized in that: in the first step, after the previous process is completed, photolithography is performed on the first surface of the wafer Coating of the glue, forming an etching window by exposure and development, and forming the required stepped protrusion or groove structure on the first surface of the wafer after etching. 5. A method of manufacturing a large chip size package according to claim 3, characterized in that: in the third step, the polymer connector is replaced with a dry film, and the dry film includes resin, solvent , photosensitive compounds and additives; at this time, the step of coating adhesive on the surface of the polymer connector is omitted to complete the bonding with the wafer, and the dry film used is directly bonded to the wafer without applying adhesive combine. 6. A method of manufacturing a large chip size package according to claim 3, characterized in that: in the fourth step, the wafer thinning process also includes stress-relief plasma etching; After thinning, plasma etching is used to remove the internal stress remaining in the wafer due to grinding, reduce the warpage of the wafer, and facilitate the subsequent process.