CN103000648B - Large chip sized package and manufacture method thereof - Google Patents
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- CN103000648B CN103000648B CN201210478706.XA CN201210478706A CN103000648B CN 103000648 B CN103000648 B CN 103000648B CN 201210478706 A CN201210478706 A CN 201210478706A CN 103000648 B CN103000648 B CN 103000648B
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Abstract
Large chip sized package and manufacture method thereof, belong to sensor technical field.Central authorities in wafer first surface above silicon substrate are provided with optics interactive areas, are connected with metal interconnection structure in the one side being provided with optics interactive areas, and the I/O on silicon substrate around optics interactive areas passes through metal interconnection anatomical connectivity to electronic pads; The surface of metal interconnection knot is provided with protective layer, and is formed with step-like projection or groove structure on the protection layer; First surface and the sheet glass of wafer are bonded together, between sheet glass and wafer, form cavity; The second surface of wafer is provided with TSV hole, and electronic pads is connected to pad pad above wafer second surface by TSV hole through silicon substrate, TSV hole hole wall is manufactured with successively and makes passivation layer and clad lining, TSV hole is filled by polymeric material; Wafer second surface makes welding resisting layer, and soldered ball is produced on pad pad.Present invention improves the lamination problem between glass and silicon substrate in existing encapsulating structure, improve package reliability.
Description
Technical field
The present invention relates to a kind of large chip sized package (CSP) and a kind of method manufacturing described large chip sized package (CSP).Described encapsulating structure and manufacture method can be preferably used for imageing sensor or MEMS.
Background technology
Chip size packages (CSP) is the chip encapsulation technology of a new generation, and its technical performance has had again new lifting.CSP encapsulation can allow the ratio of chip area and package area more than 1:1.14, and quite close to the ideal situation of 1:1, absolute dimension also only has 32 square millimeters, is about 1/3 of common BGA, is only equivalent to 1/6 of TSOP memory chip area.Compared with BGA package, under equal space, memory capacity can be improved three times by CSP encapsulation.When the object of CSP is the little chip before use large chip (chip functions is more, and performance is better, and chip is more complicated) substitutes, the area that its packaging body takies printed panel remains unchanged or less.Packaging body just because of CSP product is little and thin, and therefore it obtains application rapidly in hand-held mobile electronic device.Volume size after CSP not only reduces encapsulation significantly, reduce packaging cost, improve packaging efficiency, and more meet the requirement of high-density packages; Simultaneously due to because data transfer path is short, stability is high, this be encapsulated in reduce energy consumption while also improve speed and the stability of transfer of data.
Imageing sensor is a kind of semiconductor module, is a kind of equipment optical imagery being converted into electronic signal, and electronic signal is stored after can being used to do and processing further or be digitized, or for image transfer is shown to another display unit.It is widely used in digital camera and other electro-optical devices.Nowadays imageing sensor is mainly divided into charge coupled device (CCD) and cmos image sensor (CIS, CMOSImageSensor).Although ccd image sensor is better than cmos image sensor in picture quality and noise etc., cmos sensor can with traditional semiconductor fabrication techniques manufacture, and production cost is lower.Simultaneously because parts number used is relatively less and signal transmission distance is short, cmos image sensor possesses the advantages such as low in energy consumption, electric capacity, inductance and stray delay reduction.
Figure 1 shows that the encapsulation schematic diagram of a traditional cmos image sensor (CIS).Shown cmos sensor is logical to be comprised: ceramic bases 2, the integrated circuit 4 (IC) that ceramic bases 2 top surface is installed, bond layer 3 is positioned between integrated circuit 4 (IC) and ceramic bases 2.There is the pad 6 on the IC surface made at integrated circuit 4 (IC) on the surface, 7 to be connected with the pad 8 of the substrate surface in ceramic bases 2 by going between.Image sensitive district 5 is positioned at the top of integrated circuit 4 (IC), and image sensitive district 5 comprises can accept optics interactive elements (as photosensitive electric diode, the photodiode) array that light produces the signal of telecommunication.Be installed on framework 1 with the glass lens 10 that described optics interactive elements is corresponding, framework 1 is connected with ceramic bases 2 by bonding agent 9.
Cmos sensor structure shown in Fig. 1 has the aspect much can improved.The first, because this encapsulation employs bulky glass lens 10, this is totally unfavorable to the volume reducing encapsulation, therefore can reduce by adopting lenticule 110 volume encapsulated.Second, ceramic bases 2 can be changed to silicon substrate, by making redistribution layer (RDL) in surface of silicon, the I/O (not shown on figure) at integrated circuit 4 (IC) edge being connected with the pad 8 of substrate surface, further can reducing the size of encapsulating structure like this.3rd, shown encapsulating structure can not with the lower wafer level processing of cost and surface mounting technology.
Fig. 2 is cmos image sensor (CIS) encapsulating structure of improved existing employing silicon through hole (TSV) technology.In the encapsulation shown in Fig. 2, first in the top surface making image sensing unit 120 of silicon substrate 130, described image sensing district 120 comprises optics interactive elements and controls the transistor array (not shown) of photosignal output, is placed with multiple micro lens 110 on image sensing district 120.Secondly, by making redistribution layer 160 (RDL) on the surface at silicon substrate 130 top, the I/O (not shown) at edge, image sensing district 120 is connected to silicon through hole 170 (TSV).Finally, silicon through hole 170 (TSV) extends to the pad pad 175 of lower surface from the top of silicon substrate 130, soldered ball 190 is produced on pad pad 175.Welding resisting layer 180 (SMF) is furnished with at the back side of silicon substrate 130.The sheet glass 150 at top is bonded together with silicon substrate 130 by polymer link 140.
Growing along with CMOS technology, integrated level is also more and more higher, this just makes the area in image sensing district more and more come to realize more large-area photosensitive region, and for the encapsulating structure shown in Fig. 2 while increasing along with sensing unit area, sheet glass 150 is also more and more serious with the lamination between silicon substrate 130.In addition, silicon through hole (TSV) is if when adopting electric copper facing technology, and first through hole need make insulating barrier (can be oxide, as silicon dioxide; Also can be that nitride is as silicon nitride), separator, finally completes plating Cu and fills up hole.Plating Cu is also a kind of expensive technique.
Summary of the invention
A first aspect of the present invention is: based on the current chip size packages (CSP) being applicable to cmos image sensor, for the glass when chip size increases gradually with the problem easily producing layering between wafer, provide a kind of large size chip CSP encapsulating structure of improvement, in order to improve this lamination problem, improve the reliability of encapsulation.
Large chip sized package (CSP) of the present invention comprises wafer, and the front of described wafer 200 is the first surface 201 forming image sensing district, and the negative of described wafer 200 is second surface 202; Central authorities in described wafer 200 first surface 201 above silicon substrate 130 are provided with optics interactive areas 210, be connected with metal interconnection structure 220 (IMD) in the one side being provided with optics interactive areas 210, the I/O on silicon substrate 130 around optics interactive areas 210 is connected to electronic pads 225 by metal interconnection structure 220 (IMD); The surface of metal interconnection structure 220 (IMD) is provided with protective layer 230, and is formed with step-like projection or groove structure on protective layer 230; Be bonded together by polymer link 140 between the first surface 201 of wafer 200 and sheet glass 150, between sheet glass 150 and wafer 200, form cavity by exposure imaging technique; The second surface 202 of wafer 200 is provided with TSV hole 260, electronic pads 225 is connected to pad pad 175 above wafer 200 second surface 202 by TSV hole 260 through silicon substrate 130, TSV hole 260 hole wall is manufactured with passivation layer 265 and clad lining 270 successively, and with polymer latex, TSV hole 260 is filled; Finally on wafer 200 second surface 202, make welding resisting layer 180 (SMF), and soldered ball 190 is produced on pad pad 175.
The material of described protective layer is silicon nitride.Described polymer latex is for be made up of resin, solvent, Photoactive compounds and additive etc.
A second aspect of the present invention there is provided a kind of method manufacturing described large chip sized package, comprises the following steps:
The first step: wafer is provided
Described wafer first surface should comprise and be formed with image sensing district and interconnect architecture electronic pads; Outermost layer protective layer on wafer first surface is with the raised structures of the region making step of bond glass.
Or the step raised structures on described wafer first surface also can be groove structure.
Second step: make polymer connecting material on glass
First preliminary treatment cleaning was carried out to glass, preliminary treatment cleaning comprises pickling neutralization, plasma cleaning etc., then be coated with one deck photoresist at the bonding surface of glass, entreat formation cavity in glass through exposure imaging technique, remaining photoresist is as polymer link;
3rd step: glass carries out bonding with wafer
By at polymer spacers surface coating one deck resin glue, bonding machine platform is then utilized to be combined together by glass isomorphous round key.
4th step: the grinding of wafer second surface is thinning
Carry out thinning by carrying out grinding at wafer second surface to wafer.
5th step: form TSV hole at wafer second surface
By being coated with one deck photoresist at wafer second surface, form etching window by exposure imaging.Dry method etch technology is adopted to form hole.Described dry method etch technology comprises deep reaction ion etching (DRIE).
6th step: the filling in TSV hole
First in TSV hole, form one deck passivation layer with the second surface of wafer, and remove the passivation layer on electronic pads surface; Then clad lining is made in passivation layer surface; Last at clad lining surface deposition one deck dielectric layer, TSV hole to be filled up.
7th step: make line layer and soldered ball at wafer second surface
By exposing the dielectric layer of wafer second surface, developing and electroplating technology, form circuit layer at second surface, TSV is connected with pad pad.Then soldered ball is produced on pad pad.
In the described first step, after front road technique completes, by carrying out the coating of photoresist at wafer first surface, form etching window by exposure imaging, form required step projection or groove structure through the first surface being etched in wafer.
In the 3rd described step, polymer link can also be selected as dry film (DryFilm), described dry film is made up of resin, solvent, Photoactive compounds and additive etc., then can save the bonding having carried out same wafer on polymer link surface by being coated with this step process of bonded adhesives, dry film used just directly can carry out bonding with wafer without painting bonded adhesives, decreases technological process.
In the 4th described step, described wafer reduction process also comprises destressing plasma etching.After wafer is thinning, by plasma etching, removing because grinding the internal stress remained in wafer, reducing the warpage of wafer, being convenient to the carrying out of subsequent technique simultaneously.
The present invention is by making projection or the groove structure of step at wafer first surface, effectively increase glass with the bond strength between wafer, improve glass with the layering between wafer, improve the reliability of encapsulation, make described encapsulation be applicable to larger sized chip size packages.In manufacture method, first have employed dry film as the bonding material between glass and wafer; Secondly the destressing plasma etching taked after thinning to wafer can effectively to be removed in wafer due to the internal stress that grinding produces, and improves the warpage situation of wafer, thus further facilitates later technological operation; Finally have employed and make metal substrate and utilize dielectric (as polymer) to fill the technique in TSV hole and the electric copper facing technology of inexpensive.In sum, these steps decrease while technological process improves production efficiency and also reduce production cost.
Accompanying drawing explanation
Fig. 1 is the structural representation of a traditional cmos sensor (CIS).
Fig. 2 is the structural representation of existing a cmos sensor (CIS).
The detailed maps that Fig. 3 (a) encapsulates for the cmos sensor (CIS) drawn according to embodiments of the invention, and there is the raised structures of step wafer first surface bonding region.
The detailed maps that Fig. 3 (b) encapsulates for the cmos sensor (CIS) drawn according to embodiments of the invention, and there is the groove structure of step wafer first surface bonding region.
Fig. 4 (a) is the manufacturing process generalized section of the cmos sensor (CIS) according to embodiments of the invention drafting to (g).
Number in the figure: 1. framework, 2. ceramic bases, 3. bond layer, 4. integrated circuit, 5. image sensitive district, the pad on 6.IC surface, 7. go between, 8. the pad of substrate surface, 9. bonding agent, 10. glass lens, 110. micro lens, 120. image sensing districts, 130. silicon substrate, 140. polymer link, 150. sheet glass, 160. redistribution layer, 170. silicon through holes, 175. pad pads, 180. welding resisting layer, 190. soldered ball, 200. wafer, 201. first surface, 202, second surface, 210. optics interactive areas, 220. metal interconnection structures, 225. electronic pads, 230. protective layer, 260.TSV hole, 265. passivation layer, 270. clad lining.
Embodiment
The present invention carrys out the adhesion of reinforcing glass sheet 150 with wafer 200 by the projection or groove structure making step on the first surface 201 of wafer 200, improve sheet glass 150 with the lamination problem between wafer 200, improve the reliability of encapsulation and be applicable to larger sized cmos sensor (CIS) encapsulation.The cmos sensor (CIS) that Fig. 3 (a) and Fig. 3 (b) is respectively step projection and the groove structure made on wafer first surface 201 encapsulates schematic diagram.
Shown in Fig. 3 (a), the large chip sized package of embodiment of the present invention comprises wafer 200, and the front of described wafer 200 is the first surface 201 forming image sensing district, and the negative of described wafer 200 is second surface 202; The top center of described wafer 200 first surface 201 silicon substrate 130 is provided with optics interactive areas 210, be connected with metal interconnection structure 220 (IMD) in the one side being provided with optics interactive areas 210, the I/O on wafer 200 around optics interactive areas 210 is connected to electronic pads 225 by metal interconnection structure 220 (IMD); The surface of metal interconnection structure 220 (IMD) is provided with protective layer 230 (as silicon nitride), and is formed with step-like projection or groove structure on protective layer 230 (as silicon nitride); Protective layer 230 (as silicon nitride) above and between sheet glass 150 is bonded together by polymer link 140, forms cavity by exposure imaging technique between sheet glass 150 and wafer 200; The second surface 202 of wafer 200 is provided with TSV hole 260, penetrate silicon substrate 130 by TSV hole 260 and electronic pads 225 is connected to pad pad 175 above wafer 200 second surface 202, TSV hole 260 hole wall is manufactured with passivation layer 265 and clad lining 270 successively, and with polymer latex, TSV hole 260 is filled; Finally on wafer 200 second surface 202, make welding resisting layer 180 (SMF), and soldered ball 190 is produced on pad pad 285.
The manufacturing process of the cmos image sensor of the present embodiment is described in detail below in conjunction with Fig. 4 (a) to (g).Fig. 4 (a) is the manufacturing process generalized section of the cmos sensor according to embodiments of the invention drafting to (g).
First please refer to Fig. 4 (a), provide wafer 200, the front of described wafer 200 is the first surface 201 forming image sensing district, and the negative of described wafer 200 is second surface 202.Wafer 200 comprises: silicon substrate 130; Optics interactive areas 210 is formed at the central authorities above wafer 200 first surface 201 silicon substrate 130; Above optics interactive areas 210, make metal interconnection layer 220 (IMD) makes the I/O of periphery, optics interactive areas 210 (not shown on figure) be connected with the electronic pads 225 in metal interconnection layer 220 (IMD), produces electric connection to make image sensing district with peripheral circuit; Protective layer 230 (as silicon nitride) is made in metal interconnection layer 220 (IMD) outside.Wherein on first surface 201 with the projection or the groove structure that the protective layer (as silicon nitride) 230 of sheet glass 150 bond area make in advance step; In optics interactive areas 210, array has multiple photodiode and is connected respectively multiple transistor (not shown)s of photodiode.
Next please refer to Fig. 4 (b), first coating machine platform figure is utilized by polymer latex (as photoresist is made up of resin, solvent, Photoactive compounds and additive etc.) to be coated on the sheet glass 150 of preliminary treatment cleaning, by carrying out exposure imaging to polymer latex, form cavity on polymer latex, remaining polymer latex is as the polymer link 140 of bonding sheet glass 150 and wafer 200 bonding.Then be bonded together with wafer 200 by bonding machine platform sheet glass 150.
Next please refer to Fig. 4 (c), make hole, TSV hole 260, TSV at the second surface 202 of wafer and penetrate silicon substrate 130 and be communicated to electronic pads 225, make electronic pads 225 can realize being electrically connected by TSV hole 260 and wafer second surface 202.
Following step is had: (a) silicon substrate 130 to wafer second surface 202 carries out thinning, by grinding technics, the thickness of wafer 200 can be down to 130 microns from 600 ~ 700 microns when making TSV hole 260; B () carries out destressing plasma etching to wafer second surface 202, thus remove the internal stress due to grinding generation in wafer 200, improves the warpage of wafer 200, is convenient to subsequent technique and carries out; C () forms etching window, be coated with one deck photoresist by the wafer second surface 202 after thinning, enters the techniques such as overexposure development and forms the etching window needed; D the etching in () TSV hole 260, adopts dry method etch technology (as deep reactive ion etch, DRIE) to form hole, electronic pads 225 is come out.The TSV hole 260 formed is inclined hole, so that form passivation layer 265 in subsequent technique.TSV hole 260 can be more than or equal to or be less than the width of electronic pads 225 with the aperture that electronic pads 225 is connected.Next please refer to Fig. 4 (d), make one deck passivation layer 265 at the second surface 202 of wafer, and remove the passivation layer on bottom electrical polar cushion 225 surface, to expose electronic pads 225.
Passivation layer 265 can be oxide (as silicon dioxide), also can be nitride (as silicon nitride).The making of passivation layer 265 can using plasma chemical vapour deposition (CVD) (PECVD).Optionally, when the depth-to-width ratio of TSV260 smaller (such as during about 1:1) also can adopt the method for coating passivating material to be coated on the second surface 202 of wafer.
Next please refer to Fig. 4 (e), to the making of TSV hole 260 hole inwall and the enterprising row metal lining 270 of wafer second surface 202.
The making of clad lining 270 can adopt the physical vapour deposition (PVD) (PVD) of aluminium, and the passivation layer 265 that previous step is made sputters layer of metal lining 270; Also can be formed the conductive substrates of layer of metal or alloy material on passivation layer 265 by galvanoplastic.
Next please refer to Fig. 4 (f), hole is carried out to the filling of dielectric filler (as polymer) to complete TSV hole 260 structure; Its patterning is made to form line layer by carrying out etching to the clad lining 270 of wafer second surface 200b; The line layer made is being coated with one deck welding resisting layer 180 (SMF) with protection circuit layer; Exposure imaging is carried out to welding resisting layer 180 (SMF), makes pad pad 175, TSV hole 260 in precalculated position and be connected by line layer with pad pad 175.Concrete steps comprise: (a) adopts dielectric filler (as polymer) to complete filling to TSV hole 260; b () forms etching window by exposure imaging technique at wafer second surface 202; the clad lining 270 of wafer second surface 202 is etched with and forms circuit distribution patterns; c () forms line layer by electroplating technology at wafer rear 202; d () be coated with welding resisting layer 180 (SMF) at wafer rear 202, form pad pad 175 by exposure imaging protection circuit layer.
Next please refer to Fig. 4 (g), by soldered ball 190, then by cutting machine, full wafer wafer is cut into the chip of single.
To be object be effectively illustrates and describe the present invention in the description of the embodiment that the present invention carries out, but only should not be construed as by example the scope of the present invention limiting and defined by claims by this.Technical staff belonging to any this area without departing from the spirit and scope of the present invention, can make possible variation and amendment.Therefore protection of the present invention covers the amendment in the essence of an invention that defines of claim and scope.
Claims (6)
1. large chip sized package, it is characterized in that: it includes wafer (200), the front of described wafer (200) is the first surface (201) forming image sensing district, and the negative of described wafer (200) is second surface (202); Central authorities in described wafer (200) first surface (201) above silicon substrate 130 are provided with optics interactive areas (210), be connected with metal interconnection structure (220) in the one side being provided with optics interactive areas (210), the upper optics interactive areas (210) of silicon substrate (130) I/O is around connected to electronic pads (225) by metal interconnection structure (220); The surface of metal interconnection structure (220) is provided with protective layer (230), and is formed with step-like projection or groove structure on protective layer (230); Be bonded together by polymer link (140) between the first surface (201) of wafer (200) and sheet glass (150), between sheet glass (150) and wafer (200), be provided with the cavity formed by exposure imaging technique; The second surface (202) of wafer (200) is provided with TSV hole (260), electronic pads (225) is connected to pad pad (175) above wafer (200) second surface (202) by TSV hole (260) through silicon substrate (130), TSV hole (260) hole wall is manufactured with passivation layer (265) and clad lining (270) successively, and with polymer latex, TSV hole (260) is filled; Wafer (200) second surface (202) is manufactured with welding resisting layer (180), soldered ball 190 is produced on pad pad (175).
2. large chip sized package according to claim 1, is characterized in that: the material of described protective layer (230) is silicon nitride; Polymer link (140) is made up of polymer latex; Described polymer latex is the material comprising resin, solvent, Photoactive compounds and additive.
3. a method for the large chip sized package described in manufacturing claims 1, is characterized in that: comprise the following steps:
The first step: wafer is provided;
Described wafer first surface should comprise and be formed with image sensing district and interconnect architecture electronic pads; Outermost layer protective layer on wafer first surface is with the raised structures of the region making step of bond glass; Or the step raised structures on described wafer first surface is groove structure;
Second step: make polymer link on glass;
First preliminary treatment cleaning was carried out to glass, preliminary treatment cleaning comprises pickling neutralization, plasma cleaning, then be coated with one deck photoresist at the bonding surface of glass, entreat formation cavity in glass through exposure imaging technique, remaining photoresist is as polymer link;
3rd step: glass carries out bonding with wafer;
By at polymer link surface coating one deck resin glue, bonding machine platform is then utilized to be combined together by glass isomorphous round key;
4th step: the grinding of wafer second surface is thinning;
Carry out thinning by carrying out grinding at wafer second surface to wafer;
5th step: form TSV hole at wafer second surface;
By being coated with one deck photoresist at wafer second surface, form etching window by exposure imaging; Dry method etch technology is adopted to form hole; Described dry method etch technology comprises deep reaction ion etching;
6th step: the filling in TSV hole;
First in TSV hole, form one deck passivation layer with the second surface of wafer, and remove the passivation layer on electronic pads surface; Then clad lining is made in passivation layer surface; Last at clad lining surface deposition one deck dielectric layer, TSV hole to be filled up;
7th step: make line layer and soldered ball at wafer second surface;
By exposing the dielectric layer of wafer second surface, developing and electroplating technology, form circuit layer at second surface, TSV is connected with pad pad; Then soldered ball is produced on pad pad.
4. a kind of method manufacturing large chip sized package according to claim 3, it is characterized in that: in the described first step, after front road technique completes, by carrying out the coating of photoresist at wafer first surface, form etching window by exposure imaging, form required step projection or groove structure through the first surface being etched in wafer.
5. a kind of method manufacturing large chip sized package according to claim 3, is characterized in that: in the 3rd described step, polymer link is replaced by dry film, and described dry film comprises resin, solvent, Photoactive compounds and additive; Now save the bonding having carried out same wafer on polymer link surface by being coated with bonded adhesives this step process, dry film used without painting bonded adhesives just direct same wafer carry out bonding.
6. a kind of method manufacturing large chip sized package according to claim 3, is characterized in that: in the 4th described step, described wafer reduction process also comprises destressing plasma etching; After wafer is thinning, by plasma etching, removing because grinding the internal stress remained in wafer, reducing the warpage of wafer, being convenient to the carrying out of subsequent technique simultaneously.
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| CN103762198B (en) * | 2013-12-31 | 2016-07-06 | 中国科学院微电子研究所 | TSV hole filling method |
| CN105731360B (en) * | 2014-12-09 | 2017-10-10 | 中芯国际集成电路制造(上海)有限公司 | MEMS sensor and preparation method thereof |
| CN104617029A (en) * | 2015-01-07 | 2015-05-13 | 中国电子科技集团公司第五十五研究所 | Method for improving semiconductor wafer bonding alignment precision |
| CN105826332A (en) * | 2015-01-09 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN106365108A (en) * | 2015-07-23 | 2017-02-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof, and electronic apparatus |
| CN205752132U (en) * | 2016-05-19 | 2016-11-30 | 深圳市汇顶科技股份有限公司 | Silicon through hole chip, fingerprint Identification sensor and terminal unit |
| US10199333B2 (en) | 2017-07-05 | 2019-02-05 | Omnivision Technologies, Inc. | Delamination-resistant semiconductor device and associated method |
| CN107946335B (en) | 2017-12-22 | 2020-10-27 | 成都先锋材料有限公司 | CMOS image sensing packaging structure and manufacturing method thereof |
| US11114383B2 (en) | 2018-10-23 | 2021-09-07 | Micron Technology, Inc. | Semiconductor devices having integrated optical components |
| CN112420603A (en) * | 2020-11-20 | 2021-02-26 | 中国科学院半导体研究所 | Preparation method of TSV-based MEMS sensor vertical electrical interconnection structure |
| CN113526454B (en) * | 2021-07-16 | 2024-04-19 | 芯知微(上海)电子科技有限公司 | MEMS packaging structure and manufacturing method thereof |
| CN115656789B (en) * | 2022-12-26 | 2024-04-09 | 惠州市金百泽电路科技有限公司 | Step bonding pad structure and testing method thereof |
| CN117013974B (en) * | 2023-10-08 | 2024-01-30 | 深圳新声半导体有限公司 | Wafer-level packaging method of BAW filter |
| CN117246973A (en) * | 2023-11-17 | 2023-12-19 | 苏州敏芯微电子技术股份有限公司 | Micro-electromechanical force sensor and preparation method thereof |
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