CN102544040B - Method utilizing TSV (Through-Silicon-Via) to realize wafer level package of GaAs (gallium arsenide) image sensor - Google Patents
Method utilizing TSV (Through-Silicon-Via) to realize wafer level package of GaAs (gallium arsenide) image sensor Download PDFInfo
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- CN102544040B CN102544040B CN201210014615.0A CN201210014615A CN102544040B CN 102544040 B CN102544040 B CN 102544040B CN 201210014615 A CN201210014615 A CN 201210014615A CN 102544040 B CN102544040 B CN 102544040B
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Abstract
The invention relates to a method utilizing TSV (Through-Silicon-Via) to realize wafer level package of a GaAs (gallium arsenide) image sensor. The method comprises the following steps: combining wet etching with mechanical machining to machine a groove; manufacturing a resin insulating layer in the groove; then manufacturing a through hole in resin by using a laser method; electroplating the inner part of the groove and the inner part of the through hole to realize the back extraction of the electrode of a front wafer surface; and making a passivating layer and solder bumps. The whole process is completed at a wafer level, and the interconnection density is high while the package cost is reduced. Meanwhile, a manufactured interconnection structure has high reliability.
Description
Technical field
The present invention relates to one utilizes TSV technology to realize the wafer-level encapsulation method of GaAs (GaAs) imageing sensor.Belong to image sensor package and manufacture field.
Background technology
Generally speaking, imageing sensor is a kind of semiconductor module, and it is in order to convert an optical imagery to electronic signal, and memory image signal and transmit it to a display unit.
Along with the development of information technology, image sensing module has been applied in digital mobile product more and more widely, especially cellular handset, and its market also keeps having increased for many years.But along with the sustainable competition on semicon industry microminiaturization, multi-functional trend and market, the mobile product of a new generation has higher requirement to image sensing module, for example little profile and low cost.The encapsulation of traditional image sensing module, for example chip on board technology (Chip On Board, COB) and cover brilliant flexible circuit plate technique (Chip On Flexible, COF), because the restriction of method for packing is difficult to meet these requirements.Wafer-Level Packaging Technology (Wafer Level Packaging, WLP) provide good solution route for meeting this requirement.
Described WLP technology refers to, in the situation that not being cut, chip completes whole packaging process at wafer scale, as plastic packaging, wire bonds and packaging and testing etc., after cutting, obtain packaged final products, be considered to follow-on chip size packages technology (Chip Size Packaging, CSP).It is applied to image sensor package field, and WLP technology has small size, high-performance and advantage cheaply.In this technology, realize electrical connection for the pad guiding back side from imageing sensor front, several structures have been developed out, as T-shaped connection and TSV (Through silicon Via).
Fig. 1 shows that Tessera manufactures WLCSP (Wafer Level Chip Size Packaging) the cross-sectional configuration figure of this image sensor package.
As shown in Figure 1, on the front of wafer 101, form multiple image sensor modules (as image sensing cell 102 and a pad electrode 103); This wafer is adhered on transparency carrier 104 with resin 105.Etched wafer 101 forms groove 106, encapsulating, bonding substrate 114 overleaf subsequently, from back side fluting, plated metal line, form T-shaped connection 109, and make outer electrode 110.Finally cut this wafer along line of cut 115 places, obtain multiple packaged chips.After this,, by a default processing procedure, just can form image device module, for example a video camera.
But the structure after above-mentioned wafer-class encapsulation is follow-up after cutting step is divided into multiple encapsulated integrated circuit components, one section of T-shaped connection is exposed to the external world, is subject to penetration of moisture, thereby is subjected to corrosion and peels off and wait integrity problem generation.Therefore, the encapsulation of this form often cannot be lost efficacy by reliability testings such as high temperature/high humidity tests., in above-mentioned manufacture method, because the connection area of this T-type connection 109 is very little, probably chap meanwhile, equally easily cause the integrity problem of jointing.
The another kind of implementation of WLP is TSV technology.Owing to adopting perpendicular interconnection, TSV technology can shorten electrical interconnection length significantly, thereby has reduced signal delay, has improved electrical property.Meanwhile, TSV technology can realize three-dimensional stacked encapsulation easily, is therefore used as the technical way of high performance three-dimensional high-density packages.Because draw at the back side that can realize front electrode, and there is the feature of high density, small size, be applied in recent years the encapsulation field of imageing sensor.
The main technique method for the treatment of through wafer interconnection construction is at present: utilize Bosch reactive ion etching-inductively coupled plasma method in crystal column surface etching blind hole; Form insulating barrier at silicon face with chemical vapour deposition (CVD) oxide or nitride passivation; Metal SiClx through hole, adopts copper electric plating method filling silicon through holes, removes unnecessary copper electrodeposited coating with chemico-mechanical polishing; Back side grinding wafer, exposes copper conductor layer, completes through-hole structure.
But, as mentioned above, this utilization the technique such as such as RIE, CVD and CMP, make with high costsly, thereby only use at high-end product, be not suitable for low-end product application.Meanwhile, between substrate and steel structure, only have the insulating barrier that one deck is very thin, make TSV interconnection form very high electric capacity, sometimes even exceeded the capacitance of standard wire interconnection mode.In technique, used the method for dry plasma etch, whole device is exposed under the bombardment of ion, easily causes the inefficacy of device, and the especially device to Ions Bombardment sensitivity, as GaAs imageing sensor
Summary of the invention
The object of this invention is to provide a kind of through-silicon via structure of encapsulation of the imageing sensor with higher reliability; To overcome the poor problem of above-mentioned T-shaped connection reliability.
The object of the present invention is to provide one to utilize TSV technology to realize GaAs imageing sensor wafer-level encapsulation method, high to overcome conventional TSV method cost, the capacitance that forms between TSV is lower, signal lag is less, device is not existed to irradiation damage simultaneously; Overcome the poor problem of existing T-shaped connection reliability simultaneously.
The technical solution used in the present invention is: first image sensor wafer is bonded on a transparency carrier, utilizes subsequently the method that machining and wet etching are used in conjunction with to process groove at the back side of wafer, expose pad electrode at bottom portion of groove simultaneously; Then in groove, do a resin insulating barrier; Thereafter use laser processing on insulating barrier, to make through hole, through hole penetrates pad electrode; Then do in metal seed layer, through hole and groove and electroplate; Finally do passivation layer and solder bump.
Concrete technology step of the present invention is:
A. wafer bonding
(a) make pad electrode in the front of image sensing wafer, pad electrode is distributed in sensing unit periphery, and wafer material is GaAs, and thickness is 300-400 μ m;
(b), at front and a transparency carrier bonding of image sensing wafer, use BCB as binding agent.
B. on wafer, make groove
(a) use scribing machine to make groove at the back side of wafer, the degree of depth of groove is 200-300 μ m; Width is 250-350 μ m;
(b) use 9H
3pO
4-1H
2o
2-20H
2o solution corrosion groove, to exposing front electrode.
C. in groove, make insulating barrier and through hole
(a) adopt the method for glue spraying to make insulating barrier in wafer surface, insulating layer material is selected epoxy resin, and thickness is 5-10 μ m;
(b) use on the insulating barrier of laser in groove and make through-hole structure, the degree of depth of through hole is 25-30 μ m, and through hole penetrates the pad electrode of wafer frontside.
D. in groove and through hole, make metal interconnecting layer
(a) chip back surface sputter one deck Seed Layer TiW/Cu, wherein Ti/W is as adhesion layer, and Cu is Seed Layer; Seed layer thickness is 5-10 μ m;
(b) in Seed Layer, spray last layer photoresist, post-exposure, development, obtain photoetching offset plate figure;
(c) corroding metal Seed Layer, obtains seed metallization layer pattern, then removes photoresist;
(d) electro-coppering, with interconnection line in filling vias and making groove.
E. passivation and stud bump making
(a) on the basis completing at step D, at disk back side spin coating last layer epoxy resin, as passivation layer;
(b) there being the method opening of use plasma etching of electrode, make to expose electrode;
(c) use SB2-Jet laser ball implanting equipment on electrode, to prepare indium salient point.
The feature of the encapsulating structure of the imageing sensor wafer level packaging silicon through hole being provided by above-mentioned manufacture craft is:
(1) groove shapes is trapezoidal, and angle of inclination is 60 degree, and the degree of depth is 200-300 μ m; Preferential 250 μ m;
(2) through hole penetrates pad, and the degree of depth penetrating is 5 μ m; The degree of depth of whole through hole is 20-30 μ m;
(3) through-hole diameter that laser is made is 30-50 μ m, is preferably 40 μ m, is 40-60 μ m along the spacing of groove direction, is preferably 50 μ m;
Actual effect of the present invention is on the basis of the through-silicon via structure of making, to have realized the wafer level packaging of imageing sensor, and this image sensor package module has less volume and higher package reliability.Utilize the through-hole structure that laser processing is made on epoxy resin to there is less capacitance and less signal delay, realized higher interconnection density simultaneously.Whole manufacture craft to device without irradiation damage, and with IC technical process compatibility, there is low-cost advantage.
Accompanying drawing explanation
Fig. 1 is the cross-sectional configuration figure that shows the WLCSP encapsulation of Tessera company imageing sensor.
That Fig. 2 to Figure 10 shows is image sensor package operation cross-sectional configuration figure, and it is a preferred embodiment of the present invention.
Wherein: Fig. 2 GaAs image sensor cell chip; Fig. 3 bonding; Fig. 4 processing of slotting; Fig. 5 erosion grooves; Fig. 6 forms insulating barrier; Fig. 7 laser processing through hole; Fig. 8 sputtering seed layer; Fig. 9 makes passivation layer; Figure 10 makes the UBM layer of indium salient point.
Embodiment
In order to make advantage of the present invention and good effect find full expression, below in conjunction with drawings and Examples, substantive distinguishing features of the present invention and significant progress are described further.
With reference to figure 2, GaAs image sensor wafer 1 comprises several chips, through default processing procedure, is formed with image sensing assembly in each chip front side, comprises and forms image sensing cell 2 and pad electrode 3.Pad electrode 3 is distributed in image sensing cell periphery nonfunctional area, and the material of selecting can be aluminium, gold or copper.The use wave band of imageing sensor is visible-range, and wafer thickness is 350 μ m.
With reference to figure 3, wafer sheet 1 be bonded to a transparency carrier 5 on, thereafter.Substrate plays printing opacity, prevent outside contamination and exempt from the effect of mechanical damage, simultaneously for technique subsequently provides mechanical support.Bonding adopts adhesive BCB bonding, and adhesive 4 is coated in the middle of wafer and transparency carrier, and thickness is 20 μ m, adopts hot curing in bonder, and curing temperature is 200 ℃.
With reference to figure 4, in the substrate back processing of slotting, process groove 6.The position of groove is corresponding with positive pad.What the method for fluting adopted here is mechanical slotting, and the equipment of use is scribing machine, adopts the special cutter with trapezoidal blade.The breadth-first of the groove processing is 300 μ m, and depth-first is 250 μ m; In order to prevent the temperature rise in machining, in machining, use cooling fluid to carry out cooling, cooling fluid is deionized water.
Then,, with reference to figure 5, adopt the method for wet etching to corrode groove, till exposed pad.Corrosive liquid is 9H
3pO
4-1H
2o
2-20H
2o solution system, etching time is 6-8h, corrosion thickness is 80-120 μ m.The direction of vertical wafer is <100> crystal orientation, according to anisotropic corrosion principle, and the groove 14 that final etching obtains.Owing to being wafer general corrosion, the integral thickness of wafer is also by attenuation, and integral thickness is 250 μ m.Compare the method for machining fluting, the limit wall that wet etching obtains is more smooth, on material around to affect the degree of depth less, owing to approaching the functional areas (sensing unit district) of front wafer surface, adopt wet etching can minimize the impact on device function district herein.Because wafer is thicker, (m), if use separately wet etching to obtain through hole, wafer open back duty is larger, has limited interconnection density for 350 μ.
Thereafter, with reference to figure 6, adopt the method for spraying on wafer, to be coated with last layer resin as groove inner insulating layer 7, thickness is 8 μ m left and right, and resin material is epoxy resin.
With reference to figure 7, use YAG laser fabrication through hole 8.Power and the energy of controlling laser, make hole penetrate the pad electrode of wafer frontside, and penetration depth is 5 μ m, and the degree of depth of whole through hole is 20-30 μ m, and via top diameter is 30-50 μ m, and bottom is about 20-40 μ m.Prolong the direction of groove, pitch of holes 40-60 μ m.
Secondly, with reference to figure 8, sputter layer of metal Seed Layer TiW/Cu on wafer, wherein Ti/W is as adhesion layer, and Cu is Seed Layer; Afterwards, in Seed Layer, make mask, Seed Layer is carried out etching, removed photoresist, realize the patterning of Seed Layer, electroplate the thick copper of one deck 8 μ m in Seed Layer subsequently, obtain in groove lead and through hole metal filled.In through hole, metal part crossing with wafer frontside pad electrode is electrode contact 9, and because through hole is all connected in the surrounding in hole with pad, contact area is larger, therefore connects and has higher reliability with respect to traditional N-type.
Then, with reference to figure 9, utilize the method for spin coating resin to make passivation layer 12, groove is filled simultaneously.The passivation layer of making will guarantee the flatness at the back side, contributes to like this to make solder bump and image sensor package body and being connected that next stage encapsulates on substrate.The material of passivation layer is epoxy resin, and spin coating thickness is 5-15 μ m.
Finally, with reference to Figure 10, the S1912 photoresist of photoetching 1.7 μ m, exposes the place that needs opening.Use reactive ion etching (RIE) to carry out opening to epoxy resin layer, opening size is 40X40 μ m
2, after etching completes, use acetone removes photoresist, and etching gas is SF
6and C
4f
8.Sputtered with Ti/Pt/Au (30nm/20nm/100nm) metallic film is as the UBM layer of indium salient point; Use SB2-Jet laser ball implanting equipment on UBM layer, to prepare indium salient point.
Claims (7)
1. a method of utilizing TSV technology to realize the wafer level packaging of GaAs imageing sensor, it is characterized in that first image sensor wafer being bonded on a transparency carrier, utilize subsequently the method that machining and wet etching are used in conjunction with to process groove at the back side of wafer, expose pad electrode at bottom portion of groove simultaneously; Second step is in groove, to make a resin insulating barrier; And using laser processing on insulating barrier, to make through hole, through hole penetrates pad electrode; The 3rd step is to make in metal seed layer, through hole and groove to electroplate; Finally make passivation layer and solder bump; Concrete processing step is:
A. wafer bonding
(a) make pad electrode in the front of image sensing wafer, pad electrode is distributed in sensing unit periphery, and wafer material is GaAs, and thickness is 350 μ m;
(b), at front and a transparency carrier bonding of image sensing wafer, use BCB as binding agent;
B. on wafer, make groove
(a) use scribing machine to make groove at the back side of wafer, the degree of depth of groove is 200-300 μ m; Width is 250-350 μ m;
(b) use 9H
3pO
4-1H
2o
2-20H
2o solution corrosion groove, to exposing front electrode;
C. in groove, make insulating barrier and through hole
(a) adopt the method for glue spraying to make insulating barrier in wafer surface, insulating layer material is selected epoxy resin, and thickness is 5-10 μ m;
(b) use on the insulating barrier of laser processing in groove and make through-hole structure, the degree of depth of through hole is 20-30 μ m; Through hole penetrates the pad electrode of wafer frontside;
D. in groove and through hole, make metal interconnecting layer
(a) chip back surface sputter one deck Seed Layer TiW/Cu, wherein Ti/W is as adhesion layer, and Cu is Seed Layer;
(b) in Seed Layer, spray last layer photoresist, post-exposure, development, obtain photoetching offset plate figure;
(c) corroding metal Seed Layer, obtains seed metallization layer pattern, then removes photoresist;
(d) electro-coppering, with interconnection line in filling vias and making groove;
E. passivation and stud bump making
(a) on the basis completing at step D, at disk back side spin coating last layer epoxy resin, as passivation layer; Passivation layer thickness is 5-10 μ m;
(b) there being the method opening of use plasma etching of electrode, make to expose electrode;
(c) use SB2-Jet laser ball implanting equipment on electrode, to prepare indium salient point.
2. by method claimed in claim 1, the bonding temperature that it is characterized in that (b) in steps A is 200-230 ℃, and adhesive thickness is 15-25 μ m.
3. by method claimed in claim 1, it is characterized in that the groove shapes in step B is trapezoidal, angle of inclination is 60 degree.
4. by method claimed in claim 1, it is characterized in that the degree of depth that through hole in step C penetrates pad is 5 μ m.
5. by the method described in claim 1 or 4, it is characterized in that in step C, through-hole diameter is 30-50 μ m, is 40-60 μ m along the spacing of groove direction.
6. by method claimed in claim 1, it is characterized in that:
A) described depth of groove is 250 μ m; Width is 300 μ m;
B) described through hole is 50 μ m along the spacing of groove direction.
7. by the method described in claim 1,3 or 6, it is characterized in that slotting is the tool sharpening that adopts trapezoidal blade.
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| CN201210014615.0A CN102544040B (en) | 2012-01-17 | 2012-01-17 | Method utilizing TSV (Through-Silicon-Via) to realize wafer level package of GaAs (gallium arsenide) image sensor |
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| CN201210014615.0A CN102544040B (en) | 2012-01-17 | 2012-01-17 | Method utilizing TSV (Through-Silicon-Via) to realize wafer level package of GaAs (gallium arsenide) image sensor |
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| CN103794544B (en) * | 2012-10-26 | 2016-04-13 | 中国科学院上海微系统与信息技术研究所 | A kind of method of electro-coppering |
| CN103280449B (en) * | 2013-05-16 | 2016-06-01 | 华进半导体封装先导技术研发中心有限公司 | A kind of manufacture method carrying on the back photograph image sensor |
| CN103420330B (en) * | 2013-09-09 | 2015-09-02 | 厦门大学 | A kind ofly be applied to the interconnected preparation method of micro element wafer level packaging via metal |
| CN104516194A (en) * | 2013-09-30 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Patterned photoresist layer forming method and wafer-stage chip packaging method |
| CN105355636B (en) * | 2015-08-20 | 2018-10-09 | 苏州科阳光电科技有限公司 | The manufacturing method of semiconductor image sensor part |
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| KR100676493B1 (en) * | 2004-10-08 | 2007-02-01 | 디엔제이 클럽 인코 | method for manufacturing wafer level chip scale package using redistribution substrate |
| US20080284041A1 (en) * | 2007-05-18 | 2008-11-20 | Samsung Electronics Co., Ltd. | Semiconductor package with through silicon via and related method of fabrication |
| TWI375321B (en) * | 2007-08-24 | 2012-10-21 | Xintec Inc | Electronic device wafer level scale packages and fabrication methods thereof |
| WO2009140798A1 (en) * | 2008-05-21 | 2009-11-26 | 精材科技股份有限公司 | Electronic component package body and its packaging method |
| US8536672B2 (en) * | 2010-03-19 | 2013-09-17 | Xintec, Inc. | Image sensor package and fabrication method thereof |
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