CN103247639A - Wafer level packaging method and structure of image sensor - Google Patents
Wafer level packaging method and structure of image sensor Download PDFInfo
- Publication number
- CN103247639A CN103247639A CN2012100267206A CN201210026720A CN103247639A CN 103247639 A CN103247639 A CN 103247639A CN 2012100267206 A CN2012100267206 A CN 2012100267206A CN 201210026720 A CN201210026720 A CN 201210026720A CN 103247639 A CN103247639 A CN 103247639A
- Authority
- CN
- China
- Prior art keywords
- sensor wafer
- image sensor
- imageing sensor
- wafer
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Solid State Image Pick-Up Elements (AREA)
Abstract
The invention relates to a wafer level packaging method and structure of an image sensor. The method comprises the following steps: an image sensor wafer (1) consisting of a plurality of chips is provided and bonded with a transparent substrate (5); back thinning is performed to the image sensor wafer (1); the punching is carried out at positions, corresponding to a bonding pad electrode (4), on the back of the image sensor wafer to form a plurality of first through holes; an insulation layers (8) is coated and solidified; inverted trapezoidal second through holes are further formed in the insulation layers in the first through holes to expose the bonding pad electrode (4), wherein the first through holes and the second through holes are coaxial; a metal seeding layer (10) is sputtered and a metal interconnection layer (11) is formed through electroplating sequentially; and a second passivation layer (12) and a solder ball bump (13) are prepared sequentially. According to the invention, the whole technological process is completed on wafer level, the interconnection density is relatively high on the basis of reducing the packaging cost, and meanwhile, the interconnection structure prepared has higher reliability.
Description
Technical field
The present invention relates to a kind of silicon through hole (TSV) wafer level packaging technology of imageing sensor.Belong to image sensor package and make the field.
Background technology
Generally speaking, imageing sensor is a kind of semiconductor module, is in order to converting an optical imagery to electronic signal, and memory image signal and transmit it to a display unit.
Along with the development of information technology, image sensing module has been applied in the digital mobile product more and more widely, cellular handset especially, and its market also keeps having increased for many years.Yet along with the sustainable competition on semicon industry microminiaturization, multi-functional trend and the market, the mobile product of a new generation has higher requirement to image sensing module, for example little profile and low cost.The encapsulation of traditional image sensing module, for example the chip on board technology (Chip On Board, COB) and cover brilliant flexible circuit plate technique (Chip On Flexible, COF) because the restriction of method for packing is difficult to satisfy these requirements.(WaferLevel Packaging WLP) provides good solution route for satisfying this requirement to Wafer-Level Packaging Technology.
The WLP technology refers to finish whole packaging process at wafer scale under the situation that chip is not cut, as plastic packaging, wire bonds and packaging and testing etc., obtain packaged final products after the cutting, be considered to follow-on chip size packages technology (ChipSize Packaging, CSP).Be applied to the image sensor package field, the WLP technology has small size, high-performance and advantage cheaply.In this technology, realize being electrically connected in order to guide to the back side from the pad in imageing sensor front, several structures have been developed, and connect and TSV (Through silicon Via) as the T type.
Fig. 1 shows that Tessera makes WLCSP (Wafer Level Chip Size Packaging) the cross-sectional configuration figure of this image sensor package.
With reference to figure 1, via a processing procedure of subscribing, form a plurality of image sensor modules for example image sensing cell 102 and a pad electrode 103 in the front of wafer 101.This wafer is adhered on the transparency carrier 104 with resin 105.Etched wafer 101 forms grooves 106, and encapsulating, bonding substrate 114 overleaf subsequently from back side fluting, back plated metal line, form the T type and connect 109, and are made outer electrode 110.Cut this wafer along line of cut 115 places at last, obtain a plurality of packaged chips.After this, see through a default processing procedure, just can form image device module, for example a video camera.
Yet the structure after the above-mentioned wafer level packaging is follow-up through after cutting step is divided into a plurality of encapsulated integrated circuit components, and a section of connecting of T type is exposed to the external world, is subject to penetration of moisture, thereby is subjected to corrosion and peels off and wait the integrity problem generation.Therefore, the encapsulation of this form often can't be lost efficacy by reliability testings such as high temperature/high humidity tests.Simultaneously, in above-mentioned manufacture method, because the connection area of this T-type connection 109 is very little, chap probably, equally easily cause the integrity problem of jointing.
The another kind of implementation of WLP is the TSV technology.Because adopt perpendicular interconnection, the TSV technology can shorten electrical interconnection length significantly, thereby has reduced signal delay, has improved electrical property.Simultaneously, the TSV technology can realize three-dimensional stacked encapsulation easily, therefore is used as the major technique means of high performance three-dimensional high-density packages.Draw owing to can realize the back side of front electrode, and have the characteristics of high density, small size, be applied to the encapsulation field of imageing sensor in recent years.
The main technique method for the treatment of through wafer interconnection construction is at present: utilize Bosch reactive ion etching-inductively coupled plasma method in crystal column surface etching blind hole; Form insulating barrier with chemical vapour deposition (CVD) oxide or nitride passivation at silicon face; Metallization silicon through hole adopts copper electric plating method filling silicon through holes, removes unnecessary copper electrodeposited coating with chemico-mechanical polishing; Grinding wafer in the back side exposes the copper conductor layer, finishes through-hole structure.
Yet as mentioned above, this technology has been used such as technologies such as RIE, CVD and CMP, makes with high costsly, thereby only uses at high-end product, is not suitable for low-end product and uses.Simultaneously, have only the very thin insulating barrier of one deck between substrate and the steel structure, make TSV interconnection form very high electric capacity, sometimes even surpassed the capacitance of standard wire interconnection mode.Used the method for dry plasma etch in the technology, entire device is exposed under the bombardment of ion, causes the inefficacy of device easily, especially to the responsive device of ion bombardment, as the GaAs imageing sensor.
Given this, be necessary to provide a kind of imageing sensor wafer-level encapsulation method and structure thereof to address the above problem.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of imageing sensor wafer-level encapsulation method and structure thereof, be used for to solve poor, the conventional TSV method of prior art T type connection reliability cost height, capacitance is big and to the problem of the irradiation damage of device.
The technical solution used in the present invention provides a kind of imageing sensor wafer-level encapsulation method, and this method may further comprise the steps:
1) provides an image sensor wafer that comprises some chips, with a transparency carrier bonding; Described chip comprises and is formed at its positive image sensing cell and is distributed in some pad electrodes around the image sensing cell;
2) afterwards image sensor wafer is carried on the back attenuate;
3) afterwards at the image sensor wafer back, the position corresponding with described pad electrode punching, form some cross sections and be down the first trapezoidal through hole, hole depth is the entire image sensor wafer that penetrates after the back of the body attenuate;
4) the structure spraying insulating barrier that obtains after step 3) also solidifies;
5) insulating barrier in first through hole continue to form cross section and is down that trapezoidal second through hole is to exposing described pad electrode; Described first through hole is coaxial with second through hole;
6) then splash-proofing sputtering metal Seed Layer, plating form metal interconnection layer successively;
7) then prepare second passivation layer and solder bump successively.
Preferably, the material of described image sensor wafer is GaAs GaAs.
Preferably, image sensor wafer and a transparency carrier use BCB as the binding agent bonding in the step 1).
Preferably, the transparency carrier in the step 1) is glass substrate.
Preferably, step 2) image sensor wafer is carried on the back attenuate and comprise that elder generation uses the mechanical lapping attenuate, then adopts the step of chemico-mechanical polishing attenuate.
Preferably, the material of described insulating barrier is epoxy resin.
Preferably, the splash-proofing sputtering metal Seed Layer comprises the step of sputter adhesion layer and Seed Layer successively in the described step 6).
Preferably, preparing passivation layer in the described step 7) utilizes the method for spin coating epoxy resin to make.
Preferably, solder bump may further comprise the steps in the described step 7): at first preparing spin coating one deck photoresist on the structure that obtains behind second passivation layer, photoetching; Use reactive ion etching that second passivation layer is carried out opening, use acetone to remove photoresist after etching is finished, sputtered metal film is as the UBM layer of solder bump; Use galvanoplastic to prepare solder bump at the UBM layer.
Preferably, the spacing of described first through hole is 150um.
The imageing sensor wafer-level package structure that the present invention also provides a kind of above-mentioned method to prepare.
Actual effect of the present invention is to have realized the wafer level packaging of imageing sensor on the basis of the through-silicon via structure of making, and this image sensor package module has smaller volume and higher package reliability.The through-hole structure that laser is made at epoxy resin has less capacitance and less signal delay, has realized higher interconnection density simultaneously.Whole manufacture craft does not have irradiation damage to device, and with IC technical process compatibility, have low-cost advantage.
Description of drawings
Fig. 1 is the cross-sectional configuration figure that shows the WLCSP encapsulating structure of imageing sensor in the prior art.
What Fig. 2 to Figure 11 showed is image sensor package operation schematic cross-section of the present invention, and it is a preferred embodiment of the present invention.
The element numbers explanation
Image sensor wafer 1
Image sensing cell 2
BCB binding agent 6
First through hole 7
Second through hole 9
Metal interconnection layer 10
Remove Seed Layer metal interconnection layer 11 afterwards
Wafer 101
Image sensing cell 102
Electrode pad 103
The T type connects 109
Metal connecting line 111
Line of cut 115
Embodiment
Below by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be used by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change under the spirit of the present invention not deviating from.
See also Fig. 2 to Figure 11.Need to prove, the diagram that provides in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy only show in graphic with the present invention in relevant assembly but not component count, shape and size drafting when implementing according to reality, kenel, quantity and the ratio of each assembly can be a kind of random change during its actual enforcement, and its assembly layout kenel also may be more complicated.
Concrete processing step of the present invention is:
A. the wafer bonding with the back of the body attenuate
(a) make pad electrode in the front of image sensing wafer, pad electrode branch is at the sensing unit periphery, and wafer material is GaAs (GaAs) wafer;
(b) at front and a slice transparency carrier bonding of image sensing wafer, use BCB (benzocyclobutene) as binding agent;
(c) use mechanical lapping and chemico-mechanical polishing to the thinning back side of image sensing wafer successively.
B. the structure that obtains after steps A is made through hole
(a) use laser to punch for the first time at the back side of wafer, form some cross sections and be down the first trapezoidal through hole;
(b) spray epoxy in wafer back and first through hole solidify to form insulating barrier then;
(c) punching for the second time on the insulating barrier in first through hole forms some cross sections and is down the second trapezoidal through hole; Suitably pad electrode is punched.
C. interconnection in the through hole
(a) sputtered with Ti W/Au layer, wherein TiW is as adhesion layer, and Au is Seed Layer;
(b) in wafer back spraying photoresist, photoetching;
(c) the Au interconnection layer is electroplated;
(d) remove photoresist and metal seed layer.
D. passivation and stud bump making
(a) on the basis that step C finishes, at disk back side spin coating last layer epoxy resin, as second passivation layer;
(b) spin coating photoresist, photoetching making mask subsequently.Use the method for plasma etching in the epoxy resin upper shed, make and expose electrode; Sputtered with Ti/Pt/Au makes UBM, removes mask subsequently;
(c) use galvanoplastic to prepare solder bump at electrode.
Concrete, please refer to shown in Figure 2.Image sensor wafer 1 comprises several chips, through default processing procedure, be formed with the image sensing assembly in each chip front side, described image sensing assembly comprises image sensing cell 2, be positioned at first passivation layer 3 on the image sensing cell and be positioned on first passivation layer, be distributed in the some pad electrodes 4 around the image sensing cell 2.Described pad electrode 4 is distributed in image sensing cell periphery nonfunctional area, and the material of selecting for use can be aluminium, Jin Hetong.The wave band that uses of imageing sensor is visible-range, and the wafer standard thickness is 350um.Wafer material is elected GaAs GaAs.
With reference to shown in Figure 3, the front of wafer 1 be bonded to a transparency carrier 5 (for example glass substrate) on thereafter.The effect that this transparency carrier 5 plays printing opacity, prevents outside contamination and exempt from mechanical damage.Simultaneously also provide mechanical support for subsequently technology.Adopt BCB (benzocyclobutene) material as the binding agent bonding during bonding, binding agent 6 is coated between wafer 1 and the substrate 5, and thickness is preferably 3um, bonding in the bonding machine, and adopt hot curing, curing temperature is elected 200 ℃ as.
With reference to shown in Figure 4, GaAs image sensor wafer reduction process in the present embodiment, adopts the quick attenuate of mechanical grinding device earlier, and then adopts chemical mechanical polish process, makes surfacing, and thickness thinning can be down to 150um.
Then, with reference to shown in Figure 5, use the ultraviolet laser of cold light wave band in the punching of GaAs image sensor wafer back, form several cross sections and be first through hole 7 trapezoidal, that hole depth is 150um.The optical maser wavelength of described ultraviolet laser is 355nm, and the zone of punching is chosen to be image sensing cell periphery nonfunctional area (namely not having the picture dot district) and corresponding to pad electrode 4 tops.This first through hole 7 penetrates wafer 1, the about 80um of hole openend diameter, and end aperture is about 50um.The spacing in adjacent two holes is 150um.
Thereafter, with reference to shown in Figure 6, adopt the method for spraying to be coated with last layer epoxy resin as insulating barrier 8 in wafer back and first through hole 7, thickness is about about 10um, in about 200 ℃ curing of temperature, is about 30min curing time then.
With reference to shown in Figure 7, use ultraviolet laser in first through hole 7, to carry out the punching second time, form cross section and be down the second trapezoidal through hole 9, the openend aperture is 50um, end aperture is 30um; This second through hole 9 is punched pad electrode 4 in right amount, and penetration depth is elected 1-3um as, and twice punching in front and back will guarantee coaxial.(namely first through hole and second through hole are coaxial)
Secondly, with reference to shown in Figure 8, sputter layer of metal Seed Layer 10 on wafer, its material is elected TiW/Au as, and thickness is 200/1000A.Wherein TiW is as adhesion layer, and Au is Seed Layer.
Afterwards, with reference to shown in Figure 9, at metal seed layer 10 spraying one deck photoresists, thickness is about 2um, and photoresist is carried out photoetching, exposes successively afterwards, development and post bake.Carry out Au on the basis of this metal seed layer 10 and electroplate, preparation metal interconnecting layer 11, electroplating thickness is 2um.Remove photoresist and metal seed layer 10 subsequently, obtain metal interconnecting layer 11.
Then, with reference to shown in Figure 10, finish on the basis of above-mentioned steps, utilize the method for spin coating epoxy resin to make second passivation layer 12, thickness is 15um, is heating and curing subsequently.
At last, with reference to shown in Figure 11, the photoresist of spin coating one bed thickness 1.7um, the photoetching making mask uses plasma etching methods such as (RIE) that epoxy resin layer is made second passivation layer 12 and carries out opening subsequently, makes and exposes electrode.Opening size is 40X40um2, uses acetone to remove photoresist after etching is finished, and etching gas is SF6 and C4F8; Sputtered with Ti/Pt/Au (being preferably 30nm/20nm/100nm) metallic film is as the UBM layer of solder bump 13 then.Remove mask subsequently.Use galvanoplastic at UBM layer preparation solder bump 13 at last.
The feature of the encapsulating structure of the imageing sensor wafer level packaging silicon through hole that is provided by described manufacture craft is:
The through hole of (1) twice laser making is coaxial, and through hole has certain tapering;
(2) second through holes penetrate pad, and the degree of depth maximum that penetrates can be 3um;
The diameter of (3) twice laser beam drilling is followed successively by openend 80 and 50um, terminal 50um and 30um, and pitch of holes is 150um;
The invention provides a kind of imageing sensor TSV encapsulation of lower cost, the capacitance that forms between TSV is lower, signal lag is less, simultaneously there is not irradiation damage in device.And because the flexibility of laser processing need not mask during the preparation through hole.
In sum, actual effect of the present invention is to have realized the wafer level packaging of imageing sensor on the basis of the through-silicon via structure of making, and this image sensor package module has smaller volume and higher package reliability.The through-hole structure that laser is made at epoxy resin has less capacitance and less signal delay, has realized higher interconnection density simultaneously.Whole manufacture craft does not have irradiation damage to device, and with IC technical process compatibility, have low-cost advantage.So the present invention has effectively overcome various shortcoming of the prior art and the tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not is used for restriction the present invention.Any person skilled in the art scholar all can be under spirit of the present invention and category, and above-described embodiment is modified or changed.Therefore, have in the technical field under such as and know that usually the knowledgeable modifies or changes not breaking away from all equivalences of finishing under disclosed spirit and the technological thought, must be contained by claim of the present invention.
Claims (11)
1. an imageing sensor wafer-level encapsulation method is characterized in that, this method may further comprise the steps:
1) provides an image sensor wafer (1) that comprises some chips, with a transparency carrier (5) bonding; Described chip comprises and is formed at its positive image sensing cell (2) and is distributed in some pad electrodes (4) around the image sensing cell;
2) afterwards image sensor wafer (1) is carried on the back attenuate;
3) afterwards at the image sensor wafer back, the position corresponding with described pad electrode (4) punching, form some cross sections and be down the first trapezoidal through hole, hole depth is the entire image sensor wafer that penetrates after the back of the body attenuate;
4) structure that obtains after step 3) sprays insulating barrier (8) and solidifies;
5) insulating barrier in first through hole continue to form cross section and is down that trapezoidal second through hole is to exposing described pad electrode (4); Described first through hole is coaxial with second through hole;
6) then splash-proofing sputtering metal Seed Layer (10), plating form metal interconnection layer (11) successively;
7) then prepare second passivation layer (12) and solder bump (13) successively.
2. imageing sensor wafer-level encapsulation method according to claim 1 is characterized in that, the material of described image sensor wafer is GaAs GaAs.
3. imageing sensor wafer-level encapsulation method according to claim 1 is characterized in that, image sensor wafer in the step 1) (1) uses BCB as the binding agent bonding with a transparency carrier (5).
4. imageing sensor wafer-level encapsulation method according to claim 1 is characterized in that, the transparency carrier in the step 1) (5) is glass substrate.
5. imageing sensor wafer-level encapsulation method according to claim 1 is characterized in that step 2) in image sensor wafer (1) is carried on the back attenuate comprise and use earlier the mechanical lapping attenuate, then adopt the step of chemico-mechanical polishing attenuate.
6. imageing sensor wafer-level encapsulation method according to claim 1 is characterized in that, the material of described insulating barrier (8) is epoxy resin.
7. imageing sensor wafer-level encapsulation method according to claim 1 is characterized in that, splash-proofing sputtering metal Seed Layer (10) comprises the step of sputter adhesion layer and Seed Layer successively in the described step 6).
8. imageing sensor wafer-level encapsulation method according to claim 1 is characterized in that, prepares passivation layer (12) in the described step 7) and utilizes the method for spin coating epoxy resin to make.
9. imageing sensor wafer-level encapsulation method according to claim 1, it is characterized in that, solder bump in the described step 7) (13) may further comprise the steps: at first preparing spin coating one deck photoresist on the back structure that obtains of second passivation layer (12), the place that needs opening is exposed in photoetching; Use reactive ion etching that second passivation layer (12) is carried out opening, use acetone to remove photoresist after etching is finished, sputtered metal film is as the UBM layer of solder bump (13); Use galvanoplastic to prepare solder bump (13) at the UBM layer.
10. imageing sensor wafer-level encapsulation method according to claim 1 is characterized in that, the spacing of described first through hole is 150um.
11. imageing sensor wafer-level package structure according to any described method preparation of claim 1-10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100267206A CN103247639A (en) | 2012-02-07 | 2012-02-07 | Wafer level packaging method and structure of image sensor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100267206A CN103247639A (en) | 2012-02-07 | 2012-02-07 | Wafer level packaging method and structure of image sensor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103247639A true CN103247639A (en) | 2013-08-14 |
Family
ID=48927027
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012100267206A Pending CN103247639A (en) | 2012-02-07 | 2012-02-07 | Wafer level packaging method and structure of image sensor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103247639A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104517864A (en) * | 2013-10-08 | 2015-04-15 | 精材科技股份有限公司 | Method of fabricating wafer-level chip package |
| CN106276783A (en) * | 2016-11-04 | 2017-01-04 | 中国工程物理研究院电子工程研究所 | A kind of low loss interconnection process of high frequency chip |
| CN109698208A (en) * | 2017-10-20 | 2019-04-30 | 新加坡有限公司 | Packaging method, image sensor package structure and the lens module of imaging sensor |
| WO2019079937A1 (en) * | 2017-10-23 | 2019-05-02 | Boe Technology Group Co., Ltd. | Integrated circuit chip, display apparatus, and method of fabricating integrated circuit chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1935630A (en) * | 2006-10-18 | 2007-03-28 | 中国科学院上海微系统与信息技术研究所 | Micro electromechanical system chip size airtight packaging vertical interconnecting structure and its manufacturing method |
| US20080284041A1 (en) * | 2007-05-18 | 2008-11-20 | Samsung Electronics Co., Ltd. | Semiconductor package with through silicon via and related method of fabrication |
| US20090289345A1 (en) * | 2008-05-21 | 2009-11-26 | Xintec, Inc. | Electronic device package and fabrication method thereof |
-
2012
- 2012-02-07 CN CN2012100267206A patent/CN103247639A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1935630A (en) * | 2006-10-18 | 2007-03-28 | 中国科学院上海微系统与信息技术研究所 | Micro electromechanical system chip size airtight packaging vertical interconnecting structure and its manufacturing method |
| US20080284041A1 (en) * | 2007-05-18 | 2008-11-20 | Samsung Electronics Co., Ltd. | Semiconductor package with through silicon via and related method of fabrication |
| US20090289345A1 (en) * | 2008-05-21 | 2009-11-26 | Xintec, Inc. | Electronic device package and fabrication method thereof |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104517864A (en) * | 2013-10-08 | 2015-04-15 | 精材科技股份有限公司 | Method of fabricating wafer-level chip package |
| CN106276783A (en) * | 2016-11-04 | 2017-01-04 | 中国工程物理研究院电子工程研究所 | A kind of low loss interconnection process of high frequency chip |
| CN106276783B (en) * | 2016-11-04 | 2018-03-02 | 中国工程物理研究院电子工程研究所 | A kind of low loss interconnection process of high frequency chip |
| CN109698208A (en) * | 2017-10-20 | 2019-04-30 | 新加坡有限公司 | Packaging method, image sensor package structure and the lens module of imaging sensor |
| CN109698208B (en) * | 2017-10-20 | 2023-06-30 | 新加坡有限公司 | Image sensor packaging method, image sensor packaging structure and lens module |
| WO2019079937A1 (en) * | 2017-10-23 | 2019-05-02 | Boe Technology Group Co., Ltd. | Integrated circuit chip, display apparatus, and method of fabricating integrated circuit chip |
| US11202370B2 (en) | 2017-10-23 | 2021-12-14 | Boe Technology Group Co., Ltd. | Integrated circuit chip, display apparatus, and method of fabricating integrated circuit chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10128211B2 (en) | Thin fan-out multi-chip stacked package structure and manufacturing method thereof | |
| US10090253B2 (en) | Semiconductor package | |
| US6008070A (en) | Wafer level fabrication and assembly of chip scale packages | |
| CN111971792B (en) | Multi-chip package with offset 3D structure | |
| CN111799227B (en) | Semiconductor device and method of forming the same | |
| CN107706521B (en) | Fan-out type antenna packaging structure and preparation method thereof | |
| US20140091471A1 (en) | Apparatus and Method for a Component Package | |
| CN111312697A (en) | Three-dimensional stacking integrated structure, multi-chip integrated structure and preparation method thereof | |
| CN111052371A (en) | Semiconductor device with laterally offset stacked semiconductor die | |
| CN105374693A (en) | Semiconductor packages and methods of forming the same | |
| CN104851841A (en) | Semiconductor package including an embedded surface mount device and method of forming the same | |
| JP3660918B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN102969305A (en) | Die-to-die gap control for semiconductor structure and method | |
| CN105225967A (en) | The method of encapsulated semiconductor device and the semiconductor device of encapsulation | |
| CN103280449A (en) | Method for manufacturing backside illuminated (BSI) CMOS image sensor | |
| CN103855173A (en) | Wafer level packaging method and packaging structure for image sensor | |
| CN102544040B (en) | Method utilizing TSV (Through-Silicon-Via) to realize wafer level package of GaAs (gallium arsenide) image sensor | |
| CN103247639A (en) | Wafer level packaging method and structure of image sensor | |
| CN110854093A (en) | Three-dimensional laminated packaging structure and manufacturing method thereof | |
| TW200845237A (en) | Sensor-type semiconductor device and manufacturing method thereof | |
| CN107611092A (en) | Wafer stage chip encapsulating structure and preparation method thereof | |
| CN115132593B (en) | Three-dimensional packaging structure and preparation method thereof | |
| US10510632B2 (en) | Method of packaging thin die and semiconductor device including thin die | |
| CN115101424A (en) | Organic interposer packaging structure and manufacturing method | |
| CN104282657A (en) | Ultra-thin multi-layer packaging body and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130814 |