CN106276783B - A kind of low loss interconnection process of high frequency chip - Google Patents
A kind of low loss interconnection process of high frequency chip Download PDFInfo
- Publication number
- CN106276783B CN106276783B CN201610963499.5A CN201610963499A CN106276783B CN 106276783 B CN106276783 B CN 106276783B CN 201610963499 A CN201610963499 A CN 201610963499A CN 106276783 B CN106276783 B CN 106276783B
- Authority
- CN
- China
- Prior art keywords
- metal
- interconnection
- chip
- high frequency
- microstrip line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
Abstract
The invention discloses a kind of low loss interconnection process of high frequency chip, belong to microelectronic component interconnection package field, this method realizes the metal interconnection between high frequency chip pad using MEMS Micromachining Technologies, the bridging distance of chip interconnection can be shortened, the loss that ghost effect introduces is reduced, improves the frequency characteristic of device；And interconnection metal dimension, controlled shape are acted charitably；The disposable interconnection of multi-chip on same function circuit board can also be realized, shortens technique fabrication cycle, available for the low-loss metal interconnection between high band even Terahertz frequency range electronic device and integration packaging.
Description
Technical field
The present invention relates to a kind of low loss interconnection process of high frequency chip, belongs to microelectronic component interconnection package neck
Domain, available for the low-loss metal interconnection between high band even Terahertz frequency range electronic device and integration packaging.
Background technology
In high frequency chip（Such as solid-state integrated amplifier）Practical application in, it is aobvious and easy for the demand of waveguide footprint scheme
See, metal interconnection technology therein is most important to ensuring the good signal transmission performance of device, particularly encapsulate in reflection,
The requirement of insertion loss and low manufacture cost.Research shows, with being continuously increased for frequency and bandwidth, existing encapsulation interconnection skill
Art has been unable to meet demand.Advanced project administration of U.S. Department of Defense（DARPA）The DAHI formulated in 2012（Diverse
Accessible Heterogeneous Integration）In the works, existing corresponding project is carrying out this respect research.It is special
It is not to enter Terahertz frequency range, high frequency and bandwidth all propose more to the waveguide footprint interconnection technique of existing microwave band
High challenge.
There are the following problems in research process for current high frequency solid state integrated amplifier：
（1）Loss problem：In the waveguide footprint of high frequency solid state integrated amplifier module, between module chips and waveguide
Low-loss transition connection is current active demand, and the mode of common metal line bonding interconnection at present realizes chip and transmission
Line（Microstrip line, co-planar waveguide）Between connection, be encapsulation in key technology.With the lifting of working frequency, metal interconnection
Delay and power consumption be continuously increased, interconnection be substituted transistor size, turn into the principal element and limit of decision-making circuit performance
Make the bottleneck of its external development.
（2）Pad size：For the consideration for reducing power consumption, high frequency chip（>100GHz）There is bonding pad area（<30μm）
With pad spacing（10 μm or so）The problem of too small, reach traditional gold wire bonding technological limit, practical operation is difficult.
The content of the invention
The present invention is to overcome above-mentioned technological deficiency, it is proposed that a kind of low loss interconnection process of high frequency chip, is used
MEMS Micromachining Technologies, can have the advantages that packaging density is big, interconnection line is short, ghost effect is small, be advantageous to high frequency height
Speed application, can also realize the disposable interconnection of multi-chip on same function circuit board, shorten technique fabrication cycle, available for height
Low-loss metal interconnection and integration packaging between frequency range even Terahertz frequency range electronic device.
Technical scheme is as follows：
The low loss interconnection process of a kind of high frequency chip, it is characterised in that step is：
（1）Chip or microstrip line substrate are by the smooth substrate being mounted on for support of solder, to ensure follow-up micro-nano
The progress of processing technology；
（2）Uniform coating polyimide thickness glue forms polyimide covercoat on chip or microstrip line substrate, for protecting
Protect chip, microstrip line substrate damages from subsequent technique；
（3）Photoresist is coated on polyimide covercoat, and by photoetching, by chip, the pad area of microstrip line substrate
The polyimide covercoat in domain is exposed；
（4）The polyimide covercoat of exposed region is removed using dry etching, on exposed chip or microstrip line substrate
Metal pad or welding region；
（5）The photoresist on polyimide covercoat is removed, obtains polyimide covercoat；
（6）Metal is prepared on polyimide covercoat and on the metal pad or welding region of chip or microstrip line substrate
Grown layer, the Seed Layer thickeied is electroplated mainly as follow-up interconnection area metal level；
（7）Photoresist is coated on metal grown layer, the through hole arranged by photoetching in non-interconnection region fabrication cycle
Pattern, expose the metal grown layer below through-hole pattern, primarily as the through hole subsequently prepared for removing polyimides glue
Mask；
（8）Using wet etching, the metal grown layer at lead to the hole site is removed, exposes polyimide covercoat, then goes
Except all photoresists, removing glue through hole is reserved on metal grown layer；
（9）Thick photoresist is sprayed above, and exposes the metal grown layer of interconnection area by photoetching, forms follow-up plating
The mask of step；
（10）Using the metal grown layer of interconnection area as Seed Layer, the metal life of interconnection area is thickeied by way of plating
Long layer, then removes thick photoresist, realizes the making of chip chamber metal interconnecting wires；
（11）Using reactive ion etching, polyimide covercoat is removed, while peels off the metal for removing non-interconnection region
Grown layer, realize the metal interconnection between chip and microstrip line substrate or between different chips.
Above-mentioned interconnection process step（1）Employed in solder can be conductive silver glue or be low temperature pre-shaped weld tabs
（SnPb, SnPbIn etc.）.
In above-mentioned interconnection process, the pad of chip can be Al pads or Au pads.
Above-mentioned interconnection process step（1）In, after attachment, between the upper surface of chip and adjacent microstrip line substrate or different cores
Difference in height between the upper surface of piece is less than 5 μm.
In above-mentioned interconnection process, step（6）It is middle that metal grown layer is grown by the way of magnetron sputtering or evaporation；Metal is given birth to
The composition of long layer has unlike material according to different pads.
Above-mentioned interconnection process step（9）In, the thickness of the thick photoresist is 10-15 μm, is selected according to electroplating time true
Determine the thickness of thick photoresist.
Above-mentioned interconnection process step（10）In, the thickness for the metal grown layer that the plating thickeies is 15-20 μm.
Beneficial effects of the present invention are as follows：
The present invention uses MEMS Micromachining Technologies, and metal is mutual between different chips or between chip and microstrip line substrate
Apart from short, it is small that ghost effect introduces loss, improves the frequency characteristic of device for bridging even；Interconnect metal dimension, controlled shape row
It is good；The disposable interconnection that multi-chip is integrated on same function substrate can be achieved, shorten technique fabrication cycle.
Brief description of the drawings
Fig. 1 is the schematic diagram that chip and microstrip line substrate are mounted in substrate by the present invention；
Fig. 2 is the schematic diagram that polyimide covercoat is formed on chip and microstrip line substrate in Fig. 1；
Fig. 3 is one layer of photoresist and photoetching exposed pad overlying regions will to be coated on the chip in Fig. 2 and microstrip line substrate
The schematic diagram of polyimide covercoat；
Fig. 4 is by welding disking area exposes on the chip in Fig. 3 and microstrip line substrate schematic diagram；
Fig. 5 is the schematic diagram for removing all photoresists in Fig. 4；
Fig. 6 is the schematic diagram of whole upper surface formation metal grown layer in Figure 5；
Fig. 7 is the schematic diagram that through-hole pattern is formed on the basis of Fig. 6；
Fig. 8 is to remove the metal grown layer of the through hole in Fig. 7 and remove the schematic diagram after all photoresists；
Fig. 9 is to spray thick photoresist and photoetching exposed pad region on chip and microstrip line substrate on the basis of Fig. 8
Schematic diagram；
Figure 10 is that formation thickeies metal level and removes the schematic diagram after photoresist on the basis of Fig. 9；
Figure 11 is that the polyimide covercoat of non-welding disking area on chip and microstrip line substrate is removed on the basis of Figure 10
Schematic diagram；
Figure 12 is the schematic top plan view formed in Figure 11 after interconnection structure.
Embodiment
As shown in figs. 1-12, a kind of low loss interconnection process of high frequency chip, its step are：
（1）Chip or microstrip line substrate are by the smooth substrate being mounted on for support of solder, to ensure follow-up micro-nano
The progress of processing technology；
（2）Uniform coating polyimide thickness glue forms polyimide covercoat on chip or microstrip line substrate, for protecting
Protect chip, microstrip line substrate damages from subsequent technique；
（3）Photoresist is coated on polyimide covercoat, and by photoetching, by chip, the pad area of microstrip line substrate
The polyimide covercoat in domain is exposed；
（4）The polyimide covercoat of exposed region is removed using dry etching, on exposed chip or microstrip line substrate
Metal pad or welding region；
（5）The photoresist on polyimide covercoat is removed, obtains polyimide covercoat；
（6）Metal is prepared on polyimide covercoat and on the metal pad or welding region of chip or microstrip line substrate
Grown layer, the Seed Layer thickeied is electroplated mainly as follow-up interconnection area metal level；
（7）Photoresist is coated on metal grown layer, the through hole arranged by photoetching in non-interconnection region fabrication cycle
Pattern, expose the metal grown layer below through-hole pattern, primarily as the through hole subsequently prepared for removing polyimides glue
Mask；
（8）Using wet etching, the metal grown layer at lead to the hole site is removed, exposes polyimide covercoat, then goes
Except all photoresists, removing glue through hole is reserved on metal grown layer；
（9）Thick photoresist is sprayed above, and exposes the metal grown layer of interconnection area by photoetching, forms follow-up plating
The mask of step；
（10）Using the metal grown layer of interconnection area as Seed Layer, the metal life of interconnection area is thickeied by way of plating
Long layer, then removes thick photoresist, realizes the making of chip chamber metal interconnecting wires；
（11）Using reactive ion etching, polyimide covercoat is removed, while peels off the metal for removing non-interconnection region
Grown layer, realize the metal interconnection between chip and microstrip line substrate or between different chips.
Above-mentioned interconnection process step（1）Employed in solder can be conductive silver glue or be low temperature pre-shaped weld tabs
（SnPb, SnPbIn etc.）.
In above-mentioned interconnection process, the pad of chip can be Al pads or Au pads.
Above-mentioned interconnection process step（1）In, after attachment, between the upper surface of chip and adjacent microstrip line substrate or different cores
Difference in height between the upper surface of piece is less than 5 μm.
Above-mentioned interconnection process step（2）In, it is coated using sol evenning machine, 1500 turns/min of spin coating machine speed, thickness leads to
Time control is crossed, all chips/microstrip line substrate is completely covered；Post bake：120 DEG C, 60min.
Above-mentioned interconnection process step（3）In, photoresist is sprayed using deep trench glue spreader, glue is thick about 10 μm；Front baking：
120 DEG C, 60 min；Time for exposure：80 second；Developing time：3 min.
Above-mentioned interconnection process step（4）In, using reactive ion etching machine（RIE）Perform etching.
In above-mentioned interconnection process, step（6）It is middle that metal grown layer is grown by the way of magnetron sputtering or evaporation；Metal is given birth to
The composition of long layer has unlike material according to different pads.
For Au pads：Cr（Adhesion layer）-Au（Growth was once）, thickness 200nm-200nm；
For Al pads：Ti（Al/Cr）（Adhesion layer）-Pt（Pd/Cu）（Diffusion impervious layer）-Au（Grown layer）, thickness
200nm-200nm-200nm。
Above-mentioned interconnection process step（9）In, the thickness of the thick photoresist is 10-15 μm, is determined according to electroplating time.
Above-mentioned interconnection process step（10）In, the thickness for the metal grown layer that the plating thickeies is 15-20 μm.
Claims (6)
1. the low loss interconnection process of a kind of high frequency chip, it is characterised in that step is：
（1）Chip or microstrip line substrate pass through the smooth substrate being mounted on for support of solder；After attachment, chip and adjacent micro-
Difference in height between upper surface with line substrate or between the upper surface of different chips is less than 5 μm；
（2）Uniform coating polyimide thickness glue forms polyimide covercoat on chip or microstrip line substrate；
（3）Photoresist is coated on polyimide covercoat, and by photoetching, by chip, the welding disking area of microstrip line substrate
Polyimide covercoat is exposed；
（4）The polyimide covercoat of exposed region is removed using dry etching, the metal on exposed chip or microstrip line substrate
Pad or welding region；
（5）The photoresist on polyimide covercoat is removed, obtains polyimide covercoat；
（6）Metal growth is prepared on polyimide covercoat and on the metal pad or welding region of chip or microstrip line substrate
Layer；
（7）Photoresist is coated on metal grown layer, the through-hole pattern arranged by photoetching in non-interconnection region fabrication cycle,
Expose the metal grown layer below through-hole pattern；
（8）Using wet etching, the metal grown layer at lead to the hole site is removed, exposes polyimide covercoat, then removes institute
There is photoresist, removing glue through hole is reserved on metal grown layer；
（9）Thick photoresist is sprayed above, and exposes the metal grown layer of interconnection area by photoetching, forms follow-up plating step
Mask；
（10）Using the metal grown layer of interconnection area as Seed Layer, the metal growth of interconnection area is thickeied by way of plating
Layer, then removes thick photoresist, realizes the making of chip chamber metal interconnecting wires；
（11）Using reactive ion etching, polyimide covercoat is removed, while peels off the metal growth for removing non-interconnection region
Layer, realize the metal interconnection between chip and microstrip line substrate or between different chips.
A kind of 2. low loss interconnection process of high frequency chip according to claim 1, it is characterised in that：Step（1）
Employed in solder be conductive silver glue or be low temperature pre-shaped weld tabs.
A kind of 3. low loss interconnection process of high frequency chip according to claim 1, it is characterised in that：The chip
Pad be Al pads, or Au pads.
A kind of 4. low loss interconnection process of high frequency chip according to claim 1, it is characterised in that：Step（6）
It is middle that metal grown layer is grown by the way of magnetron sputtering or evaporation.
A kind of 5. low loss interconnection process of high frequency chip according to claim 1, it is characterised in that：Step（9）
In, the thickness of the thick photoresist is 10-15 μm, is determined according to electroplating time.
A kind of 6. low loss interconnection process of high frequency chip according to claim 1, it is characterised in that：Step（10）
In, the thickness for the metal grown layer that the plating thickeies is 15-20 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610963499.5A CN106276783B (en) | 2016-11-04 | 2016-11-04 | A kind of low loss interconnection process of high frequency chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610963499.5A CN106276783B (en) | 2016-11-04 | 2016-11-04 | A kind of low loss interconnection process of high frequency chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106276783A CN106276783A (en) | 2017-01-04 |
| CN106276783B true CN106276783B (en) | 2018-03-02 |
Family
ID=57720449
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610963499.5A Expired - Fee Related CN106276783B (en) | 2016-11-04 | 2016-11-04 | A kind of low loss interconnection process of high frequency chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106276783B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5198385A (en) * | 1991-01-11 | 1993-03-30 | Harris Corporation | Photolithographic formation of die-to-package airbridge in a semiconductor device |
| CN102376629A (en) * | 2010-08-17 | 2012-03-14 | 中国科学院上海微系统与信息技术研究所 | Method for realizing through-silicon-via interconnection by suspension photoresist |
| CN102645359A (en) * | 2012-04-11 | 2012-08-22 | 上海交通大学 | Preparation method of copper-tin intermetallic compound micro-stretching sample for chip interconnection |
| CN103247639A (en) * | 2012-02-07 | 2013-08-14 | 中国科学院上海微系统与信息技术研究所 | Wafer level packaging method and structure of image sensor |
| CN105140140A (en) * | 2015-07-16 | 2015-12-09 | 北京工业大学 | Novel wafer level tin solder micro bump manufacturing method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012171663A1 (en) * | 2011-06-15 | 2012-12-20 | Eth Zurich | Low-temperature wafer-level packaging and direct electrical interconnection |
-
2016
- 2016-11-04 CN CN201610963499.5A patent/CN106276783B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5198385A (en) * | 1991-01-11 | 1993-03-30 | Harris Corporation | Photolithographic formation of die-to-package airbridge in a semiconductor device |
| CN102376629A (en) * | 2010-08-17 | 2012-03-14 | 中国科学院上海微系统与信息技术研究所 | Method for realizing through-silicon-via interconnection by suspension photoresist |
| CN103247639A (en) * | 2012-02-07 | 2013-08-14 | 中国科学院上海微系统与信息技术研究所 | Wafer level packaging method and structure of image sensor |
| CN102645359A (en) * | 2012-04-11 | 2012-08-22 | 上海交通大学 | Preparation method of copper-tin intermetallic compound micro-stretching sample for chip interconnection |
| CN105140140A (en) * | 2015-07-16 | 2015-12-09 | 北京工业大学 | Novel wafer level tin solder micro bump manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106276783A (en) | 2017-01-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI626697B (en) | Semiconductor device and method of forming fine pitch rdl over semiconductor die in fan-out package | |
| TWI606523B (en) | Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (ewlb-mlp) | |
| TWI567866B (en) | Semiconductor device and method of forming an interconnect structure with tsv using encapsulant for structural support | |
| TWI649811B (en) | Thin 3D fan-out embedded wafer level package for application processor and memory integration | |
| TWI499000B (en) | Semiconductor device and method of forming dual-active sided semiconductor die in fan-out wafer level chip scale package | |
| TWI508202B (en) | Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structure | |
| CN108878296B (en) | Preparation method of three-dimensional micro-convex point | |
| US8058100B2 (en) | Method for fabricating chip scale package structure with metal pads exposed from an encapsulant | |
| TWI520287B (en) | Semiconductor device and method of forming rdl wider than contact pad along first axis and narrower than contact pad along second axis | |
| TW201108335A (en) | Semiconductor device and method of forming dam material around periphery of die to reduce warpage | |
| TW200929388A (en) | Semiconductor device and method of forming the device using sacrificial carrier | |
| CN102496580B (en) | A kind of formation method of solder bump | |
| JP2004039929A (en) | Semiconductor device and method for manufacturing bump of semiconductor chip | |
| JP3660918B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN109244231B (en) | Packaging structure and packaging method of acoustic surface filter chip | |
| CN102437065A (en) | High-reliability chip scale packaging method | |
| CN112769411A (en) | Wafer-level packaging method and device for surface acoustic wave chip | |
| CN109003959B (en) | A kind of high thermal conductivity encapsulating structure that bonding wire is preforming and its manufacturing method | |
| CN106276783B (en) | A kind of low loss interconnection process of high frequency chip | |
| CN102437135A (en) | Wafer-level columnar bump packaging structure | |
| JP2005019522A (en) | Semiconductor device and its manufacturing method | |
| CN102496603A (en) | Chip level packaging structure | |
| US20050266611A1 (en) | Flip chip packaging method and flip chip assembly thereof | |
| CN111403355A (en) | Packaging structure of complete plastic package antenna and preparation process thereof | |
| CN110299330A (en) | A kind of encapsulating structure and packaging method of wafer stage chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180302 Termination date: 20211104 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |