WO2012171663A1

WO2012171663A1 - Low-temperature wafer-level packaging and direct electrical interconnection

Info

Publication number: WO2012171663A1
Application number: PCT/EP2012/002554
Authority: WO
Inventors: Stéphane KÜHNE
Original assignee: Eidgenoessische Technische Hochschule Zurich ETHZ
Current assignee: Eidgenoessische Technische Hochschule Zurich ETHZ
Priority date: 2011-06-15
Filing date: 2012-06-15
Publication date: 2012-12-20
Anticipated expiration: 2013-12-15

Abstract

Proposed is a low-temperature wafer-level bonding process based on hybrid bonding of a device substrate (3) with a cap substrate (1), which cap substrate (1) features through silicon vias (2), wherein simultaneous mechanical and electrical bonding of different materials at low temperature is used, without a prior planarization of the heterogeneous substrates before the hybrid bonding process. Therein the hybrid bonding process is based on low-temperature direct bonding (LTDB) and transient liquid phase bonding (TLPB, and during the wafer-level hybrid bonding process, ultra-thin AuSn contact pads (9) are forming local electrical interconnects between metallization layers of the device substrate (3) and the through silicon vias (2) of the cap substrate (1) by transient liquid phase bonding (TLPB). During the wafer-level hybrid bonding process simultaneously, a strong mechanical bond is performed in the low-temperature direct bonding (LTDB) by hydrophilic direct bonding of plasma activated Si and Si02 interfaces between device substrate (3) and cap substrate (2).

Description

TITLE

Low-temperature wafer-level packaging and direct electrical interconnection TECHNICAL FIELD

The present invention relates to wafer-level bonding processes and electronic components made using such a process.

PRIOR ART

There is a major interest for wafer-level and 3D packaging solutions in microelectronic and MEMS development. The demand for an ever-growing number functionalities in products requires the reduction of package size and cost and an improvement in reliability at the same time. New packaging and system integration solutions develop toward system in package (SiP) technologies. Thereby the through silicon via (TSV) technology is regarded as an example of MEMS fabrication enabling high density interconnection, true wafer- level packaging and MEMS designs with significantly reduced form factor. Thus, the combination of wafer bonding and TSV technology is a promising platform for wafer-level hermetic packaging and interconnection. The advantages of TSVs in 3D packaging are shorter signal paths, reduced power consumption, and higher I/O densities. Further, TSV packages are compatible with today's surface mount technologies, e.g. ball grid arrays and enable a significant reduction of parasitic capacitances.

The prevailing metal based TSV technology relies on deep reactive ion etching, CVD passivation and seed metal deposition, trench refill by electroplating and a CMP process for wafer thinning in order to expose the vias. The major challenges of such a process are the achievable aspect-ratio of the vias due to limited conformal deposition of insulating and seed layers in narrow trenches, as well as void-free trench refill and the thinning/polishing of the heterogeneous substrates. For both, 3D integrated circuit (3D IC) stacking and MEMS packaging applications, the two main classes of strategies are the via first approach, a front-end process, and the via last approach, a back-end process. Each of these different ways of elaborating the vias has its advantages and drawbacks in terms of electrical performances, refilling materials and cost. However, there is a general interest in reducing the complexity and number of back-end process steps for fragile and expensive device substrates. Yet another key technology for successful system integration is the electrical interconnection of the stacked structures. Approaches are based on solder bonding, which enables void free bonding at low temperatures. However, the relatively thick solder metallization of several microns has to be deposited by electroplating and additional process steps are required for a precise bond gap control.

So the two key technologies for successful 3D system integration and 3D packaging are the through silicon via (TSV) technology and the electrical interconnection of the stacked structures. Additionally, there is a substantial interest in reducing the complexity and number of back-end process steps for the packaging of fragile and expensive device substrates. For both, 3D integrated circuit (3D IC) stacking and MEMS packaging applications, the two main classes of strategies are the via first approach, a front-end process, and the via last approach, a back-end process. Each of these different ways of elaborating the TSVs has its advantages and drawbacks in terms of electrical performances, refilling materials and cost. However, both involve complex processing sequences to achieve the bonding and electrical connection.

Recent advances in 3D IC technology demonstrated the potential of metal direct bonding for the stacking and interconnection of ICs, as well as direct bonding of metal and dielectrics at the same time. This technology involves a demanding planarization process for adequate mechanical and electrical properties. On the other hand, Cu-Cu thermo- compressive bonding requires an annealing at elevated temperatures in order to allow Cu inter-diffusion and grain growth to achieve high enough bonding strength and low number of interfacial voids. For the packaging of fragile or released MEMS structures a planarization is often challenging to achieve. Therefore, a vast majority of MEMS packaging approaches are based on solder bonding, which enables void free bonding at low temperatures. Bumps or island are used for electrical interconnection and a sealing rim is applied to close the cavity. However, the relatively thick solder metallization of several microns has to be deposited by electroplating and additional process steps are required for a precise bond gap control, which again increases the process complexity. One approach proposed, is to use a hybrid bonding process relying on direct bonding and local ultra-thin AuSn eutectic bonding using an eutectic mixture having a melting point of above 275° C, so working at a process temperature of 300° C. This technology enables the bonding and local interconnection of two substrates. However, the process is based on rather high temperature eutectic bonding, which is challenging to apply with ultra-thin interconnects compared to the proposed transient liquid phase bonding (TLPB). Further, the local interconnection of metallization layers is not suited for packaging applications, since it is not enabling an electrical connection through the package, e.g. hermetic packaging and electrical connection by means of TSVs.

SUMMARY OF THE INVENTION

The proposed low-temperature wafer-level packaging technology is providing means to mechanically bond a device substrate with a cap substrate and simultaneously electrically connect the device substrate. The encapsulation and direct interconnection is achieved by hybrid bonding of a cap substrate featuring through silicon vias (TSV). Therewith, both encapsulation and electrical interconnection of the device substrate are performed simultaneously and do not require back-end processing. The hybrid bonding process is based on low-temperature direct bonding (LTDB) and transient liquid phase bonding (TLPB). The direct bond is defining the geometry and performing the mechanical bonding and sealing of the cavities on the packaged substrate. Whereas the TLP bond is forming self-planarized interconnects between the packaged device substrate and the TSVs of the cap substrate.

In the proposed approach to overcome the prior art limitations, the TSVs are integrated in the cap substrate and therewith the fabrication process of the MEMS device substrate is not affected in contrast to approaches where the electrical interconnection is performed through the MEMS substrate. The encapsulation and electrical interconnection are carried out simultaneously in one single hybrid bonding process. The electrical interconnection by TSVs is performed through the fully pre-processed cap substrate and does therefore not necessitate back-end processing of neither the MEMS device nor the cap substrate. The hybrid wafer bonding and interconnection is the last process step.

The hybrid bonding technology is combining the advantage of the bond gap defining mechanical bond and the self-planarization of reflown electrical interconnections. During the wafer-level hybrid bonding process, ultra-thin AuSn contact pads are forming local electrical interconnects between the metallization layers of the device substrate and the TSVs of the cap substrate by transient liquid phase bonding (TLP). Simultaneously, a strong mechanical bond is performed by hydrophilic direct bonding of plasma activated Si and Si02 interfaces. The direct bond is defining the geometry and allows for precise cavity gap control between device and cap substrate, since a self-planarization of the interconnects is taking place during the TLP bonding. The electrical interconnect is formed by reflow and interdiffusion of the AuSn metallization and the TSVs of the bonded cap substrate. Thus, no planarization of heterogeneous substrates by chemical-mechanical polishing (CMP) is required before bonding. Further, the formed intermetallic compounds (IMC) during TLP bonding feature an increased temperature stability compared to the one of the starting materials. Finally, the low-temperature process is preferably not exceeding 250°C, which is offering the possibility of multiple material integration and full CMOS compatibility.

The developed low-temperature bonding technology/process for wafer-level packaging with direct electrical interconnection solves, among others, the following issues:

• Device wafer capping and electrical interconnection in one bonding process

• Bonding of a fully preprocessed device wafer and a cap wafer featuring through silicon vias

• No back-end processing necessary

· Capping with well defined geometry

• Self-planarized electrical interconnection

• No CMP of heterogeneous bonding interfaces necessary (however nevertheless possible)

• High temperature stability despite of low-annealing temperature

To summarize therefore, a low-temperature wafer-level packaging technology based on hybrid bonding of a device substrate with a cap substrate is proposed, which features through silicon vias (TSV). The technology allows for simultaneous mechanical and electrical bonding of different materials at low temperature, without a planarization of the heterogeneous substrates before the hybrid bonding process.

The hybrid bonding process is based on low-temperature direct bonding (LTDB) and transient liquid phase bonding (TLPB). Therewith, the properties of the mechanical and the electrical bond are optimized and tailored accordingly. The mechanical direct bond between silicon, oxide or other dielectric interfaces is strong with a precisely defined geometry. Besides the geometry defining property the direct bond is performing the sealing of the cavities on the packaged substrate. Whereas the self-planarized metal interconnects of the TLPB are forming local ohmic contacts between the packaged device substrate and the TSVs of the cap substrate.

In summary the following technical challenges and issues are solved by the packaging technology: - Improved mechanical and electrical bond properties

- Separate mechanical and electrical bonding in one low-temperature process

-Simultaneous bonding of different materials Si-Si, Si-Si0₂, Si0₂-Si0₂, AuSn-Cu, AgSn- Cu

-No planarization of heterogeneous or structured substrates (Silicon, dielectrics, metals) required

- Strong mechanical bond, precise geometry definition, hermetic sealing

- Self-planarized metal interconnection (CuSn intermetallic phases)

Therefore, the hybrid bonding technology provides means to seal and electrically connect MEMS device substrates by bonding a cap substrate featuring through silicon vias (TSV) in one low-temperature process and on wafer-level. The low process temperature allows the integration of multiple-materials in MEMS as well as system integration in 3D packaging and 3D stacked MEMS applications. Further, the process is CMOS compatible and could therewith be applied for stacked 3D CMOS/MEMS integration and packaging. As concerns the process flow, the technology concept preferably is to include the local deposition of thin AuSn interconnects into recesses on the MEMS device substrate. The deposited AuSn layer thickness is adapted according to the actual recess depth and TSV projection length. The deposited AuSn layer preferably has an excess thickness of 200nm with respect to final interconnect height after TLP bonding. This excess thickness ensures the sufficient contact between AuSn and TSVs during the reflow and self-planarization of the interconnects.

Thus, one dry etch step, a diffusion barrier and AuSn deposition are the only mandatory process steps to be integrated in the complete fabrication process of any arbitrary MEMS substrate to be packaged with hybrid bonding of a TSV cap wafer. The AuSn can also be deposited and structured onto the TSV cap substrate, if the MEMS substrate is not compatible with the deposition process (compare Figures 1.1 and 1.2).

E.g. after the plasma activation for the direct bond, the wafers are aligned and brought into contact. The actual bonding process is performed by heating the stack to 250°C and applying a bond tool force to the stack. The direct bond as well as the TLP bonds require e.g. an extended annealing at 250°C for four hours in order to allow the complete polymerization of hydroxyl functional groups which form strong covalent siloxane bonds, as well as to achieve an isothermal solidification and homogenization of the CuSn intermetallic compounds in the TLP bond. More generally speaking, the present invention relates to a low -temperature wafer-level bonding process based on hybrid bonding of a device substrate with a cap substrate, which cap substrate features through silicon vias. The through silicon vias are normally based on copper or completely made of copper conductive material passing through openings in the cap substrate in a direction essentially perpendicular to the main plane of the substrate. According to the present invention, simultaneous mechanical and electrical bonding of different materials at low temperature is used in the process, preferably without a prior planarization of the heterogeneous substrates before the hybrid bonding process. The hybrid bonding process is based on low-temperature direct bonding (LTDB) for the formation of a mechanical bond and concomitant transient liquid phase bonding (TLPB) for the formation of local ohmic contacts, preferably at a process temperature not exceeding 250°C, this temperature preferably never being exceeded over the whole bonding process. However also somewhat higher process temperatures can be used.

During the wafer-level hybrid bonding process, ultra-thin AuSn contact pads are forming local electrical interconnects between metallization layers of the device substrate and the through silicon vias of the cap substrate by transient liquid phase bonding (TLPB).

During the wafer-level hybrid bonding process simultaneously, a strong mechanical bond is performed in the low-temperature direct bonding (LTDB) by hydrophilic direct bonding of plasma activated Si and Si0₂ interfaces between device substrate and the cap substrate. According to the invention, the ultrathin AuSn pads have a composition close to or equal to the tin rich eutectic mixture of these two constituents, preferably with a melting point in the range of 225-235°C, more preferably in the range of 230-233°C. Using this particular mixture ratio of the two components makes it possible to use much lower temperatures than hitherto available for concomitant mechanical low-temperature bonding and transient liquid phase bonding. Figure 1.0 shows the phase diagram for the binary mixture of Au and Sn. While conventionally at a higher temperature of the Au rich eutectic at a temperature of 278°C the process is carried out (illustrated with circle 5), it was found that the second eutectic (illustrated with circle 6) allows to work at a lower temperature of 231.9°C allowing for much more gentle processing conditions and allowing for more delicate electronic and/or electric compounds to be mounted on the device, while nevertheless providing an excellent ohmic bond, inter alia due to the fact that intermetallic species are formed between tin and copper in the interfacial region between the via and the AuSn pad. On the other hand surprisingly the low Au content of this eutectic is still sufficient to prevent oxidation and corresponding deactivation of the Sn prior to the bonding process. The pads are preferably made by using masking technology such as photolithography, and subsequent evaporation deposition or sputtering, more preferably by first evaporation depositing or sputtering a layer of Sn and subsequently, in the corresponding proportion, evaporation depositing or sputtering a layer of Au. This means that the two components of the AuSn pad are subsequently and overlapping applied to the corresponding region of concern. Due to the migration properties of the Au applied to the surface of the Sn, the corresponding alloy automatically forms due to the thin layer structure. In the alternative it would also be possible to apply the mixture of the two constituents of the ally directly and conjointly.

The AuSn pads according to yet another preferred embodiment have an excess thickness in the range of 100-500 nm, preferably in the range of 150-300 nm, most preferably in the range of 200 nm, with respect to the final interconnect height of the transient liquid phase bonding.

According to another preferred embodiment, the overall thickness of the pads is less than 1.5 pm, preferably less than 1 μ, more preferably in the range of 200-700 nm, most preferably in the range of 500 nm.

The AuSn pads are, prior to the bonding process, preferably applied to the through silicon vias, the latter preferably being based on or consisting of copper.

In the alternative or additionally, the AuSn pads can be applied to the device substrate prior to the bonding process. In this case, the AuSn pads can be applied to electrical conductors located on or in the device substrate, to electrical contacts of electronic and/or electromechanical and/or electrooptical elements mounted on the and/or in the device substrate, or to silicon surface areas of the device substrate, or to a combination of such locations.

The conducting material of the through silicon vias is, as already pointed out above, preferably based on or consisting of Cu. Further preferably the process of the transient liquid phase bonding is carried out such that at the contact interface between the AuSn pads and the through silicon vias intermetallic species between copper and tin are formed, preferably in the form of Cu₃Sn and/or Cu₆Sn₅.

The simultaneous mechanical and electrical bonding of different materials at low temperature can be, according to yet another preferred embodiment, carried out for a time span of 30-600 min, preferably in the range of 120-520 min, preferably in the range of 480 min.

According to yet another preferred embodiment, simultaneous mechanical and electrical bonding of different materials at low temperature can be carried out using a bond tool pressure of 1-5 bar, preferably in the range of 2-4 bar, most preferably in the range of 3 bar.

According to yet another preferred embodiment, the process is carried out under low pressure atmosphere conditions, most preferably under vacuum conditions, with a residual pressure of preferably not more than lxlO^*3 mbar or not more than lxlO^"4 mbar. The pressure values depend on the application, or the target cavity pressure after bonding, respectively. With a typical bonding tool one can get a bonding chamber pressure as low as l x lO^"5 mbar.

The silicon contact surfaces for the low-temperature direct bonding (LTDB) can be prepared for the bonding step by oxygen plasma activation, preferably for a time span in the range of 30-120 seconds with a coil and platen power of 300-1200 W and 10-50 W, respectively, followed by rinsing of the contact surfaces with water, preferably with deionized water, and/or surface hydration with silanol (SiOH) functional groups and subsequent essentially complete, preferably fully complete drying of the contact surfaces prior to contacting the contact surfaces for the establishment of the low-temperature direct bond (LTDB).

The device substrate and/or cap substrate can be structured such that in the final device they enclose a cavity with functional elements of an electronic circuit and/or electronic and/or electromechanical and/or electrooptical element, in particular measurement element, wherein preferably (but not necessarily) in the final device the cavity is sealed and under vacuum.

The device substrate and/or cap substrate can e.g. be a MEMS device.

In addition to the above-mentioned process, the present invention also relates to a device made using such a process, wherein preferably the device substrate and/or cap substrate is a MEMS device.

In such a device, preferably the device substrate and/or cap substrate are structured enclosing a cavity with functional elements of an electronic circuit and/or electronic and/or electromechanical and/or electrooptical element, in particular measurement element, as well as combinations thereof, wherein preferably the cavity is sealed and under vacuum. Further embodiments of the invention are laid down in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention are described in the following with reference to the drawings, which are for the purpose of illustrating the present preferred embodiments of the invention and not for the purpose of limiting the same. In the drawings,

Fig. 1.0 shows the phase diagram of AuSn with circles indicating the Au rich (left) and the Sn rich (right) eutectics;

Fig. 1.1 shows a schematic cross-section of device and cap substrate for the wafer- level packaging; the device substrate features a metallization and the AuSn interconnects;

Fig. 1.2 shows a schematic cross-section of device and cap substrate for the wafer- level packaging; the AuSn interconnects are deposited on the TSVs of the cap substrate;

Fig, 1.3 shows a schematic cross-section of device and cap substrate for the wafer- level packaging; the AuSn interconnects are deposited directly on the device layer;

Fig. 1.4 shows a schematic cross-section of device and cap substrate for the wafer- level packaging; the AuSn interconnects are deposited on the TSVs of the cap substrate;

Fig. 2.1 shows a CAD model of the fabricated test structure for process validation, a) the two separately fabricated substrates and b) the device after hybrid bonding or packaging, respectively; the TSV cap substrate is displayed transparent for a better visibility of the structure;

Fig. 2.2 shows a schematic process flow of the TSV wafer fabrication;

Fig. 2.3 shows a schematic process flow of the device wafer processing (a-c) and the wafer- level packaging (d-e);

Fig. 2.4 shows photographs of TSV cap substrate (left) and device substrate with metallization and AuSn interconnect pads deposited into the cavity (right); Fig. 2.5 shows WLI measurements of TSV projection (a) and device cavity with deposited metal and AuSn pad. A superposition of the profiles A:A and B:B is plotted in c);

Fig. 2.6 shows a microscope picture of a device cross-section;

Fig. 2.7 shows SEM pictures of device cross-sections: a) device cavity area showing TLP bonded TSV as well as the conformal TSV passivation and the direct bond; b) TLP bond interface analysis with device metallization and the formed CuSn IMCs;

Fig. 2.8 shows a wafer-map of performed resistance measurements. The resistance was always measured between two TSVs and evidences a systematic variation due to a non-uniform device metal sheet resistance; the inverted markers indicate the location of the I-V measurement samples plotted in Figure 2.9; and

Fig. 2.9 shows I-V measurement curves of packaged samples; the CAD drawing indicates the DC probing path (red) for the performed measurements between two TSVs; the measurements show the formation of ohmic contacts; the location of the I-V measurement samples on the wafer is highlighted by the inverted markers in Figure 2.8. DESCRIPTION OF PREFERRED EMBODIMENTS

The presented wafer-level packaging technology enables the direct integration of electrical interconnects during low-temperature wafer bonding of a cap substrate featuring through silicon vias (TSV) onto substrate such as a MEMS device wafer. The hybrid bonding process is based on hydrophilic direct bonding of plasma activated Si/Si0₂ surfaces and the simultaneous interconnection of the device metallization layers with Cu TSVs by transient liquid phase (TLP) bonding of ultra-thin AuSn connects. The direct bond enables precise geometry definition between device and cap substrate, whereas the TLP bonding does not require a planarization of the interconnect metallization before bonding. The complete process flow is successfully validated and the fabricated devices characterization evidenced ohmic interconnects without interfacial voids in the TLP bond.

A TSV fabrication approach and the application of the fabricated TSV cap substrate for wafer-level packaging by a hybrid low-temperature bonding process is proposed here. The device wafer capping and electrical interconnection of the metallization with Cu TSVs is achieved by hydrophilic direct bonding of plasma activated Si/Si0₂ surfaces and the simultaneous local transient liquid phase (TLP) bonding of AuSn connects, respectively. In the presented approach the TSVs are integrated in the cap substrate and therewith the fabrication process of the MEMS substrate is not affected in contrast to approaches where the electrical interconnection is performed through the MEMS substrate. Additionally, no back-end processing of the MEMS substrate is necessary, since the electrical interconnection is performed through a fully pre-processed cap wafer. The fabrication process does not require planarization of heterogeneous bond interfaces for a successful hybrid wafer bonding. Further, the low-temperature process is CMOS compatible.

The wafer-level process flow is validated by fabricating and evaluating test structures made out of a two wafer stack. Figure 2.1 shows a schematic 3D picture of the test structure on chip-level; a) the two separately fabricated device and cap substrates and b) the device after hybrid bonding and dicing, respectively. The TSV cap substrate is displayed transparent for a better visibility of the structure. The MEMS device substrate is a silicon wafer featuring dry etched cavities, a metallization layer and the AuSn interconnects. The cap wafer is a conformal thermal oxide passivated Cu TSV substrate. The TSV fabrication is based on bottom-up electrochemical trench refill with a temporary bonded seed substrate, which allows for the fabrication of void-free vertical TSV with a conformal oxide passivation through a thick cap wafer. The limiting factor for the cap wafer thickness is the TSV aspect-ratio. On one hand, the aspect-ratio is limited by the DREE process for etching the via holes, on the other hand, by the surface wettability of the electrolyte for the bottom-up electrochemical via refill.

During the wafer-level hybrid bonding process, ultra-thin AuSn contact pads are forming local electrical interconnects between the metallization layers of the MEMS substrate and the TSV substrate by transient liquid phase bonding (TLP). Simultaneously, the mechanical bond is performed by hydrophilic direct bonding of plasma activated Si and Si02 interfaces. The resulting bonds can reach bond energies above 2J/m², which is close to silicon fracture energy. Further, the direct bond is defining the geometry and allows for precise cavity gap control between device and cap substrate, since there is no intermediate layer and a self-planarization of the AuSn interconnects is taking place during the TLP bonding. The electrical interconnect is formed by reflow and diffusion of the eutectic AuSn metallization. Thus, no planarization of heterogeneous substrates by CMP is required before bonding. Finally, the used tin rich eutectic AuSn as well as the plasma activated direct bonding allow for the process temperature not exceeding 250°C.

Besides the general advantages of TSV substrates for MEMS packaging applications, thick TSV cap wafers are of special interest, since they can substantially increase the package stability against external mechanical load. Additionally, there is no wafer thinning process involved and thick wafers are easier to handle throughout the fabrication process. The presented TSV fabrication process is based on a bottom-up trench refill through a whole 400μπι thick wafer (TSV aspect-ratio of 1). The void-free refill of vertical TSVs through the complete wafer featuring a thick conformal via passivation is achieved by temporary bonding to a seed substrate. During trench refill and planarization of the over-plated TSVs, this temporary bond will also act as surface protection of the side designated for later hybrid bonding to the device substrate.

The starting substrate is a 400μπι thick double side polished (DSP) wafer (Fig. 2.2a). The through silicon holes of the TSV wafer are completely etched through by an ICP DRDE process (Fig. 2.2b). Then a conformal oxide passivation is grown by a thermal wet oxidation of the wafer (Fig. 2.2c). The thermal growth of an oxide enables a conformal passivation of thick TSV substrates with vertical TSV holes. The oxide passivation was grown to a thickness of about 500nm.

Then the wafer is bonded onto a low resistivity silicon seed wafer for the via refill (Fig. 2.2d). The seed wafer additionally features a gold metal layer and the temporary adhesive bonding is performed with the polydimethylglutarimide (PMGI) based lift-off resist LOR 10B from Microchem Corp. (Fig. 2.2d). After bonding, the LOR is structured by an isotropic wet etching process using the through silicon holes as a mask. The via holes are refilled by a bottom-up electrochemical Cu deposition in a two electrode configuration (Fig. 2.2e). The electroplating is carried out by contacting the seed wafer backside and applying a DC current density of 4 A/dm². After the Cu refill, the over-plated vias are planarized by a grinding and polishing step and finally the seed substrate is removed (Fig. 2.2f). The remaining TSV projection height is due to the temporary LOR bonding and features the same height as the adhesive layer thickness. Therefore, the projection height can be controlled by the LOR layer thickness and the implications for the countersinking and TLP bonding with the device wafer are discussed further below.

As concerns the wafer-level packaging, first, the fabrication of the MEMS device substrate is introduced, before describing the actual wafer-level packaging process. One dry etch step, the diffusion barrier and AuSn deposition are the only process steps to be integrated in the complete fabrication process of any arbitrary MEMS substrate to be packaged by hybrid bonding of a TSV cap wafer. The presented MEMS test structure features a device metallization deposited into a dry etched cavity. Thus, the MEMS substrate preparation starts with dry etching of alignment markers and the cavity (Fig. 2.3a). The cavity is etched by a time controlled isotropic process to a depth of 2.2μηι, which can be a critical parameter. For a successful device packaging, the cavity depth and the deposited metallization thickness should be precisely matched with the TSV projection height mentioned above. On one hand, the total thickness of all deposited metal layers has to exceed the cavity depth, in order to allow the contacting between AuSn interconnect pads and TSVs during TLP bonding. But on the other hand, the metals can act as distance keeper and inhibit the direct bonding, since the planarization of the ultra-thin AuSn interconnects is limited for finite heating rates. Therefore the critical vertical dimensions are monitored across the wafer during the complete process and suited parameter windows are discussed further below.

Then the 200nm device metallization is deposited by e-beam evaporation and structured by a lift-off process (Fig. 2.3b). The device metal is composed of an adhesion layer (Cr), the actual metallization (Au) and an additional 60nm diffusion barrier (Cr/Ti) as finish. The diffusion barrier on top of the device metal is necessary in order to prevent the device metal to be consumed by the AuSn during TLP bonding. In a second photolithography, evaporation and lift-off step, the AuSn pads are deposited (Fig. 2.3c). The deposited AuSn layer thickness is adapted according to the actual cavity depth, device metal thickness and TSV projection length. The target overlap or excess thickness of the AuSn interconnects with respect to the gap to be filled during TLP bonding is 200nm. Thus, with a device cavity of 2.2μιτι, a device metallization of 200nm and a TSV projection of 1.7μπι, the required AuSn interconnect layer thickness is 500nm.

Now both, the TSV cap wafer and the MEMS wafer are ready for packaging by the hybrid bonding process. Figure 2.4 shows two photographs of prepared TSV cap and MEMS device wafers.

After the plasma activation for the direct bond, the wafers are aligned and brought into contact (Fig. 2.3d-e). The actual bonding process is performed by heating the stack to 250°C and applying a bond tool pressure of 3 bar. As soon as the interconnect melting temperature is reached, the self -planarization takes place and the direct bond surfaces come into contacted. The direct bond as well as the TLP bonds require an extended annealing at 250°C for four hours in order to allow the complete polymerization of hydroxyl functional groups which form covalent siloxane bonds, as well as to achieve an isothermal solidification and homogenization of the CuSn intermetallic compounds in the TLP bond. At the end the bonded wafer stack is diced and device cross-sections are prepared for the examination presented below. Three critical parameters, which have to be matched for a successful wafer-level packaging are the TSV projection height, the device metal cavity depth where the TSVs are countersunk and the AuSn interconnect thickness. Throughout the process, these critical dimensions are monitored by means of white light interferometer (WLI) measurements across the wafers. Figure 2.5a) shows a WLI measurement of the TSV topography of the cap wafer. As already indicated in the process flow illustrations in Figure 2.2 and 2.3, the TSVs have an excess length on one side of the wafer. This projection is due to the use of the temporary LOR adhesive bonding instead of bonding the seed layer directly onto the TSV substrate. The advantages of using adhesive bonding over direct or metal bonding, is the quicker and easier wafer splitting after TSV electroplating and planarization. Further, the thermal oxide surface flatness can be preserved for a high quality direct bond to the MEMS device wafer. The countersinking of the TSV projection into the TLP interconnect cavity is controllable by adjusting cavity depth and projection height. The projection height can be tailored to the MEMS device cavity by adjusting the LOR layer thickness. The TSV projection uniformity on wafer-level was measured by WLI and the data evaluation evidenced a projection height of 1.68±0.1μιη across the wafer. Further, the defined variation of the device metal cavity etching process is in the range of +50nm across the wafer. These TSV projection height and device cavity variations are compensated by the planarization of the AuSn interconnects during transient liquid phase (TLP) bonding. However, these variations across the wafer require a certain excess height of the AuSn interconnects. The target overlap or excess thickness of the AuSn interconnects with respect to the gap to be filled during TLP bonding is 200nm.

Figure 2.5b) shows a WLI measurement on the device wafer. The two measured profiles A:A and B:B are superposed in Figure 2.5c) in the same way the hybrid bonding will be performed after the wafer alignment. The profiles show the required overlap of TSV projection and AuSn interconnect, as well as illustrate the importance of precise vertical device dimension control. If either the etched cavity is too deep or the deposited device metallization and AuSn pad are not thick enough, the TLP bonding will fail because of an insufficient contact between AuSn pad and Cu TSV. On the other hand, if the cavity is not deep enough, the TSV projection and metallizations will act as distance keeper and inhibit the contacting and direct bonding of the surrounding Si and Si0₂ surfaces. Additionally, the minimal AuSn interconnect thickness is restricted by the achievable heating rate during the bonding process. A too thin AuSn layer will solidify before complete interconnect planarization and wetting of the TSV surface. Thus, creating interfacial voids and inhibiting a close contact of the direct bond interfaces. The 500nm AuSn layer thickness constitutes a lower bound for the applied heating rate of 100K/min.

After hybrid bonding, the wafer stack is diced and device cross-sections are prepared for bond examination. The results of the cross-section analysis are illustrated in Figures 2.6 and 2.7. A microscope picture of a packaged device cross-section is shown in Figure 2.6. The bottom-up TSV refill yields void free Cu vias with a conformal thermal oxide passivation. The Si/Si0₂ direct bond interface is continuous and features no gap at the edges of the device cavities, which demonstrates a sufficient planarization of the TLP bond. Figure 2.7 illustrates the SEM cross-section analysis performed with an energy selective backscattered (ESB) detector. Backscattered electrons (BSE) generate contrast between areas with different chemical compositions, since the backscattered electron intensity depends on the atomic number of the material. Therefore the Si0₂ TSV passivation, the Si substrates, the device metallization, the Cu TSV as well as the TLP bond area with CuSn intermetallic compounds (DvICs) can clearly be distinguished in Figure 2.7a. The direct bond cross-section shows a continuous Si/Si0₂ interface without voids or cracks at the cavity edge. The thermal oxide acting as direct bond interface and TSV passivation features a homogeneous thickness of 560nm. Further, the enlarged view of the TLP bond in Figure 2.7b shows the HvlCs present at the bond interface. The bond is void-free, which indicates a good wetting of the AuSn liquid phase in the early phase of the TLP bond. Interfacial void formation is generally caused by an early TLP bond solidification due to η-phase (Cu₆Sn₅) solid state growth before reaching the interconnect melting point. This is especially critical when bonding thin films with a too low heating rate, since Cu and Sn react spontaneously at room temperature to form Cu₆Sn₅.

EDX measurements confirmed the formed intermetallic compounds to be Cu₃Sn and Cu₆Sn₅. The DVIC layer thickness of the TLP bond interface ranges from 300nm to 800nm, depending on the local formation of Cu₃Sn. The resulting EVIC temperature stability of the interconnects is significantly increased compared to the AuSn properties before TLP bonding. The melting temperature of the formed IMCs is 415°C, even though the annealing temperature does not exceed 250°C. Further, the device matallization can also be identified in the ESB pictures, which is confirming the Cr/Ti diffusion barrier to be effective.

The fabricated devices were characterized by resistance and I-V measurements. All measurements were performed across two TSVs, two interconnects and the device metal, as indicated in the drawn DC probing path in Figure 2.9. The average resistance of 198 measured samples was 99.54+21.55Ω. The resistance variation is due to a non-uniform device metallization thickness over the wafer. The corresponding variation of the device metal sheet resistance was determined to be 0.596+0.13Ω/α. Based on this measured sheet resistance and the conductor line length and width, the computed resistance of the device metal conductor lines between two TSVs yield a value of 101.77+22.95Ω. This is in good agreement with the measured values and confirms the main resistance contribution coming from the device metallization. A wafer-map of the performed resistance measurements is plotted in Figure 2.8. The graph illustrates the systematic variation due to the non-uniform device metal sheet resistance.

Finally, the I-V measurements between two vias evidenced the interconnects to form ohmic contacts. The I-V curves of different samples are plotted in Figure 2.9. Additionally, the measurement sample location on the wafer is indicated by inverted markers in Figure 2.8. The DC characteristic agrees well with the computed values based on geometry and measured sheet resistances.

The presented wafer-level packaging and direct interconnection technology has thus successfully been validated. The TSV substrate fabrication yielded void-free Cu TSVs with a thick conformal passivation of 560nm through a 400μπι wafer. The direct bonding of plasma activated Si/Si0₂ surfaces and TLP bonding of AuSn interconnects and the Cu TSVs were successfully integrated into one low-temperature wafer-level hybrid bonding process for packaging applications. The direct bonding results in strong mechanical bonds, whereas the local TLP bonding of AuSn pads with the TSVs allows for direct electrical interconnection of cap and device substrate. A cross-section analysis of fabricated devices evidenced a working TLP bond self-planarization as well as no interfacial void formation, despite of using an ultra-thin AuSn interconnect metallization. The formed intermetallic compounds (EVICs) of the TLP bond are Cu₆Sn₅ and Cu₃Sn and the consumption of the device metallization could be efficiently prevented by the deposited Cr/Ti diffusion barrier. The carried out electrical device characterization by I-V measurements confirmed the fabrication of ohmic electrical interconnects on wafer-level. The measured average resistance between two TSVs was 99.54+21.55Ω, which is in good agreement with the computed value of 101.77+22.95Ω due to the measured sheet resistance variation of the device metallization across the wafer. The presented approach minimizes the number of process steps for packaging and interconnection of MEMS device substrates. In particular, there is no back-end processing required after the hybrid bonding of the TSV cap wafer. Finally, the presented low- temperature 0-level packaging process with direct interconnection is enabling the integration of different materials for optimized MEMS functionality and performance.

LIST OF REFERENCE SIGNS cap wafer 1 1 cavity, vacuum

through silicon via (TSV) 12 oxide passivation device wafer 13 silicon

generic device structure 14 device metal, conductors of Sn poor eutectic mems

Sn richt eutectic 15 alignment marker mechanical bond (LTDB) 16 via hole

interconnect, transient liquid 17 lift-off resist (LOR) adhesive phase bond (TLPB), location bond

of intermetallic phases 18 seed metal

AuSn eutectic alloy layer 19 metal cavity

contact surface for

mechanical bond

Claims

Low-temperature wafer-level bonding process based on hybrid bonding of a device substrate (3) with a cap substrate (1), which cap substrate (1) features through silicon vias (2),

wherein simultaneous mechanical and electrical bonding of different materials at low temperature is used, preferably without a prior planarization of the heterogeneous substrates before the hybrid bonding process,

wherein the hybrid bonding process is based on low-temperature direct bonding (LTDB) and transient liquid phase bonding (TLPB) for the formation of local ohmic contacts,

wherein during the wafer-level hybrid bonding process, ultra-thin AuSn contact pads (9) are forming local electrical interconnects between metallization layers of the device substrate (3) and the through silicon vias (2) of the cap substrate (1) by transient liquid phase bonding (TLPB),

and wherein during the wafer-level hybrid bonding process simultaneously, a strong mechanical bond is performed in the low-temperature direct bonding (LTDB) by hydrophilic direct bonding of plasma activated Si and Si0₂ interfaces between device substrate (3) and cap substrate (2),

wherein the ultrathin AuSn pads (9) have a composition close to or equal to the tin rich eutectic mixture of these two constituents, preferably with a melting point in the range of 225-235°C, more preferably in the range of 230-233°C.

Process according to claim 1 , wherein the ultrathin AuSn pads (9) have a composition close to or equal to the tin rich eutectic mixture of these two constituents, with a melting point in the range of 225-235°C, preferably in the range of 230-233°C.

Process according to claim 1 or 2, wherein the transient liquid phase bonding (TLPB) for the formation of local ohmic contacts is carried out at a process temperature not exceeding 250°C.

4. Process according to any of the preceding claims, wherein the pads (9) are made by using photolithography, and subsequent evaporation deposition, more preferably by first evaporation depositing a layer of Sn and subsequently, in the corresponding proportion, a layer of Au.

5. Process according to any of the preceding claims, wherein the AuSn pads (9) have an excess thickness in the range of 100-500 nm, preferably in the range of 150- 300 nm, most preferably in the range of 200 nm, with respect to the final interconnect height of the transient liquid phase bonding, wherein more preferably the overall thickness of the pads (9) is less than 1.5 μπι, preferably less than 1 μ, more preferably in the range of 200-700 nm, most preferably in the range of 500 nm.

6. Process according to any of the preceding claims, wherein the AuSn pads (9) are applied to the through silicon vias (2), preferably being based on or consisting of copper, prior to the bonding process.

7. Process according to any of the preceding claims, wherein the AuSn pads (9) are applied to the device substrate (3) prior to the bonding process, wherein the AuSn pads (9) are applied to electrical conductors located on or in the device substrate (3) and/or to electrical contacts of electronic and/or electromechanical and/or electrooptical elements mounted on the and/or in the device substrate (3) and/or to silicon surface areas of the device substrate (3).

8. Process according to any of the preceding claims, wherein the conducting material of the through silicon vias (2) is based on or consisting of Cu, and wherein the process of the transient liquid phase bonding is carried out such that at the contact interface between the AuSn pads (9) and the through silicon vias (2) intermetallic species between copper and tin are formed, preferably in the form of Cu₃Sn and/or Cu₆Sn₅.

9. Process according to any of the preceding claims, wherein the simultaneous mechanical and electrical bonding of different materials at low temperature is carried out for a time span of 30-600 min, preferably in the range of 120-520 min, preferably in the range of 480 min, and/or wherein simultaneous mechanical and electrical bonding of different materials at low temperature is carried out using a bond tool pressure of 1-5 bar, preferably in the range of 2-4 bar, most preferably in the range of 3 bar, wherein further preferably the process is carried out under low pressure atmosphere conditions, most preferably under vacuum conditions, with a residual pressure of preferably not more than O. lmbar, preferably not more than 0.01 or even 0.001 or 0.0001 mbar.

10. Process according to any of the preceding claims, wherein the silicon contact surfaces for the low-temperature direct bonding (LTDB) are prepared for the bonding step by oxygen plasma activation, preferably for a time span in the range of 30-120 seconds with a coil and platen power of 500-1200 W and 10-50 W, respectively, followed by rinsing of the contact surfaces with water, preferably with deionized water, and subsequent essentially complete, preferably fully complete drying of the contact surfaces prior to contacting the contact surfaces for the establishment of the low-temperature direct bond (LTDB).

11. Process according to any of the preceding claims, wherein the device substrate (3) and/or cap substrate (1) are structured such that in the final device they enclose a cavity (1 1) with functional elements of an electronic circuit and/or electronic and/or electromechanical and/or electrooptical element, in particular measurement element, wherein preferably in the final device the cavity (1 1) is sealed and under vacuum.

12. Process according to claim 1 1, wherein the device substrate (3) and/or cap substrate (1 ) is a MEMS device.

13. Process according to any of the preceding claims, wherein prior to the bonding the process does not involve any planarization of the heterogeneous substrates.

14. Device made using a process according to any other preceding claims, wherein preferably the device substrate (3) and/or cap substrate (1) is a MEMS device. Device according to claim 14, wherein the device substrate (3) and/or cap substrate ( 1 ) are structured enclosing a cavity (1 1) with functional elements of an electronic circuit and/or electronic and/or electromechanical and/or electrooptical element, in particular measurement element, wherein preferably the cavity (1 1) is sealed and under vacuum.