CN104516194A - Patterned photoresist layer forming method and wafer-stage chip packaging method - Google Patents
Patterned photoresist layer forming method and wafer-stage chip packaging method Download PDFInfo
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Abstract
A patterned photoresist layer forming method and a wafer-stage chip packaging method are disclosed. The wafer-stage chip packaging method comprises following steps: (1) during manufacturing of a patterned photoresist layer used for forming a re-wire arrangement, coating a substrate with a first photoresist layer in a first viscosity being less than 100cp so that the first photoresist layer is a low-viscosity photoresist layer; (2) coating the first photoresist layer with a second photoresist layer in a second viscosity being higher than the first viscosity; and (3) performing exposure and development to the first photoresist layer and the second photoresist layer. Because that adhesivity of the low-viscosity photoresist layer is weaker than that of the high-viscosity photoresist layer, the patterned photoresist layer, compared with a patterned photoresist layer in the prior art, is easier to remove, so that residue of the patterned photoresist layer in through holes is avoided.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of formation method of graphical photoresist layer, and a kind of wafer stage chip encapsulation method based on silicon through hole technology.
Background technology
Silicon through hole (Through Silicon Via, be called for short TSV) technology is a kind of realization between chip and chip, between wafer and wafer or the interconnection technique of line conduction between wafer and chip.Encapsulate bonding and use the superimposing technique of salient point different from IC in the past, silicon through hole technology can make that chip is maximum in the density that three-dimensional is stacking, physical dimension is minimum.
Existing a kind of wafer stage chip encapsulation method based on silicon through hole technology comprises:
As shown in Figure 1, provide wafer 1, wafer 1 has front S1 and back side S2, and wherein, the front S1 of wafer 1 is formed with circuit structure, forms the larger through hole 2 of depth-to-width ratio at the back side S2 of wafer 1;
As shown in Figure 2, the back side S2 of wafer 1 and the bottom of through hole 2 and sidewall form wiring material layer 3a again, then, form the graphical photoresist layer 4 covering again wiring material layer 3a filling vias 2, graphical photoresist layer 4 has the opening (mark) exposing wiring material layer 3a again, and described opening is positioned at outside through hole 2;
Etch as shown in Figure 3, with graphical photoresist layer 4 for mask, to wiring material layer 3a(more as shown in Figure 2), what form multiple interval connects up 3 again;
As shown in Figure 4, formed and connect up again after 3, utilize wet etching method to remove graphical photoresist layer 4(as shown in Figure 3).
But the graphical photoresist layer 4(in through hole 2 is as shown in Figure 3) be difficult to remove totally, cause in through hole 2 and still have photoresist 4a to remain.
In order to solve this problem, prior art provides a solution, and as shown in Figure 5, it carrys out the graphical photoresist layer 4 in alternate figures 2 with the dry film 5 formed by vacuum laminator, and dry film 5 covers above wiring material layer 3a again, not filling vias 2.For mask, wiring material layer 3a is again etched with dry film 5, after forming wiring again, dry film 5 can be removed neatly.
But the price of dry film is very expensive, and the formation process of dry film is very complicated, therefore, be unfavorable for reducing manufacturing cost, simplified manufacturing technique.
Summary of the invention
The problem to be solved in the present invention is: in the existing wafer stage chip encapsulation method based on silicon through hole technology, and the graphical photoresist layer being positioned at through hole is difficult to remove totally.
Another problem that the present invention will solve is: in the existing wafer stage chip encapsulation method based on silicon through hole technology, and the price being used for being formed the dry film connected up again is very expensive, and the formation process of dry film is very complicated, is unfavorable for reducing manufacturing cost, simplified manufacturing technique.
For solving the problem, the invention provides a kind of wafer stage chip encapsulation method based on silicon through hole technology, comprising:
There is provided substrate, described substrate has front and back;
Through hole is formed at the back side of described substrate;
Form the layer of wiring material again covered on the bottom of backside of substrate and through hole and sidewall;
Form graphical photoresist layer, described in described graphical photoresist layer covers again above wiring material layer, be filled in described through hole, described graphical photoresist layer have expose described in wiring material layer the first opening be positioned at outside described through hole again, the formation method of described graphical photoresist layer comprises: the first photoresist layer applying the first viscosity in substrate, and described first viscosity is less than 100cp; Described first photoresist layer applies the second photoresist layer of second viscosity, and described second viscosity is greater than the first viscosity; Described second photoresist layer and the first photoresist layer are exposed; Develop after exposure, to form graphical photoresist layer;
With described graphical photoresist layer for mask, the described layer of wiring material is again etched, to form connecting up again of multiple interval.
Optionally, described first viscosity is 10 to 50cp.
Optionally, the technological parameter of the first photoresist layer of described coating first viscosity comprises: the rotating speed of described substrate is 1000 to 4000rpm, and the thickness of described first photoresist layer is 0.3 to 5 micron.
Optionally, the technological parameter of described first soft baking comprises: temperature is 80 to 150 DEG C, and the time is 30 to 90s.
Optionally, described second viscosity is 50 to 1000cp.
Optionally, the technological parameter of the second photoresist layer of described coating second viscosity comprises: the rotating speed of described substrate is 500 to 3000rpm, and the thickness of described second photoresist layer is 1 to 100 micron.
Optionally, the technological parameter of described second soft baking comprises: temperature is 80 to 150 DEG C, and the time is 60 to 240s.
Optionally, the depth-to-width ratio of described through hole is more than or equal to 5.
Optionally, described in formation again before wiring material layer, also comprise: form the insulation course covering described backside of substrate and through-hole side wall.
Optionally, also comprise:
After removing described graphical photoresist layer, formed described in covering and connect up again, fill completely described through hole and adjacent two insulation courses in gap between wiring again;
Carry out graphically to described insulation course, the second opening connected up again described in exposing with formation in described insulation course;
Wiring again below described second opening forms soldered ball.
Compared with prior art, technical scheme of the present invention has the following advantages:
Graphical photoresist layer in the technical program is jointly made up of different the first photoresist layer of viscosity, the second photoresist layer, and the first photoresist layer be positioned at below the second photoresist layer is low viscosity photoresist layer.And graphical photoresist layer of the prior art is identical by viscosity and makes for full-bodied photoresist layer, because the adhesion of low viscosity photoresist layer is more weak than the adhesion of high-viscosity photolithographic layer, therefore the adhesion of graphical photoresist layer is more weak than the adhesion of photoresist layer graphical in prior art in the present invention, thus the graphical photoresist layer in the present invention is easier than graphical photoresist layer of the prior art to be removed, and makes not have graphical photoresist layer in through hole and remains.
In addition, the formation process of lower than the cost of dry film, the graphical photoresist layer of graphical photoresist layer is simpler than the formation process of dry film, is thus conducive to reducing manufacturing cost, simplified manufacturing technique.
In addition, present invention also offers a kind of formation method of graphical photoresist layer, comprising:
Substrate applies the first photoresist layer of the first viscosity, and described first viscosity is less than 100cp;
Described first photoresist layer applies the second photoresist layer of second viscosity, and described second viscosity is greater than the first viscosity;
Described second photoresist layer and the first photoresist layer are exposed;
Develop after exposure, to form graphical photoresist layer.
Optionally, coating described first photoresist layer after, apply described second photoresist layer before, also comprise: the first soft baking is carried out to described first photoresist layer.
Optionally, coating described second photoresist layer after, carry out described exposure before, also comprise: the second soft baking is carried out to described second photoresist layer.
Optionally, described first viscosity is 10 to 50cp.
Optionally, described second viscosity is 50 to 1000cp.
Compared with prior art, technical scheme of the present invention has the following advantages:
Graphical photoresist layer in the technical program is jointly made up of different the first photoresist layer of viscosity, the second photoresist layer, and the first photoresist layer be positioned at below the second photoresist layer is low viscosity photoresist layer.And graphical photoresist layer of the prior art is identical by viscosity and makes for full-bodied photoresist layer, because the adhesion of low viscosity photoresist layer is more weak than the adhesion of high-viscosity photolithographic layer, therefore the adhesion of graphical photoresist layer is more weak than the adhesion of photoresist layer graphical in prior art in the present invention, thus the graphical photoresist layer in the present invention is easier than graphical photoresist layer of the prior art to be removed, and makes substrate not to have graphical photoresist layer and remains.
Accompanying drawing explanation
In the existing a kind of wafer stage chip encapsulation method based on silicon through hole technology of Fig. 1 to Fig. 4, encapsulating structure is in the cross-sectional view of each production phase;
Fig. 5 is in the wafer stage chip encapsulation method of existing another kind based on silicon through hole technology, the cross-sectional view of encapsulating structure production phase wherein;
Fig. 6 to Figure 13 be in one embodiment of the present of invention encapsulating structure in the cross-sectional view of each production phase.
Embodiment
Find after deliberation, cause in the existing wafer stage chip encapsulation method based on silicon through hole technology, the graphical photoresist layer being positioned at through hole is difficult to remove clean reason and is:
As shown in Figure 2, graphical photoresist layer 4 utilizes viscosity identical and makes through a photoetching process for full-bodied photoresist, this photoetching process comprises: the once soft baking step after glue application step, gluing, the single exposure step after soft baking, because the viscosity of graphical photoresist layer 4 is high, following impact can be brought: 1) glutinousness of graphical photoresist layer 4 is directly proportional to the viscosity of graphical photoresist layer 4, cause the in uneven thickness of graphical photoresist layer 4, the graphical photoresist layer 4 be particularly filled in bottom through hole 2 is thicker; 2) adhesion of graphical photoresist layer 4 is stronger; 3) graphical photoresist layer 4 is comparatively insoluble in wet etchant, and above-mentioned 3 impacts all can cause the graphical photoresist layer 4 in through hole 2 that depth-to-width ratio is larger to be difficult to remove clean.
In order to solve the problem, the invention provides a kind of wafer stage chip encapsulation method based on silicon through hole technology of improvement, the method is being constructed for being formed in the graphical photoresist layer connected up again, in substrate, first apply the first photoresist layer of the first viscosity, described first viscosity is less than 100cp, the first photoresist layer is made to be low viscosity photoresist layer, the second photoresist layer of second viscosity is applied again on the first photoresist layer, described second viscosity is greater than the first viscosity, and then the first photoresist layer and the second photoresist layer are exposed, development, because the adhesion of low viscosity photoresist layer is more weak than the adhesion of high-viscosity photolithographic layer, therefore, graphical photoresist layer in the present invention is easier than existing graphical photoresist layer to be removed, the graphical photoresist layer being positioned at through hole is made not have residual.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
As shown in Figure 6, provide substrate 100, substrate 100 has front S1 and back side S2.
In the present embodiment, substrate 100 is wafer, wafer is formed with circuit structure (not shown).The face that definition substrate 100 is formed with circuit structure is front S1, and the face deviating from front S1 is back side S2.In a particular embodiment, described wafer is Silicon Wafer.
In the present embodiment, the front S1 of substrate 100 is formed with pad P, and the effect of pad P is electrically connected the circuit structure on wafer and external circuit.
Continue, with reference to shown in Fig. 6, to form through hole 110 at the back side S2 of substrate 100.
In the present embodiment, the formation method of through hole 110 comprises: on the back side S2 of substrate 100, form graphical photoresist layer (not shown), the position of described graphical photoresist layer definition through hole 110; With described graphical photoresist layer for mask, substrate 100 is etched, to form through hole 110 in substrate 100.
In a particular embodiment, the described method etched substrate 100 is Deep Reaction ion etching (Deep Reactive Ion Etch is called for short DRIE).
In the present embodiment, through hole 110 exposed pad P, the depth-to-width ratio of through hole 110 is more than or equal to 5.
Continue, with reference to shown in Fig. 6, to form the insulation course 120 covered on the back side S2 of substrate 100 and the sidewall of through hole 110.
In the present embodiment, the formation method of insulation course 120 comprises: on the back side S2 of substrate 100 and the bottom of through hole 110 and sidewall, form insulation course, and the formation method of this insulation course can be the method such as chemical vapor deposition, thermal oxide; Carry out graphically, to remove the insulation course covered bottom through hole 110 to described insulation course.
As shown in Figure 7, formed and to cover on insulation course 120 and the layer of the wiring material again 130a be filled in through hole 110.
Because wiring material layer 130a covers the bottom of through hole 110 again, therefore, then wiring material layer 130a can be electrically connected with pad P.
In the present embodiment, then the material of wiring material layer 130a is aluminium copper, then the formation method of wiring material layer 130a is plating, physical vapour deposition (PVD) etc.
Formed and to cover on wiring material layer and the graphical photoresist layer be filled in through hole again, graphical photoresist layer has and exposes wiring material layer and the first opening be positioned at outside through hole again.The formation method of graphical photoresist layer comprises:
As shown in Figure 8, substrate 100 applies the first photoresist layer 141 of the first viscosity, and described first viscosity is less than 100cp, makes the first photoresist layer 141 be low viscosity photoresist layer; First soft baking (described soft baking is also referred to as front baking) is carried out to the first photoresist layer 141; After carrying out described first soft baking, the first photoresist layer 141 applies the second photoresist layer 142 of second viscosity, and described second viscosity is greater than the first viscosity; Second soft baking is carried out to the second photoresist layer 142; After carrying out described second soft baking, the first photoresist layer 141 and the second photoresist layer 142 are exposed; After exposure, the first photoresist layer 141 and the second photoresist layer 142 are developed, as shown in Figure 9, cover again on wiring material layer 130a and the graphical photoresist layer 140 be filled in through hole 110 to be formed.
In the present invention, shown in composition graphs 8 and Fig. 9, graphical photoresist layer 140 is jointly made up of the first photoresist layer 141, second photoresist layer 142 that viscosity is different, and the first photoresist layer 141 be positioned at below the second photoresist layer 142 is low viscosity photoresist layer.And graphical photoresist layer of the prior art is identical by viscosity and makes for full-bodied photoresist layer, because the adhesion of low viscosity photoresist layer is more weak than the adhesion of high-viscosity photolithographic layer, therefore the adhesion of graphical photoresist layer 140 is more weak than the adhesion of photoresist layer graphical in prior art in the present invention, thus the graphical photoresist layer 140 in the present invention is easier than graphical photoresist layer of the prior art to be removed, and makes not have graphical photoresist layer 140 in through hole 110 and remains.
In the present embodiment, the first viscosity of the first photoresist layer 141 is 10 to 50cp(centipoise); The technological parameter applying the first photoresist layer 141 comprises: the rotating speed of substrate 100 is 1000 to 4000rpm, and the thickness of the first photoresist layer 141 is 0.3 to 5 micron; The technological parameter of described first soft baking comprises: temperature is 80 to 150 DEG C, and the time is 30 to 90s.
As previously mentioned, in the viscosity of the first photoresist layer 141 and subsequent technique, whether graphical photoresist layer 140 totally can remove tight association.Empirical tests finds, when the viscosity of the first photoresist layer 141 is set to 10 to 50cp, in subsequent technique, the removal ability of graphical photoresist layer 140 is better.
In addition, whether the thickness of the first photoresist layer 141 also totally can remove tight association with graphical photoresist layer 140 in subsequent technique.Empirical tests finds, when the thickness of the first photoresist layer 141 is set to 0.3 to 5 micron, in subsequent technique, the removal ability of graphical photoresist layer 140 is better.
In a particular embodiment, the first viscosity of the first photoresist layer 141 is 20cp, when applying the first photoresist layer 141, the rotating speed of substrate 100 is 4000rpm, and the thickness of the first photoresist layer 141 is 1 micron, when carrying out described first soft baking, temperature is 120 DEG C, and the time is 90s.
In the present embodiment, the second viscosity of the second photoresist layer 142 is 50 to 1000cp(centipoise); The technological parameter applying the second photoresist layer 142 comprises: the rotating speed of substrate 100 is 500 to 3000rpm, and the thickness of the second photoresist layer 142 is 1 to 100 micron; The technological parameter of described second soft baking comprises: temperature is 80 to 150 DEG C, and the time is 60 to 240s.
Empirical tests finds; when the viscosity of the second photoresist layer 142 is set to 50 to 1000cp; the second photoresist layer 142 is not only made to have good adhesion; to be attached on the first photoresist layer 141; and make the thickness of the second photoresist layer 142 be unlikely to too small, make follow-up formation again in wiring process the second photoresist layer 142 layer of wiring material again below graphical photoresist layer can be protected to be etched.
In a particular embodiment, the second viscosity of the second photoresist layer 142 is 500cp, when applying the second photoresist layer 142, the rotating speed of substrate 100 is 1500rpm, and the thickness of the second photoresist layer 142 is 10 microns, when carrying out described second soft baking, temperature is 90 DEG C, and the time is 180s.
In concrete enforcement, the thickness sum of the first photoresist layer 141 and the second photoresist layer 142 is 5 to 50 microns, and make when the subsequent patterning layer 130a of wiring material again, graphical photoresist layer 140 can protect wiring material layer 130a again.
Described soft baking step can bring following advantage: remove the solvent in photoresist; Strengthening the adhesiveness of photoresist so that photoresist can well adhere to when developing, relaxing the stress produced in photoresist in rotary course; Photoresist is prevented to be stained with on equipment; Improve the adhesiveness of photoresist, the homogeneity of photoresist.
In other embodiments, in the step forming graphical photoresist layer, described first soft baking and the second soft baking can not also be carried out.
After described development, the step that post bake cures can also be carried out.The effect that described post bake cures vapors away solvent residual in photoresist, improves the adhesiveness of photoresist.
The material of the first photoresist layer 141 can be identical with the material of the second photoresist layer 142, and in this case, in the first photoresist layer 141, second photoresist layer 142, the concentration of solvent is not identical.The material of the first photoresist layer 141 also can not be identical with the material of the second photoresist layer 142.
Etch as shown in Figure 10, with graphical photoresist layer 140 for mask, to wiring material layer 130a(more as shown in Figure 9), connect up 130 again with what form multiple interval.
As shown in figure 11, graphical photoresist layer 140(is removed as shown in Figure 10).
In the present embodiment, wet etching method is utilized to remove graphical photoresist layer 140.
As shown in figure 12, formed to cover and to connect up again above 130 and to fill the insulation course 150 in full through hole 110 and adjacent two gaps between 130 of connecting up again.
In the present embodiment, the material of insulation course 150 is the dielectric materials such as silicon dioxide.
Continue, with reference to shown in Figure 12, to carry out graphically to insulation course 150, with formation in insulation course 150 expose connect up again 130 the second opening (mark).
As shown in figure 13, connecting up again on 130 below described second opening forms bump bottom metal layer (Under Bump Metallization is called for short UBM) 160, and bump bottom metal layer 160 130 to contact with connecting up again.
Continue, with reference to shown in Figure 13, bump bottom metal layer 160 to form soldered ball 170.
In other embodiments, soldered ball 170 and connect up between 130 again and also can not have bump bottom metal layer 160, in this case, soldered ball 170 130 directly to contact with connecting up again.
In semiconductor processing, usually there is so a kind of processing procedure: substrate surface is coated with material layer to be patterned, carry out graphically to treat patterned material layer, first on material layer to be patterned, form graphical photoresist layer, then treat patterned material layer with this graphical photoresist layer for mask to etch, after material pattern to be patterned, remove graphical photoresist layer.
But, in the graphical photoresist layer step of removal, be difficult to graphical photoresist layer to remove totally, especially when substrate surface is provided with opening and graphical photoresist layer is filled in opening, often have photoresist in opening and remain.
In order to solve this problem, the invention provides a kind of formation method of graphical photoresist layer, the method comprises:
Substrate applies the first photoresist layer of the first viscosity, and described first viscosity is less than 100cp, makes the first photoresist layer be low viscosity photoresist layer;
Described first photoresist layer applies the second photoresist layer of second viscosity, and described second viscosity is greater than the first viscosity;
Described second photoresist layer and the first photoresist layer are exposed;
Develop after exposure, to form graphical photoresist layer.
Described graphical photoresist layer is jointly made up of the first different photoresist layer of viscosity and the second photoresist layer, and the first photoresist layer be positioned at below the second photoresist layer is low viscosity photoresist layer.And graphical photoresist layer of the prior art is identical by viscosity and makes for full-bodied photoresist layer, because the adhesion of low viscosity photoresist layer is more weak than the adhesion of high-viscosity photolithographic layer, therefore the adhesion of graphical photoresist layer is more weak than the adhesion of photoresist layer graphical in prior art in the present invention, thus the graphical photoresist layer in the present invention is easier than graphical photoresist layer of the prior art to be removed, and does not have photoresist.
In the present embodiment, coating described first photoresist layer after, apply described second photoresist layer before, also comprise: the first soft baking is carried out to described first photoresist layer.
In the present embodiment, coating described second photoresist layer after, carry out described exposure before, also comprise: the second soft baking is carried out to described second photoresist layer.
In a particular embodiment, described first viscosity is 10 to 50cp.
In a particular embodiment, described second viscosity is 50 to 1000cp.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (15)
1. a formation method for graphical photoresist layer, is characterized in that, comprising:
Layer levied by the first photoresist that substrate applies the first viscosity, and described first viscosity is less than 100cp;
What described first photoresist layer applied second viscosity levies the second photoresist layer, and described second viscosity is greater than the first viscosity;
Described second photoresist layer and the first photoresist layer are exposed;
Develop after exposure, to form graphical photoresist layer.
2. formation method according to claim 1, is characterized in that, coating described first photoresist layer after, apply described second photoresist layer before, also comprise: the first soft baking is carried out to described first photoresist layer.
3. formation method according to claim 1, is characterized in that, coating described second photoresist layer after, carry out described exposure before, also comprise: the second soft baking is carried out to described second photoresist layer.
4. formation method according to claim 1, is characterized in that, described first viscosity is 10 to 50cp.
5. formation method according to claim 1, is characterized in that, described second viscosity is 50 to 1000cp.
6., based on a wafer stage chip encapsulation Fang Zhengfa for silicon through hole technology, it is characterized in that, comprising:
There is provided substrate, described substrate has front and back;
Through hole is formed at the back side of described substrate;
Form the layer of wiring material again covered on the bottom of backside of substrate and through hole and sidewall;
The method described in claim 1 is utilized to form graphical photoresist layer, described in described graphical photoresist layer covers again above wiring material layer, be filled in described through hole, described graphical photoresist layer have expose described in wiring material layer the first opening be positioned at outside described through hole again;
With described graphical photoresist layer for mask, the described layer of wiring material is again etched, to form connecting up again of multiple interval.
7. method for packing according to claim 6, is characterized in that, described first viscosity is 10 to 50cp.
8. method for packing according to claim 7, is characterized in that, the technological parameter of the first photoresist layer of described coating first viscosity comprises: the rotating speed of described substrate is 1000 to 4000rpm, and the thickness of described first photoresist layer is 0.3 to 5 micron.
9. method for packing according to claim 7, is characterized in that, the technological parameter of described first soft baking comprises: temperature is 80 to 150 DEG C, and the time is 30 to 90s.
10. method for packing according to claim 6, is characterized in that, described second viscosity is 50 to 1000cp.
11. method for packing according to claim 10, is characterized in that, the technological parameter of the second photoresist layer of described coating second viscosity comprises: the rotating speed of described substrate is 500 to 3000rpm, and the thickness of described second photoresist layer is 1 to 100 micron.
12. method for packing according to claim 10, is characterized in that, the technological parameter of described second soft baking comprises: temperature is 80 to 150 DEG C, and the time is 60 to 240s.
13. method for packing according to claim 6, is characterized in that, the depth-to-width ratio of described through hole is more than or equal to 5.
14. method for packing according to claim 6, is characterized in that, described in formation again before wiring material layer, also comprise: form the insulation course covering described backside of substrate and through-hole side wall.
15. method for packing according to claim 6, is characterized in that, also comprise:
After removing described graphical photoresist layer, formed described in covering and connect up again, fill completely described through hole and adjacent two insulation courses in gap between wiring again;
Carry out graphically to described insulation course, the second opening connected up again described in exposing with formation in described insulation course;
Wiring again below described second opening forms soldered ball.
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| CN111710605A (en) * | 2020-06-19 | 2020-09-25 | 扬州国宇电子有限公司 | Method for stripping metal on semiconductor table top |
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