CN103762202B - Chip packaging method and structure - Google Patents
Chip packaging method and structure Download PDFInfo
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- CN103762202B CN103762202B CN201410042062.9A CN201410042062A CN103762202B CN 103762202 B CN103762202 B CN 103762202B CN 201410042062 A CN201410042062 A CN 201410042062A CN 103762202 B CN103762202 B CN 103762202B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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Abstract
The invention provides a chip packaging method and structure. The chip packaging method includes the steps that a base is provided, wherein the base comprises a substrate and a client layer which is arranged on the surface of the substrate, the surface of the client layer is the first surface of the base, the surface, opposite to the first surface, of the substrate is the second surface, and a plurality of welding pads are formed in the client layer; the second surface of the base is etched to form a groove, wherein the groove is provided with a first sub groove and second sub grooves, the second sub grooves are located in the two sides of the first sub groove and protruded, the first sub groove is communicated with the second sub grooves, the second sub grooves are exposed out of part of the surfaces of the welding pads, and the second sub grooves are only exposed out of one sides of the welding pads; insulating layers are formed in the inner wall of the groove and the second surface of the base; through holes located in the welding pads are formed and penetrate through the insulating layers and the welding pads; a wiring metal layer is formed; a solder mask layer is formed, and an opening is formed in the solder mask layer and exposed out of part of the surface of the wiring metal layer; a welded ball is formed in the opening. According to the method, reliability of the packing structure can be improved.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of chip packaging method and encapsulating structure.
Background technology
Wafer stage chip is encapsulated（Wafer Level Chip Size Packaging, WLCSP）Technology is to full wafer wafer
It is packaged after test and cuts the technology for obtaining single finished product chip again, the chip size after encapsulation is consistent with nude film.Wafer scale
Chip size packages technology changes conventional package such as ceramic leadless chip carrier（Ceramic Leadless Chip
Carrier）, organic leadless chip carrier（Organic Leadless Chip Carrier）With digital camera modular
Pattern, has complied with market increasingly light to microelectronic product, little, short, thinning and low priceization and has required.Jing crystal wafer chip dimension encapsulations
Chip size after technology encapsulation has reached and has been highly miniaturized, and chip cost is with the reduction of chip size and the increasing of wafer size
Significantly reduce greatly.Crystal wafer chip dimension encapsulation technology can be by IC designs, wafer manufacture, packaging and testing, substrate manufacture
The technology for integrating, is the focus in current encapsulation field and the trend of future development.
Existing wafer-level chip size package method is mainly included the following steps that：
First, semiconductor crystal wafer and substrate are pressed, the client layer refers to the material layer for being formed with device, crystal column surface
Device portions protected by substrate, reduce extraneous pollution and infringement；To wafer relative to the back side of substrate carry out it is thinning after, and
Using photoetching technique and plasma dry etch process, wafer is performed etching, form groove, and expose some welderings
Pad.
Then, insulating barrier is formed in groove surfaces, and radium-shine punching is carried out to weld pad.
Finally, the deposited metal layer on wafer rear, and the metal level is patterned, metallic circuit is formed, it is complete
Into wiring；The solder mask of filling groove is formed on metallic circuit, and opening is formed in weld, formed in the opening
Soldered ball；Wafer is opened along Cutting Road heartcut again, obtains chip；Chip is electrically connected on pcb board by stannum ball, letter is realized
Number input and export.
More wafer-level chip size package methods may be referred to the Chinese patent of Publication No. CN101419952A.
The reliability of the encapsulating structure that existing chip packaging method is formed need further raising.
The content of the invention
The problem that the present invention is solved is to provide a kind of chip packaging method and encapsulating structure, improves the reliability of encapsulating structure
Property.
To solve the above problems, the present invention provides a kind of chip packaging method, including：Substrate is provided, the substrate includes
First surface and the second surface relative with the first surface, the first surface has client layer and in client layer
Weld pad；The second surface of the substrate is etched, groove is formed, the groove has the first sub- groove and positioned at the first sub- groove
Second sub- groove of the protrusion of both sides, the first sub- groove and the second sub- groove connection, the second sub- groove exposes weldering
The part surface of pad, and the second sub- groove at most exposes a line of the weld pad；On the groove inner wall surface
And form insulating barrier on the second surface of substrate；Through hole is formed, the through hole is located in weld pad, and penetrates insulating barrier and weld pad；
Interconnection metal layer is formed in the groove, through-hole surfaces；Solder mask is formed in the wiring metal layer surface, in the solder mask
With opening, the opening exposes the surface of part interconnection metal layer；Formed in the opening and be located at interconnection metal layer table
The soldered ball in face.
Optionally, the described first sub- groove is located at the client's layer surface between adjacent welding-pad.
Optionally, the described second sub- groove includes Part I and Part II, and Part I is located at weld pad surface, second
Part is located at client's layer surface, connects the Part I and the first groove.
Optionally, the through hole is formed using laser boring technique.
Optionally, also include：Substrate is provided, after the first surface of the substrate and substrate are pressed, is re-formed described recessed
Groove.
Optionally, the material of the insulating barrier includes macromolecule organic insulation polymer or inorganic insulation dielectric material.
Optionally, the insulating barrier is formed using spraying coating process, spin coating proceeding or chemical vapor deposition method.
To solve the above problems, technical scheme also provides the encapsulating structure that a kind of employing said method is formed,
Including：Substrate, the substrate includes first surface and the second surface relative with the first surface, and the first surface has
Client layer and the weld pad in client layer；Groove in the substrate second surface, the groove is sub with first
Second sub- groove of groove and the protrusion positioned at the first sub- groove both sides, the first sub- groove and the second sub- groove connection, institute
The part surface that the second sub- groove exposes weld pad is stated, and the second sub- groove at most exposes of the weld pad
Side；Positioned at the groove inner wall surface and the insulating barrier of the second surface of substrate；Through hole in weld pad, the through hole is penetrated
Insulating barrier and weld pad；Positioned at the groove, the interconnection metal layer of through-hole surfaces；Positioned at the welding resistance of the wiring metal layer surface
There is opening, the opening exposes the surface of part interconnection metal layer in layer, the solder mask；Position in the opening
In the soldered ball of wiring metal layer surface.
Optionally, the described first sub- groove is located at the client's layer surface between adjacent welding-pad.
Optionally, the described second sub- groove includes Part I and Part II, and Part I is located at weld pad surface, second
Part is located at client's layer surface, connects the Part I and the first groove.
Optionally, also include：Substrate, first surface and the substrate of the substrate are pressed.
Optionally, the material of the insulating barrier includes macromolecule organic insulation polymer or inorganic insulation dielectric material.
Compared with prior art, technical scheme has advantages below：
In technical scheme, the second surface of substrate is etched, form groove, the groove has the first sub- groove
And the second sub- groove of the protrusion positioned at the first sub- groove both sides, the first sub- groove and the connection of the second sub- groove, described the
Two sub- grooves expose the part surface of weld pad, and the second sub- groove only exposes a line of the weld pad.Due to
The second sub- groove only exposes a line of the weld pad, so its excess-three bar side of the weld pad is by the lining above weld pad
Bottom covers, the substrate can butt welding pave effective supporting role, offset the stress that weld pad is subject to, it is to avoid due to weldering
Pad is caused weld pad to disconnect with the junction of substrate by excessive stresses, such that it is able to improve the reliability of the encapsulating structure of formation
Property, and the trustworthiness of encapsulation chip.
Description of the drawings
Fig. 1 to Figure 10 is the schematic diagram of the forming process of the encapsulating structure of embodiments of the invention.
Specific embodiment
As described in the background art, the encapsulating structure reliability that existing chip packaging method is formed is relatively low.
On the one hand, it is because the thickness of the solder mask of filling in groove is larger, in the heat cure for forming the solder mask
During, because solder mask is different from the thermal coefficient of expansion of wafer, larger stress can be produced, and client layer is passed to,
Larger stress is produced in client layer；And during soldered ball is formed using reflow soldering process, due to solder mask and wafer
Thermal coefficient of expansion it is different, the high temperature in reflow process also can produce stress in client layer.
On the other hand, after wafer level packaging is completed, need to enter the soldered ball on chip and pcb board in the way of Reflow Soldering
Row is electrically connected, then filler.Because the material of the glue material adopted when the solder mask is from filler is different, thermal cycle test is being carried out
During, can produce stress and pass to client layer due to thermal mismatching effect between the two, because client layer is one whole
Body, it is impossible to which Stress Release is gone out, and because the silicon chip of the bottom portion of groove and the junction of weld pad are more fragile, in stress
Under effect, weld pad can disconnect with silicon junction, make the reliability of encapsulating structure and reduce.
In embodiments of the invention, during groove is formed, the bottom portion of groove is set only to expose the weld pad of part
Surface so that the substrate of recess sidewall can butt welding pave enough protections and supporting role, it is to avoid under stress weld
Pad disconnects with substrate junction, such that it is able to improve the reliability of encapsulating structure.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Refer to Fig. 1, there is provided substrate, the substrate includes：Substrate 100 and the client layer 110 positioned at the surface of substrate 100,
The surface of the client layer 110 for substrate first surface 11, the surface of the substrate 100 relative with the first surface 11 is the
Two surfaces 12, some weld pads 120 are formed with 110 in the client layer.
The second surface 12 of the substrate is that, without device side, and first surface 11 is to there is device side.In the client layer 110
Semiconductor device 10 is formed with, the quantity of the weld pad 120 is multiple, the discrete periphery for being arranged in semiconductor device 10.This reality
In applying example, the weld pad 120 is shaped as rectangle, and in other embodiments of the invention the weld pad 120 can also be other
Suitable shape, the input/output terminal that the weld pad 120 is connected as the internal circuit of semiconductor device 10 with external circuit.
The semiconductor device 10 can be image sensor, photodiode or MEMS etc..
The generalized section of two continuous chips is shown in Fig. 1, dotted line both sides are respectively two chips.It is subsequently formed
After encapsulating structure, at dotted line position, cut, obtain encapsulating chip, the dotted line is line of cut.
Refer to Fig. 2, there is provided substrate 200, the first surface 11 of the substrate 100 and substrate 200 are pressed.
The size of the substrate 200 is equivalently-sized with substrate 100, and the substrate 200 includes base plate 201 and cavity wall
202。
Specifically, the base plate 201 can be glass, and the cavity wall 202 is by the surface spin coating photoetching of base plate 201
Glue, and expose, develop after formed.Cavity wall 202 on substrate 200 forms adhesive layer away from the one side of base plate 201（In figure not
Illustrate）, the adhesive layer can be polymeric adhesion material, such as silica gel, epoxy resin, benzocyclobutene etc..The bonding
Layer can both realize bonding effect, and insulation and sealing function can be played again.
The substrate 200 is pressed with the first surface 11 of substrate 100, the cavity wall 202 is surrounded with client layer 110
Cavity with wafer 100 formed semiconductor device 10 it is corresponding, weld pad 120 be located at the surface of cavity wall 202, the quasiconductor
Device 10 is located in cavity.
Follow-up Fig. 3 to Figure 10 is the partial schematic diagram of the region I in Fig. 2.
Fig. 3 and Fig. 4 is refer to, the second surface 12 of substrate is etched, groove 101 is formed, the groove 101 is sub with first
Second sub- groove 121 of groove 111 and the protrusion positioned at the both sides of the first sub- groove 111, the first sub- groove 111 and second is sub
Groove 121 is connected, and the second sub- groove 121 exposes the part surface of weld pad 120, and the second sub- groove 121 is only
Expose a line of the weld pad 120.Fig. 3 is generalized sections of the Fig. 4 along the secant in AA ' directions.
Before the groove 101 is formed, the second surface 12 of the substrate can also be carried out thinning.Specifically, may be used
To carry out being thinned to desired thickness to the second surface 12 of the substrate using chemical mechanical milling tech.
The mask layer with opening is formed on the second surface 12；Along the opening etched substrate 100, groove is formed
101.The mask layer can be photoresist layer, can form the groove 101 with using plasma etching technics.The groove
101 sidewall slope angle and bottom width can be controlled by the parameter of plasma etch process.
The groove 101 can be between adjacent chips line of cut 20（Refer to Fig. 4）Arrange, and with regard to the cutting
Line 20 is symmetrical, used as the Cutting Road for subsequently carrying out mechanical cutting processes.Some weld pads 120 of the bottom of the groove 101 are right respectively
Answer different semiconductor chips.
Specifically, in the present embodiment, the groove 101 includes the first sub- groove 111 and positioned at the described first sub- groove 111
Second sub- groove 121 of both sides.The first sub- groove 111 is connected with the second sub- groove 121, and bearing of trend mutually hangs down
Directly, it is in Os Sus domestica hole shape that the groove 101 overlooks figure.
In the present embodiment, subsequently substrate is cut along the described first sub- groove 111, the first sub- groove 111
The surface of client layer 110 between adjacent welding-pad 120.And the second sub- groove 111 is located on weld pad 120, for exposing weld pad
120 part surface.
The second sub- groove 121 includes Part I and Part II, and Part I is located at the surface of weld pad 120, second
Part is located at the surface of client layer 110, connects the Part I and the first groove 111.The second sub- groove 121 only exposes
A line of the weld pad 120 at the position of the first sub- groove 111, makes other three sides and edge of the weld pad 120
Part of solder pads 120 is covered by the substrate 100 of top, so as to the substrate 100 can provide support to weld pad 120.
Compared with prior art, embodiments of the invention can improve the reliability of weld pad 120 and the junction of substrate 100,
It is unlikely to break substrate 100 with the junction of weld pad 120 in the case where the stress of the processing procedure of heat treatment generation is subsequently related to, can be with
Improve the reliability of encapsulating structure.
In the present embodiment, the second sub- groove 121 only exposes the weld pad 120 near the side of the first sub- groove 111
A line, remaining side is covered by the substrate 100 above weld pad.The side wall of the second sub- groove 121 and weld pad 120 not by
Vertical dimension between the side for exposing is relatively low, and the area for exposing weld pad 120 is larger, follow-up on weld pad 120 to reduce
Form the alignment difficulty of through hole.
Weld pad 120 pushes down more part by the substrate 100 above it, makes substrate 100 provide weld pad 120 and effectively props up
Support, also, the substrate 100 covers three sides of weld pad 120 so that the position distribution scope that weld pad 120 is pushed down by substrate 100
Relatively wide, the negative function of the stress to being applied on weld pad 120 is stronger.
Fig. 5 is refer to, insulating barrier 102 is formed on the second surface 12 of the inner wall surface of the groove 101 and substrate.
The material of the insulating barrier 102 can be the macromolecule organic insulation polymeric materials such as photoresist, silica gel, described exhausted
The material of edge layer 102 can also be the inorganic insulation dielectric material such as silicon nitride, silicon oxide, can be using spraying coating process, chemical gas
Phase depositing operation, spin coating proceeding etc. form the insulating barrier 102.The thickness of the insulating barrier 102 can be 2um～20um.
The insulating barrier 102 is used as the sealing coat between the interconnection metal layer and substrate 100 being subsequently formed.
Fig. 6 and Fig. 7 is refer to, through hole 103 is formed, the through hole 103 is located in weld pad 120, and penetrates the He of insulating barrier 102
Weld pad 120.Fig. 7 is to form the schematic top plan view after the through hole 103（Wherein, insulating barrier is not shown）.Fig. 6 is along Fig. 7
The generalized section in secant AA ' directions.
The through hole 103 is formed using laser boring technique, the cross section of the through hole 103 can be circular or oval
Deng, and the through hole 103 is fully located in the weld pad 120, penetrates the insulating barrier 102 and weld pad on the surface of weld pad 120
120.After forming the through hole 103, the side wall of the through hole 103 exposes weld pad 120.
Fig. 8 is refer to, on the groove 101, the surface of through hole 103 interconnection metal layer 104 is formed.
Forming the method for the interconnection metal layer 104 includes：On the groove 101, through hole 103 and the surface of insulating barrier 102
Form metal level；The graphical metal level, forms interconnection metal layer 104.
The thickness of the metal level is unsuitable excessive, it is to avoid during metal level is formed, the open top of through hole 103 is blocked up
Firmly, hole is formed in second groove 103, the contact quality of metal level and weld pad 120 is affected.
The metal level can be formed using sputtering technology, make metal level have higher uniformity, the metal level
Material can be the metal materials such as copper, tungsten, aluminum, titanium, alumel, gold.
After metallic layer graphic, interconnection metal layer 104 is formed, the interconnection metal layer 104 includes being located at substrate the
Ball lower metal layer part on two surfaces 12 and the external lead portion being connected with weld pad 120 in groove 101；The outer lead
Part is electrically connected ball lower metal layer part with weld pad 120.
The process of patterned metal layer is that metal level is divided into outer lead and the ball lower metal layer portion of a plurality of mutual disconnection
Point.
Specifically, can be using photoetching process and wet-etching technology, the graphical metal level forms interconnection metal layer
104。
Fig. 9 is refer to, is formed to have in solder mask 106, the solder mask 106 on the surface of the interconnection metal layer 104 and is opened
Mouth 107, the opening 107 exposes the surface of part interconnection metal layer 104.
Solder mask 106 described in the solder mask 106 covers interconnection metal layer, and the solder mask 106 can be adopted and insulation
102 identical material of layer, can be the macromolecule organic insulation polymeric materials such as photoresist, silica gel, can be using spin coating or spray
Apply technique and form the solder mask 106.
The position of the opening 107 in the solder mask 106 is the position of the soldered ball for being subsequently formed connecting wiring metal level.
The method for forming the solder mask 106 can be the surface of interconnection metal layer 104 formed soldermask material after, it is right
The soldermask material is patterned, and opening 107 is formed at the position for subsequently needing to form soldered ball.
The solder mask 106 can protect interconnection metal layer 104 not affected by subsequent technique, and can reduce and avoid
Metal exposure beyond pad, during soldered ball is formed short circuit problem is caused.
Figure 10 is refer to, in the opening 107（Refer to Fig. 9）The interior soldered ball formed positioned at the surface of interconnection metal layer 104
108。
The soldered ball 108 is electrically connected by interconnection metal layer 104 with weld pad 120.
Specifically, the soldered ball 108 can be formed using screen printing technique and technique of backflow.
Subsequently by cutting technique substrate can be cut along the described first sub- groove 111, obtained BGA
Chip-scale encapsulation chip, and the chip is electrically connected by way of soldered ball and pcb board are with Reflow Soldering, then
Filler, realizes the input and output of signal, and carries out thermal cycle test.
Due to the glue material used during filler it is different from the material of the solder mask, in the process for carrying out thermal cycle test
In, because both thermal coefficient of expansions are different, thermal and mechanical stress can be produced.The thermal and mechanical stress is delivered to weldering by solder mask
On pad and client layer, because client layer is an entirety, stress cannot discharge in time so that weld pad can be answered masterpiece by larger
With.
In prior art, weld pad only has fraction and is covered by the substrate above it, and weld pad is in root of notch and substrate 100
Junction is more fragile, and under the stress produced in thermal cycle test, the substrate 100 holds with the junction of weld pad 120
Easily disconnect, cause the reliability for encapsulating chip to reduce.
And in embodiments of the invention, the groove of Os Sus domestica hole shape being formed in the second surface of substrate, the groove has
First sub- groove and the second sub- groove, the second sub- groove exposes the part surface of weld pad, and only exposes the weldering
The a line of pad, its excess-three bar side for making the weld pad is covered by the substrate above weld pad, and the substrate can be paved with butt welding
Effectively supporting role, offsets the stress produced to weld pad in subsequent technique, it is to avoid weld pad and lining in thermal cycle test
The problem that the junction at bottom disconnects, improves the reliability of encapsulating structure and the reliability of encapsulation chip.
To solve the above problems, the present invention also provides the encapsulating structure that a kind of said method is formed.
Figure 10 is refer to, is the generalized section of the encapsulating structure.
The encapsulating structure includes：Substrate, the substrate includes：Substrate 100 and the client layer positioned at the surface of substrate 100
110, the surface of the client layer 110 for substrate first surface 11, the surface of the substrate 100 relative with the first surface 11
For second surface 12,110 in the client layer in be formed with some weld pads 120；Groove in the second surface 12
101, the groove 101 has the second sub- groove 121 of the first sub- groove 111 and the protrusion positioned at the both sides of the first sub- groove 111,
The first sub- groove 111 is connected with the second sub- groove 121, and the second sub- groove 121 exposes the part table of weld pad 120
Face, and the second sub- groove 121 only exposes a line of the weld pad 120；Positioned at the inner wall surface of the groove 101 and
The insulating barrier 102 of the second surface 12 of substrate 100；Through hole in weld pad 120, the through hole simultaneously penetrates the He of insulating barrier 102
Weld pad 120；Positioned at the interconnection metal layer 104 of the groove 101, through-hole surfaces；Positioned at the resistance on the surface of the interconnection metal layer 104
There is opening, the opening exposes the surface of part interconnection metal layer 104 in layer 106, the solder mask 106；Positioned at institute
State the soldered ball 108 positioned at the surface of interconnection metal layer 104 in opening.
The encapsulating structure also includes：Substrate 200, first surface 11 and the substrate 200 of the substrate 100 are pressed.It is described
The size of substrate 200 is equivalently-sized with substrate 100, and the substrate includes base plate 201 and cavity wall 202.
Refer to Fig. 7, Fig. 7 is bowing for the encapsulating structure further groove 101, through hole 103 and weld pad 120 and substrate 100
Depending on schematic diagram.
In the present embodiment, the first sub- groove 111 is located at the client's layer surface between adjacent welding-pad 120.
The second sub- groove 121 exposes a line of weld pad 120.
Vertical dimension between the side wall of the second sub- groove 121 and the side not being exposed of weld pad 120 is less, makes
The area that weld pad 120 exposes is larger, through hole 103 is fully located in weld pad 120.
In the encapsulating structure, weld pad 120 covers three sides by the substrate above it, improves substrate to weld pad 120
Supporting role, and more weld pad surfaces are exposed, can effectively offset the thermal and mechanical stress pair produced in thermal cycle test
The effect of weld pad, it is to avoid weld pad disconnects with the junction of substrate, so as to improve the reliability of encapsulating structure, improves encapsulation chip
Reliability.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, without departing from this
In the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (12)
1. a kind of chip packaging method, it is characterised in that include：
Substrate is provided, the substrate includes：Substrate and the client layer positioned at one surface of substrate, another surface of the client layer
For the first surface of substrate, the substrate another surface relative with first surface for substrate second surface, the client layer
To be internally formed the material layer of some weld pads；
The second surface of the substrate is etched, groove is formed, the groove has the first sub- groove and positioned at the first sub- groove two
Second sub- groove of the protrusion of side, the first sub- groove and the second sub- groove connection, the second sub- groove exposes weld pad
Part surface, and the second sub- groove only exposes a line of the weld pad；
Insulating barrier is formed on the second surface of the groove inner wall surface and substrate；
Through hole is formed, the through hole is located in weld pad, and penetrates insulating barrier and weld pad；
Interconnection metal layer is formed in the groove, through-hole surfaces；
Formed in the wiring metal layer surface and have in solder mask, the solder mask opening, the opening exposes part cloth
The surface of line metal level；
The soldered ball positioned at wiring metal layer surface is formed in the opening.
2. chip packaging method according to claim 1, it is characterised in that the first sub- groove be located at adjacent welding-pad it
Between client's layer surface.
3. chip packaging method according to claim 1, it is characterised in that the second sub- groove include Part I and
Part II, Part I is located at weld pad surface, and Part II is located at client's layer surface, connects the Part I and first recessed
Groove.
4. chip packaging method according to claim 1, it is characterised in that form described logical using laser boring technique
Hole.
5. chip packaging method according to claim 1, it is characterised in that also include：Substrate is provided, by the substrate
After first surface is pressed with substrate, the groove is re-formed.
6. chip packaging method according to claim 1, it is characterised in that the material of the insulating barrier has including macromolecule
Machine insulating polymer or inorganic insulation dielectric material.
7. chip packaging method according to claim 1, it is characterised in that using spraying coating process, spin coating proceeding or chemistry
Gas-phase deposition forms the insulating barrier.
8. a kind of encapsulating structure, it is characterised in that include：
Substrate, the substrate includes：Substrate and the client layer positioned at one surface of substrate, another surface of the client layer is base
The first surface at bottom, the substrate another surface relative with first surface is the second surface of substrate, and the client layer is interior
Portion is formed with the material layer of some weld pads；
Positioned at the groove of the substrate second surface, the groove has the first sub- groove and positioned at the convex of the first sub- groove both sides
The the second sub- groove for going out, the first sub- groove and the second sub- groove connection, the second sub- groove exposes the part of weld pad
Surface, and the second sub- groove only exposes a line of the weld pad；
Positioned at the groove inner wall surface and the insulating barrier of the second surface of substrate；
Through hole in weld pad, the through hole penetrates insulating barrier and weld pad；
Positioned at the groove, the interconnection metal layer of through-hole surfaces；
There is opening in the solder mask of the wiring metal layer surface, the solder mask, the opening exposes part cloth
The surface of line metal level；
The soldered ball positioned at wiring metal layer surface in the opening.
9. encapsulating structure according to claim 8, it is characterised in that the first sub- groove is located between adjacent welding-pad
Client's layer surface.
10. encapsulating structure according to claim 8, it is characterised in that the second sub- groove includes Part I and the
Two parts, Part I is located at weld pad surface, and Part II is located at client's layer surface, connects the Part I and first recessed
Groove.
11. encapsulating structures according to claim 8, it is characterised in that also include：Substrate, the first surface of the substrate
With substrate pressing.
12. encapsulating structures according to claim 8, it is characterised in that the material of the insulating barrier includes organic polymer
Polymer or inorganic insulation dielectric material.
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| CN201410042062.9A CN103762202B (en) | 2014-01-28 | 2014-01-28 | Chip packaging method and structure |
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| CN201410042062.9A CN103762202B (en) | 2014-01-28 | 2014-01-28 | Chip packaging method and structure |
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| CN103762202A CN103762202A (en) | 2014-04-30 |
| CN103762202B true CN103762202B (en) | 2017-04-19 |
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| US9117715B2 (en) * | 2012-07-18 | 2015-08-25 | Hong Kong Applied Science and Technology Research Institute Company Limited | Wafer-level device packaging |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN203746834U (en) * | 2014-01-28 | 2014-07-30 | 苏州晶方半导体科技股份有限公司 | Packaging structure |
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