TWI559473B - Semiconductor border protection sealant - Google Patents

Semiconductor border protection sealant Download PDF

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Publication number
TWI559473B
TWI559473B TW104113157A TW104113157A TWI559473B TW I559473 B TWI559473 B TW I559473B TW 104113157 A TW104113157 A TW 104113157A TW 104113157 A TW104113157 A TW 104113157A TW I559473 B TWI559473 B TW I559473B
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TW
Taiwan
Prior art keywords
semiconductor
wafer
protective
active circuit
circuit layer
Prior art date
Application number
TW104113157A
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Chinese (zh)
Other versions
TW201620094A (en
Inventor
子群 趙
蓋倫 柯克帕特里克
立德 羅
雷澤厄 拉曼 卡恩
明王 施
Original Assignee
美國博通公司
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Publication of TW201620094A publication Critical patent/TW201620094A/en
Application granted granted Critical
Publication of TWI559473B publication Critical patent/TWI559473B/en

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    • H01L23/3178—Coating or filling in grooves made in the semiconductor body
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Description

半導體邊界保護密封劑 Semiconductor boundary protection sealant

本申請根據於2014年10月20日提交的美國申請第14/518,947號和2014年8月15日提交的美國臨時申請第62/037,899號主張優先權，其全部內容通過引用結合於此。 The present application claims priority from U.S. Patent Application Serial No. 14/518,947, filed on Oct.

本發明係關於半導體封裝。 This invention relates to semiconductor packages.

半導體封裝可以是包含一個或複數個半導體電子元件的金屬殼、塑膠殼、玻璃殼、或者陶瓷殼，也稱為裸片(die)或者積體電路(IC)。封裝提供對衝擊和腐蝕、以及環境因素(例如濕氣、氧化、高溫、及污染物)的保護措施。電接觸或者導線從封裝伸出並被連接到其他裝置和/或至中間的基板，或者直接至電路板。封裝可以僅有兩個導線或者接觸用於例如二極體的裝置，或者在微處理器的情況下具有幾百個導線或者接觸。 The semiconductor package may be a metal case, a plastic case, a glass case, or a ceramic case including one or a plurality of semiconductor electronic components, also referred to as a die or an integrated circuit (IC). The package provides protection against shock and corrosion, as well as environmental factors such as moisture, oxidation, high temperatures, and contaminants. Electrical contacts or wires extend from the package and are connected to other devices and/or to the intermediate substrate, or directly to the circuit board. The package may have only two wires or contacts for devices such as diodes, or in the case of a microprocessor with hundreds of wires or contacts.

半導體封裝可以是專用的獨立裝置，可以裝配至最終產品的印刷電路板(PCB)或者印刷線路板(PWB)。IC可以連接至各種佈置的基板，以及堆疊多層。另外，封裝可以裝配在其他封裝之上以形成封裝堆疊裝置。半導體封裝也可以裝配至柔性電路，例如膠帶。 The semiconductor package can be a dedicated stand-alone device that can be assembled to a printed circuit board (PCB) or printed circuit board (PWB) of the final product. The IC can be connected to various arranged substrates as well as stacked multiple layers. Additionally, the package can be mounted over other packages to form a package stacking device. The semiconductor package can also be assembled to a flexible circuit, such as a tape.

具有幾個特徵與功能的用戶產品會變得更加複雜。另外，許多用戶產品變得更小。因此，製造商利用封裝替代作為在更小的區域或者體積中達到更多特徵與功能的方法。 User products with several features and functions become more complex. In addition, many user products have become smaller. Therefore, manufacturers use package replacement as a way to achieve more features and functions in a smaller area or volume.

半導體封裝可以完全以晶圓級製造，包括以柵陣列配置製作單個IC、多級金屬噴鍍、封裝、及焊球的黏接(或者其他傳導性互連)。完成的晶圓然後被分離，即，分為單個的封裝的IC。 Semiconductor packages can be fabricated entirely at the wafer level, including fabrication of individual ICs, multi-level metallization, packaging, and solder ball bonding (or other conductive interconnects) in a gate array configuration. The completed wafer is then separated, ie, divided into individual packaged ICs.

分離的通用方法是沿著IC之間的劃片街區(saw street)鋸切晶圓。晶圓劃片完全切割穿過單個封裝的IC。然而，鋸切可能損傷接近切口的區域，尤其介質層與金屬噴鍍層。另外，由於在分離步驟中的密封圈的損傷，裸片塗層可能變得與金屬噴鍍層分層。因此，分層可能穿透裸片的密封圈內部，並且導致IC的最終失敗。附加步驟也可能導致分層繼續傳播。其他類型的分離包括隱形切片和電漿切片。 A common method of separation is to saw the wafer along a saw street between the ICs. The wafer dicing is completely cut through the IC of a single package. However, sawing may damage areas close to the cut, especially the dielectric layer and the metallization. In addition, the die coating may become delaminated from the metallization due to damage to the seal during the separation step. Therefore, delamination may penetrate the inside of the seal of the die and cause a final failure of the IC. Additional steps may also cause the layer to continue to propagate. Other types of separation include invisible slices and plasma sections.

在實施方式中，半導體封裝包括包含有源電路層的半導體單元。半導體封裝還包括有源電路層上的複數個接合焊盤，複數個接合焊盤被配置為連接至相應的外部導電連接器。半導體封裝還包括填充有源電路層的所有凹槽邊緣的保護密封塗層。保護密封塗層包含外部晶圓分離表面(exterior wafer-singulated surface，外部被單一化晶圓表面)。 In an embodiment, a semiconductor package includes a semiconductor unit including an active circuit layer. The semiconductor package also includes a plurality of bond pads on the active circuit layer, the plurality of bond pads being configured to connect to respective external conductive connectors. The semiconductor package also includes a protective seal coating that fills all of the groove edges of the active circuit layer. The protective seal coating comprises an outer wafer-singulated surface (external wafer-singulated surface).

較佳為前述外部晶圓切割表面(exterior wafer-cut surface，外部被切割晶圓表面)包括鋸切、蝕刻或者雷射改變的邊緣的一個或複數個。 Preferably, the outer wafer-cut surface (external wafer-cut surface) includes one or more of sawing, etching or laser-changing edges.

較佳為前述保護密封塗層至少部分地覆蓋前述半導體單元的裸片(die)的周邊。 Preferably, the protective seal coating at least partially covers the periphery of the die of the semiconductor unit.

較佳為前述半導體封裝進一步包括焊球外部導電連接器。 Preferably, the aforementioned semiconductor package further includes a solder ball external conductive connector.

較佳為前述半導體封裝進一步包括接合線外部導電連接器。 Preferably, the aforementioned semiconductor package further includes a bond wire external conductive connector.

較佳為前述半導體封裝進一步包括附加保護密封塗層，係圍繞前述有源電路層上的前述外部導電連接器。 Preferably, the aforementioned semiconductor package further includes an additional protective sealing coating surrounding the aforementioned external conductive connector on the active circuit layer.

較佳為前述半導體封裝進一步包括附加保護密封塗層，係在前述半導體單元的非活性表面上。 Preferably, the aforementioned semiconductor package further includes an additional protective sealing coating on the inactive surface of the aforementioned semiconductor unit.

較佳為前述保護密封塗層減少或者消除圍繞每個前述半導體單元的密封圈。 Preferably, the aforementioned protective seal coating reduces or eliminates the seal surrounding each of the aforementioned semiconductor units.

在另一種實施方式中，半導體封裝包括具有有源電路表面和非活性表面的半導體單元。半導體封裝還包括沿著有源電路表面的所有暴露的邊緣形成並且部分地沿著半導體單元的裸片邊緣延伸的凹槽。半導體封裝還包括填充在凹槽內並具有切割的、鋸切的、蝕刻的、或者雷射修改的外部表面的保護密封塗層。 In another embodiment, a semiconductor package includes a semiconductor unit having an active circuit surface and an inactive surface. The semiconductor package also includes a recess formed along all exposed edges of the active circuit surface and extending partially along the die edge of the semiconductor unit. The semiconductor package also includes a protective seal coating that fills the recess and has a cut, saw, etched, or laser modified outer surface.

較佳為前述裸片邊緣的剩餘部分包含晶圓切割邊緣。 Preferably, the remainder of the edge of the die includes a wafer cut edge.

較佳為前述凹槽沿著前述半導體單元的前述裸片邊緣延伸。 Preferably, the recess extends along the edge of the die of the semiconductor unit.

較佳為前述保護密封塗層的前述切割的、鋸切的、蝕刻的、或者雷射改變的外表面沿著前述半導體單元的前述裸片邊緣延伸。 Preferably, the aforementioned cut, saw, etched, or laser modified outer surface of the aforementioned protective seal coating extends along the aforementioned die edge of the aforementioned semiconductor unit.

較佳為前述半導體封裝進一步包括保護密封塗層，在前述半導體單元的前述非活性表面上。 Preferably, the aforementioned semiconductor package further includes a protective sealing coating on the aforementioned inactive surface of the aforementioned semiconductor unit.

較佳為前述半導體封裝進一步包括複數個焊球，係以球柵陣列在前述有源電路表面上。 Preferably, the semiconductor package further includes a plurality of solder balls on the surface of the active circuit as a ball grid array.

較佳為前述半導體封裝包括焊線接合的半導體封裝(wire-bonded semiconductor package)。 Preferably, the aforementioned semiconductor package comprises a wire-bonded semiconductor package.

較佳為前述保護密封塗層取代圍繞每個前述半導體單元的密封圈。 Preferably, the aforementioned protective sealing coating replaces the sealing ring surrounding each of the aforementioned semiconductor units.

在另一種實施方式中，製造半導體封裝的方法包括將載帶(carry tape)黏至半導體晶圓的非活性表面。方法還包括在前述半導體晶圓的半導體單元之間切割或者蝕刻凹槽。凹槽通過半導體晶圓的有源電路層切割或者蝕刻。方法還包括將保護密封塗層材料施加到半導體單元之間的凹槽中，並通過保護密封塗層材料分離(singulate，單一化)半導體單元。 In another embodiment, a method of fabricating a semiconductor package includes adhering a carry tape to an inactive surface of a semiconductor wafer. The method also includes cutting or etching the recess between the semiconductor units of the aforementioned semiconductor wafer. The grooves are cut or etched through the active circuit layer of the semiconductor wafer. The method also includes applying a protective seal coat material to the grooves between the semiconductor units and singulate the semiconductor unit by protecting the seal coat material.

較佳為前述方法進一步包括將膜黏至前述半導體晶圓的外部導電連接器；以及圍繞前述外部導電連接器施加前述保護密封塗層材料 Preferably, the method further includes adhering the film to an outer conductive connector of the semiconductor wafer; and applying the protective seal coating material to the outer conductive connector.

較佳為前述方法進一步包括穿過前述半導體單元之間的前述半導體晶圓切割或者蝕刻前述凹槽。 Preferably, the foregoing method further includes cutting or etching the aforementioned recess through the aforementioned semiconductor wafer between the semiconductor units.

較佳為前述凹槽通過切割與蝕刻步驟的組合來形成。 Preferably, the aforementioned grooves are formed by a combination of cutting and etching steps.

較佳為前述施加發生在外部導電連接器連接至前述半導體單元之前。 Preferably, the aforementioned application occurs before the external conductive connector is connected to the aforementioned semiconductor unit.

較佳為前述方法進一步包括照射並去除通過遮罩中的開口暴露的前述保護密封塗層材料，前述開口對應於前述有源電路層的下面的接合焊盤。 Preferably, the foregoing method further comprises illuminating and removing the aforementioned protective seal coating material exposed through the opening in the mask, the opening corresponding to the underlying bond pad of the active circuit layer.

較佳為前述方法進一步包括在仍以晶圓形式的封裝之後或者作為分離的前述半導體單元的最後測試，利用裸片探測器測試前述半導體單元。 Preferably, the foregoing method further comprises testing the semiconductor unit with a die detector after the package still in the form of a wafer or as a final test of the separated semiconductor unit.

在另一種實施方式中，製造半導體封裝的方法包括將複數個半導體元件以板條格式或陣列格式黏至黏性載體。格式包含相鄰的每對半導體元件之間的間隙。方法還包括在間隙內施加模塑料(mold compound)，其中，模塑料圍繞所有暴露的有源電路邊緣。方法還包括通過施加的模塑料分離複數個半導體元件。 In another embodiment, a method of fabricating a semiconductor package includes bonding a plurality of semiconductor components to a viscous carrier in a strip format or an array format. The format includes a gap between each adjacent pair of semiconductor elements. The method also includes applying a mold compound within the gap, wherein the molding compound surrounds all exposed active circuit edges. The method also includes separating a plurality of semiconductor components by the applied molding compound.

較佳為前述方法進一步包括將外部焊球連接至有源電路層的相應的接觸焊盤；以及在前述有源電路層上施加前述模塑料以包圍連接的前述外部焊球。 Preferably, the foregoing method further comprises connecting external solder balls to respective contact pads of the active circuit layer; and applying the molding compound on the active circuit layer to surround the aforementioned external solder balls.

較佳為前述方法進一步包括在前述有源電路層與施加至前述外部焊球的底表面的膜之間的前述有源電路層上施加前述模塑料。 Preferably, the method further comprises applying the molding compound to the active circuit layer between the active circuit layer and the film applied to the bottom surface of the outer solder ball.

較佳為前述方法進一步包括雷射燒蝕施加至前述外部焊球的底表面的前述模塑料。 Preferably, the foregoing method further comprises laser ablating the aforementioned molding compound applied to the bottom surface of the outer solder ball.

較佳為前述方法進一步包括通過暴露的裸片模套(exposed die chase)或者壓模(compression mold)之一，在前述間隙內和前述有源電路層上施加前述模塑料。 Preferably, the foregoing method further comprises applying the molding compound in the gap and the active circuit layer by one of an exposed die chase or a compression mold.

較佳為前述方法進一步包括在施加至前述複數個半導體元件的背表面的前述模塑料上標記前述複數個半導 體元件。 Preferably, the method further includes marking the plurality of semiconductors on the molding compound applied to the back surface of the plurality of semiconductor elements. Body component.

較佳為前述複數個半導體元件包括重組的半導體元件。 Preferably, the plurality of semiconductor elements include a recombined semiconductor element.

較佳為前述方法進一步包括在以面板形式的裸片重組和鑄模成型之後、在成型的面板被分成條狀之後、或者作為分離的前述半導體元件的最後測試，測試前述複數個半導體元件。 Preferably, the foregoing method further comprises testing the plurality of semiconductor components after the die recombination and molding in the form of a panel, after the formed panel is divided into strips, or as a final test of the separated semiconductor component.

已經通過總體介紹的方式提供前述段落，但不限制於以下申請專利的範圍。通過參照以下結合附圖所做的詳細描述，可更好理解所描述的實施方式和另外的優點。 The foregoing paragraphs have been provided by way of a general introduction, but are not limited to the scope of the following patent application. The described embodiments and additional advantages are better understood by reference to the following detailed description of the drawings.

本公開內容的更完整的評價和其許多附帶的優點將容易地被獲得，如同通過結合附圖所考慮的以下詳細描述而變得更好理解。 A more complete appreciation of the present disclosure and its many additional advantages will be readily apparent as the

100、315、345、410、510、610、1330、1440、1510、1630、1720‧‧‧晶圓 100, 315, 345, 410, 510, 610, 1330, 1440, 1510, 1630, 1720‧‧ ‧ wafers

110、1110、1840‧‧‧IC 110, 1110, 1840‧‧‧ IC

120‧‧‧非活性表面 120‧‧‧Inactive surface

130、335、365、435、620、1320‧‧‧活性表面 130, 335, 365, 435, 620, 1320‧‧‧ active surface

140‧‧‧接觸焊盤 140‧‧‧Contact pads

310、400‧‧‧晶圓級球柵陣列/WLBGA 310, 400‧‧‧ Wafer Level Ball Grid Array / WLBGA

320、350、420、530、650、710、800、920、1000、1410、1420、1820‧‧‧半導體單元 320, 350, 420, 530, 650, 710, 800, 920, 1000, 1410, 1420, 1820‧‧‧ semiconductor units

330、430、630、2030‧‧‧焊球 330, 430, 630, 2030‧‧‧ solder balls

340‧‧‧晶圓級柱柵陣列 340‧‧‧ Wafer-level column grid array

360‧‧‧導體支柱/銅柱 360‧‧‧Conductor pillar/copper pillar

370‧‧‧線 370‧‧‧ line

440、640、1230、1350、1530‧‧‧載帶 440, 640, 1230, 1350, 1530‧‧‧ carrier tape

450、660‧‧‧第一切口 450, 660‧‧‧ first incision

460、720、910‧‧‧膠帶 460, 720, 910‧‧‧ tape

470、535、930、1430‧‧‧保護材料 470, 535, 930, 1430‧‧‧protective materials

475‧‧‧IC區域 475‧‧‧IC area

480‧‧‧密封圈 480‧‧‧ sealing ring

485‧‧‧劃線街區 485‧‧‧dash block

520‧‧‧第二切口 520‧‧‧second incision

540‧‧‧分離封裝 540‧‧‧Separate package

730‧‧‧保護塗層 730‧‧‧Protective coating

1120‧‧‧基板 1120‧‧‧Substrate

1130‧‧‧焊料凸塊 1130‧‧‧ solder bumps

1135、1145‧‧‧接合焊盤 1135, 1145‧‧‧ Bond pads

1150‧‧‧接合線 1150‧‧‧bonding line

1210‧‧‧半導體晶圓 1210‧‧‧Semiconductor Wafer

1220、1450、1520、1620、1850‧‧‧有源電路層 1220, 1450, 1520, 1620, 1850‧‧‧ active circuit layers

1240‧‧‧第一凹槽 1240‧‧‧first groove

1540‧‧‧第一凹槽/晶圓凹槽 1540‧‧‧First groove/wafer groove

1310、1610、1730‧‧‧遮罩帶 1310, 1610, 1730‧‧‧ mask strips

1340‧‧‧劃片街區 1340‧‧‧Scratch block

1360‧‧‧開口 1360‧‧‧ openings

1370‧‧‧保護密封填充材料 1370‧‧‧Protection seal packing material

1710、1830‧‧‧保護密封材料 1710, 1830‧‧‧Protection sealing material

1810‧‧‧分離 1810‧‧‧Separation

2010‧‧‧重組半導體元件 2010‧‧‧Reorganized semiconductor components

2020‧‧‧黏性載體 2020‧‧‧ Sticky carrier

2040‧‧‧保護塗層材料 2040‧‧‧Protective coating materials

2050‧‧‧單元 Unit 2050‧‧

1900、2300‧‧‧方法 1900, 2300‧‧‧ method

S1910、S1920、S1930、S1940、S2310、S2320、S2330‧‧‧步驟 S1910, S1920, S1930, S1940, S2310, S2320, S2330‧‧

圖1A至圖1B分別是根據一種實施方式的IC晶圓與單個分離的(singulated)IC的示意圖。 1A-1B are schematic illustrations of an IC wafer and a single singulated IC, respectively, in accordance with an embodiment.

圖2A至圖2B是根據一種實施方式的IC的活性表面上的接合焊盤圖案的示意圖。 2A-2B are schematic illustrations of bond pad patterns on active surfaces of an IC, in accordance with an embodiment.

圖3A至圖3D分別是根據一種實施方式的具有外部連接器的晶圓的剖視圖。 3A-3D are cross-sectional views, respectively, of a wafer with an external connector, in accordance with an embodiment.

圖4A是根據一種實施方式的具有劃片街區槽(saw street groove)的晶圓級球柵陣列(WLBGA)的剖視圖。 4A is a cross-sectional view of a wafer level ball grid array (WLBGA) having a saw street groove, in accordance with an embodiment.

圖4B是根據一種實施方式的具有保護塗層填充的劃片街區槽的WLBGA的剖視圖。 4B is a cross-sectional view of a WLBGA with a smear block groove with a protective coating fill, in accordance with an embodiment.

圖4C是根據一種實施方式的具有密封圈的晶圓級IC的俯視圖。 4C is a top plan view of a wafer level IC with a seal ring, in accordance with an embodiment.

圖4D是根據一種實施方式的沒有密封圈的晶圓級IC的俯視圖。 4D is a top plan view of a wafer level IC without a seal, in accordance with an embodiment.

圖5A至圖5B分別是根據一種實施方式的分離的半導體單元的剖視圖與3D仰視圖。 5A-5B are cross-sectional and 3D bottom views, respectively, of a separate semiconductor unit, in accordance with an embodiment.

圖6是根據一種實施方式的切割為半導體單元的全部晶圓的剖視圖。 6 is a cross-sectional view of all wafers cut into semiconductor units, in accordance with an embodiment.

圖7是根據一種實施方式的半導體單元之間填充的保護塗層的剖視圖。 7 is a cross-sectional view of a protective coating filled between semiconductor units in accordance with an embodiment.

圖8A至圖8B分別是根據一種實施方式的分離半導體單元的剖視圖與3D仰視圖。 8A-8B are cross-sectional and 3D bottom views, respectively, of a split semiconductor unit, in accordance with an embodiment.

圖9是根據一種實施方式的在半導體單元之間並且在半導體單元的頂部填充的保護塗層的剖視圖。 9 is a cross-sectional view of a protective coating between semiconductor units and on top of a semiconductor unit, in accordance with an embodiment.

圖10A至圖10B分別是根據一種實施方式的分離的半導體單元的剖視圖與3D仰視圖與俯視圖。 10A-10B are cross-sectional and 3D bottom and top views, respectively, of a separate semiconductor unit, in accordance with an embodiment.

圖11A是根據一種實施方式的將要連接至基板的BGA半導體單元的剖視圖。 11A is a cross-sectional view of a BGA semiconductor unit to be connected to a substrate, in accordance with an embodiment.

圖11B是根據一種實施方式的連接至基板的焊線接合的半導體單元的剖視圖。 11B is a cross-sectional view of a wire bond bonded semiconductor unit connected to a substrate, in accordance with an embodiment.

圖12A是根據一種實施方式的晶圓的剖視圖。 Figure 12A is a cross-sectional view of a wafer in accordance with an embodiment.

圖12B是根據一種實施方式的具有劃片街區槽的晶圓的剖視圖。 12B is a cross-sectional view of a wafer having diced block trenches, in accordance with an embodiment.

圖13A是根據一種實施方式的具有劃片街區槽和黏接的遮罩帶(mask tape)的晶圓的剖視圖。 13A is a cross-sectional view of a wafer having diced block grooves and bonded mask tapes, in accordance with an embodiment.

圖13B至圖13C分別是根據一種實施方式的晶圓的圖案化遮罩帶與保護填充的凹槽的剖視圖。 13B-13C are cross-sectional views of a patterned mask strip and a protective filled recess, respectively, of a wafer, in accordance with an embodiment.

圖14A至圖14B分別是根據一種實施方式的分離的半導體單元的剖視圖與3D仰視圖。 14A-14B are cross-sectional and 3D bottom views, respectively, of a separate semiconductor unit, in accordance with an embodiment.

圖15是根據一種實施方式的具有兩個劃片街區槽的晶圓的剖視圖。 15 is a cross-sectional view of a wafer having two diced block grooves, in accordance with an embodiment.

圖16是根據一種實施方式的具有施加的載帶(carry tape)和遮罩帶的晶圓的剖視圖。 16 is a cross-sectional view of a wafer with an applied carry tape and a mask strip, in accordance with an embodiment.

圖17A至圖17B顯示根據一種實施方式的具有保護填充的劃片街區的晶圓的剖視圖。 17A-17B show cross-sectional views of a wafer with a protected filled diced street, in accordance with an embodiment.

圖18A至圖18B分別是根據一種實施方式的分離半導體單元的剖視圖與3D仰視圖。 18A-18B are cross-sectional and 3D bottom views, respectively, of a split semiconductor unit, in accordance with an embodiment.

圖18C至圖18D分別是根據一種實施方式的分離的半導體單元的剖視圖與3D底視與俯視圖。 18C-18D are cross-sectional and 3D bottom and top views, respectively, of a separate semiconductor unit, in accordance with an embodiment.

圖19是根據一種實施方式的用於製造半導體封裝的方法的流程圖。 19 is a flow chart of a method for fabricating a semiconductor package in accordance with an embodiment.

圖20A顯示根據一種實施方式的重組半導體元件的陣 列。 20A shows an array of recombined semiconductor components in accordance with an embodiment. Column.

圖20B顯示根據一種實施方式的在重組半導體元件陣列上的模塑料。 Figure 20B shows a molding compound on an array of reconstituted semiconductor elements in accordance with an embodiment.

圖20C顯示根據一種實施方式的在雷射燒蝕之後的重組半導體元件陣列。 Figure 20C shows an array of recombined semiconductor elements after laser ablation, in accordance with an embodiment.

圖20D顯示根據一種實施方式的雷射燒蝕的重組半導體元件陣列的分離。 Figure 20D shows the separation of a laser ablated recombination semiconductor device array in accordance with one embodiment.

圖20E顯示根據一種實施方式的單獨封裝的重組半導體元件。 Figure 20E shows a separately packaged recombination semiconductor component in accordance with an embodiment.

圖20F顯示根據一種實施方式的單獨封裝的重組半導體元件的保護密封塗層的特寫圖示。 Figure 20F shows a close-up illustration of a protective seal coating of a separately packaged recombined semiconductor component in accordance with an embodiment.

圖21顯示根據一種實施方式的具有黏至黏性載體的焊球的重組半導體元件的鑄型步驟。 21 shows a mold step of a recombined semiconductor component having solder balls bonded to a viscous carrier, in accordance with an embodiment.

圖22A至圖22B顯示根據一種實施方式的晶圓或者重組的半導體元件的塑封模套(mold chase)與柔性焊盤鑄模成型步驟。 22A-22B illustrate a mold chase and flexible pad molding step of a wafer or reconstituted semiconductor component, in accordance with an embodiment.

圖23是根據一種實施方式的用於製造半導體封裝的方法的流程圖。 23 is a flow chart of a method for fabricating a semiconductor package in accordance with an embodiment.

IC可以以晶圓級形式製造，其中，10個、100個、或者1000個IC形成在單個半導體晶圓內。晶圓材料可以是矽、砷化鎵、或者其他半導體材料。參考附圖，其中，幾個視圖中相同參考標號代表相同的或者對應的部分，圖1A顯示包含複數個IC 110的晶圓100。IC 110在形狀上可以是正方形或者矩形，以及適於具體製造步驟的其他形狀。 The IC can be fabricated in wafer level form with 10, 100, or 1000 ICs formed in a single semiconductor wafer. The wafer material can be germanium, gallium arsenide, or other semiconductor materials. Referring to the drawings, wherein like reference numerals refer to the same or corresponding parts in the various aspects, FIG. 1A shows a wafer 100 comprising a plurality of ICs 110. The IC 110 can be square or rectangular in shape, as well as other shapes suitable for the particular manufacturing steps.

圖1B顯示IC 110的截面區域。IC 110具有非活性表面120和活性表面130。活性表面130具有複數個導電接觸區域或者接觸焊盤140，該複數個導電接觸區域或者接觸焊盤140設計成能使IC 110與其他裝置或者基板互連。IC接觸焊盤140可以具有多層，稱為凸點下金屬噴鍍(UBM，under-bump metallization)。基導電層可以包含鋁。因為焊料沒有很好地黏至鋁，所以另一個金屬層或者導電層可以在鋁墊片上圖案化。例示之UBM包括鋁、鎳釩、及銅的組合。然而，本文中描述的實施方式考慮幾個其他 UBM材料。本文中之後所指的接觸焊盤可以包括UBM層。 FIG. 1B shows a cross-sectional area of the IC 110. IC 110 has an inactive surface 120 and an active surface 130. The active surface 130 has a plurality of electrically conductive contact regions or contact pads 140 that are designed to interconnect the IC 110 with other devices or substrates. The IC contact pad 140 may have a plurality of layers, referred to as under-bump metallization (UBM). The base conductive layer may comprise aluminum. Since the solder does not adhere well to the aluminum, another metal layer or conductive layer can be patterned on the aluminum spacer. The illustrated UBM includes a combination of aluminum, nickel vanadium, and copper. However, the embodiments described herein consider several other UBM material. Contact pads referred to hereinafter may include a UBM layer.

接觸焊盤140可以佈置成各種配置，取決於其將連接至另一個裝置或者基板的介質。圖2A顯示IC 110的俯視圖，俯視圖顯示主要佈置在IC 110的活性表面130的中心的複數個接觸焊盤140。該配置可以用於倒裝晶片類型的裝置，其中，裝置可以具有連接至接觸焊盤140的焊料凸塊或者銅柱。倒裝晶片裝置和連接的焊料凸塊被“翻轉”並連接至另一個裝置或者基板的接觸焊盤。圖2B顯示IC 110的俯視圖，俯視圖顯示主要圍繞IC 110的活性表面130的周邊佈置的複數個接觸焊盤140。該配置可以用於焊線接合類型的裝置。例如焊線接合裝置作為堆疊的裝置，或者將並排的焊線接合裝置黏接。接合線將焊線接合裝置的接觸焊盤140連接至另一個裝置或者基板的接觸焊盤。 Contact pads 140 can be arranged in a variety of configurations depending on the medium they will be connected to another device or substrate. 2A shows a top view of IC 110 showing a plurality of contact pads 140 disposed primarily at the center of active surface 130 of IC 110. This configuration can be used for flip chip type devices where the device can have solder bumps or copper posts connected to contact pads 140. The flip chip device and the attached solder bumps are "flip" and connected to the contact pads of another device or substrate. 2B shows a top view of IC 110 showing a plurality of contact pads 140 disposed primarily around the perimeter of active surface 130 of IC 110. This configuration can be used for wire bond type devices. For example, wire bonding devices are used as stacked devices, or side-by-side wire bonding devices are bonded. The bond wires connect the contact pads 140 of the wire bond device to the contact pads of another device or substrate.

圖3A是晶圓級球柵陣列(WLBGA)310的剖視圖，包含晶圓315和複數個半導體單元320。WLBGA 310也可以稱為晶圓級晶片尺寸封裝(WLCSP)，封裝的尺寸與晶片的尺寸相同或者僅稍微大於晶片的尺寸。每個半導體單元320包含IC和晶圓315的活性表面335上的複數個焊球330。圖3A是簡化的圖示，其中，僅顯示四個半導體單元320。足夠尺寸的晶圓315可以在剖視圖中具有更多的半導體單元320，例如在圖1A中的晶圓100。 3A is a cross-sectional view of a wafer level ball grid array (WLBGA) 310 including a wafer 315 and a plurality of semiconductor cells 320. WLBGA 310 may also be referred to as a wafer level wafer size package (WLCSP), the size of the package being the same as the size of the wafer or only slightly larger than the size of the wafer. Each semiconductor unit 320 includes a plurality of solder balls 330 on the active surface 335 of the IC and wafer 315. FIG. 3A is a simplified illustration in which only four semiconductor units 320 are shown. A wafer 315 of sufficient size may have more semiconductor cells 320 in a cross-sectional view, such as wafer 100 in FIG. 1A.

圖3B是晶圓級柱柵陣列340的剖視圖，包含晶圓345和複數個半導體單元350。導體支柱360位於晶圓345的活性表面365上。導體支柱360是導電支柱，包含例如具有焊料表面塗層的銅芯。 3B is a cross-sectional view of wafer level pillar grid array 340 including wafer 345 and a plurality of semiconductor units 350. Conductor post 360 is located on active surface 365 of wafer 345. Conductor post 360 is a conductive post that contains, for example, a copper core with a solder surface coating.

圖3C顯示具有焊料蓋的銅柱360的外部連接。圖3D顯示線370外部連接。 Figure 3C shows the external connection of a copper post 360 with a solder cap. Figure 3D shows the external connection of line 370.

圖4A是WLBGA 400的剖視圖，包含晶圓410和複數個半導體單元420。焊球430黏接至球柵陣列(BGA)中的晶圓410的活性表面435。其他配置包括但不限於此，細間距球柵陣列(FBGA)、針柵陣列(PGA)、柱柵陣列(CGA)、脊柵陣列(LGA)、Z互連陣列、以及其他。載帶440黏至晶圓410背面的非活性表面以在整個製造步驟中使半導體單元420保持在適當的空間佈局中。圖4A還顯示每個半導 體單元420之間的凹槽或者第一切口450。在實施方式中，雷射光束在每個半導體單元420之間的劃片街區穿行。第一切口450穿透活性表面435以去除劃片街區內的介電材料與金屬噴鍍。雷射光束還部分地切割穿過晶圓410。在其他實施方式中，電漿腐蝕或者機械鋸切可以用於第一切口450。 4A is a cross-sectional view of WLBGA 400 including wafer 410 and a plurality of semiconductor units 420. Solder balls 430 are bonded to active surface 435 of wafer 410 in a ball grid array (BGA). Other configurations include, but are not limited to, fine pitch ball grid array (FBGA), pin grid array (PGA), pillar grid array (CGA), ridge grid array (LGA), Z interconnect array, and others. Carrier tape 440 is adhered to the inactive surface on the back side of wafer 410 to maintain semiconductor unit 420 in a suitable spatial layout throughout the fabrication steps. Figure 4A also shows each semi-conductor A groove or a first slit 450 between the body units 420. In an embodiment, the laser beam travels through a dicing street between each semiconductor unit 420. The first slit 450 penetrates the active surface 435 to remove dielectric material and metallization from the diced street. The laser beam is also partially cut through the wafer 410. In other embodiments, plasma erosion or mechanical sawing can be used for the first slit 450.

圖4B是WLBGA 400的剖視圖，其中，圖4A的載帶440已經去除。例如載帶440的黏帶可以通過機械去膠帶或者施加紫外線光至載帶440以使膠帶的黏性無效。膠帶460已經黏至焊球430的底表面。膠帶460的上表面具有厚的黏合層，其中，該黏合層圍繞每個焊球430。當在隨後步驟中施加真空時，黏合材料向上流動以部分地圍繞每個焊球430，使得在每個焊球430的底表面上的膠帶460中形成凹槽。然而，非黏帶也可以用於膠帶460。在其後的步驟，保護材料470填充在形成在晶圓410的活性表面435與膠帶460的頂表面之間的間隙內以包圍焊球430的暴露部分。保護材料470還填充通過第一切口450形成的劃片街區凹槽。施加真空以提高保護材料470的毛細流動以到達並填充晶圓410與膠帶460之間的所有的開放空間並且填充通過第一切口450形成的凹槽內。 4B is a cross-sectional view of the WLBGA 400 in which the carrier tape 440 of FIG. 4A has been removed. For example, the adhesive tape of the carrier tape 440 can be used to mechanically remove the tape or apply ultraviolet light to the carrier tape 440 to invalidate the adhesiveness of the tape. The tape 460 has adhered to the bottom surface of the solder ball 430. The upper surface of the tape 460 has a thick adhesive layer, wherein the adhesive layer surrounds each of the solder balls 430. When a vacuum is applied in a subsequent step, the adhesive material flows upward to partially surround each of the solder balls 430 such that a groove is formed in the tape 460 on the bottom surface of each of the solder balls 430. However, a non-adhesive tape can also be used for the tape 460. In a subsequent step, the protective material 470 is filled in a gap formed between the active surface 435 of the wafer 410 and the top surface of the tape 460 to surround the exposed portion of the solder ball 430. The protective material 470 also fills the dicing block recess formed by the first slit 450. A vacuum is applied to increase the capillary flow of the protective material 470 to reach and fill all of the open space between the wafer 410 and the tape 460 and fill the recess formed by the first slit 450.

保護材料470在劃片街區凹槽內並且沿著活性表面435提供保護密封塗層。保護材料470由熱固膠黏劑、使用膜輔助鑄模成型的模塑料、或者環氧樹脂製成。本文中描述的實施方式也考慮沿著半導體裸片的表面提供密封和保護塗層的其他材料。 The protective material 470 provides a protective seal coating within the diced trench and along the active surface 435. The protective material 470 is made of a thermosetting adhesive, a molding compound molded using a film-assisted molding, or an epoxy resin. Embodiments described herein also contemplate other materials that provide a seal and protective coating along the surface of the semiconductor die.

在一種實施方式中，焊球430在凸出高度上約200微米。膠帶460的黏合材料圍繞焊球430約100微米的高度。這留下約100微米的差距，其中，保護材料470存在於活性表面435與膠帶460之間。本文中描述的實施方式考慮其他大小的保護材料470，並且將基於半導體元件的類型、材料、及大小不同。 In one embodiment, the solder balls 430 are about 200 microns in elevation. The adhesive material of the tape 460 surrounds the solder balls 430 by a height of about 100 microns. This leaves a gap of about 100 microns in which protective material 470 is present between active surface 435 and tape 460. The embodiments described herein consider other sizes of protective material 470 and will vary based on the type, material, and size of the semiconductor components.

圖4C顯示晶圓級形式的一些IC的俯視圖。圖4C僅顯示晶圓的部分圖示，因為在晶圓上可能存在更多的IC。IC區域475位於結構的中心，被密封圈480包圍。密封圈 480被用於保護IC。在實施方式中，密封圈480可以由兩個金屬圍欄製成，其中，每個金屬層上的金屬平面具有在金屬平面之間的金屬通孔。作為一個例子，兩個金屬圍欄的寬度可以是幾微米，例如2至5微米的寬度並且在金屬圍欄中間分開幾微米。劃線街區485存在於每個IC區域475與它的密封圈480之間。 Figure 4C shows a top view of some ICs in wafer level form. Figure 4C shows only a partial illustration of the wafer as there may be more ICs on the wafer. The IC region 475 is located at the center of the structure and is surrounded by a seal ring 480. Seal ring 480 is used to protect the IC. In an embodiment, the seal ring 480 can be made from two metal rails, wherein the metal plane on each metal layer has metal through holes between the metal planes. As an example, the width of the two metal fences may be a few microns, such as a width of 2 to 5 microns and separated by a few microns between the metal fences. A scribe block 485 is present between each IC region 475 and its seal ring 480.

本文中描述的用於保護性邊緣密封劑的實施方式提供減少或者完全去除密封圈，如在圖4D中顯示的。這在IC之間提供更大的區域。因此，IC可以一起更接近以利用更多的晶圓空間，並且產生每個晶圓的更多數量的總裸片。 Embodiments described herein for a protective edge sealant provide for reduced or complete removal of the seal, as shown in Figure 4D. This provides a larger area between the ICs. As a result, the ICs can be closer together to utilize more wafer space and produce a greater number of total dies per wafer.

在圖5A中，已經去除圖4B的膠帶460，並且晶圓510在半導體單元530之間的第二切口520中分離。劃片切割穿過半導體單元530之間的保護材料535，並且還切割穿過其餘的晶圓510以使半導體單元530遠離彼此完全分離。因為保護材料535存在於活性表面上以及凹槽內，所以晶圓劃片在執行第二切口520時，破壞介電層或者金屬噴鍍層。產生的分離封裝540具有在裸片的所有四個側邊緣並部分向上形成並且在圍繞每個焊球的活性表面上的保護材料。圖5B是分離封裝540的底部三維圖示。 In FIG. 5A, the tape 460 of FIG. 4B has been removed, and the wafer 510 is separated in the second slit 520 between the semiconductor units 530. The dicing cuts through the protective material 535 between the semiconductor cells 530 and also cuts through the remaining wafers 510 to completely separate the semiconductor cells 530 away from each other. Because the protective material 535 is present on the active surface as well as within the recess, the wafer dicing destroys the dielectric layer or metallization when the second slit 520 is performed. The resulting split package 540 has protective material formed on all four side edges of the die and partially up and on the active surface surrounding each solder ball. FIG. 5B is a three-dimensional illustration of the bottom of the split package 540.

圖6是另一實施方式的剖視圖600，顯示具有活性表面620的晶圓610、和連接至活性表面620的焊球630。晶圓610的非活性表面黏至載帶640以保持分離後的半導體單元650的空間佈局。製成第一切口660，在第一切口660中，晶圓610被部分地切割，例如在圖4A中顯示的。例如，第一切口660可以通過雷射刻槽製成。第一切口的例示是寬度為50微米至70微米。然而，本文中描述的實施方式考慮其他大小以適應半導體單元650的不同類型、材料、及尺寸。第二切口在劃片街區槽內製成以完全切穿晶圓610。第二切口延伸到載帶640中，但是沒有完全切穿載帶640。第二切口可以通過機械鋸切製成。替代地，代替兩個單獨的切口，可以通過電漿腐蝕或者機械鋸切製成單個切口。 FIG. 6 is a cross-sectional view 600 of another embodiment showing wafer 610 having active surface 620 and solder balls 630 coupled to active surface 620. The inactive surface of the wafer 610 is adhered to the carrier tape 640 to maintain the spatial layout of the separated semiconductor unit 650. A first slit 660 is formed in which the wafer 610 is partially cut, such as shown in Figure 4A. For example, the first slit 660 can be made by a laser notch. An illustration of the first slit is a width of 50 microns to 70 microns. However, the embodiments described herein contemplate other sizes to accommodate different types, materials, and sizes of semiconductor unit 650. The second slit is made in the dicing trench to completely cut through the wafer 610. The second slit extends into the carrier tape 640 but does not completely cut through the carrier tape 640. The second slit can be made by mechanical sawing. Alternatively, instead of two separate slits, a single slit can be made by plasma etching or mechanical sawing.

載帶640保持半導體單元650的空間佈局，並且黏至晶圓邊緣(未圖示)以提供剛性框架。另一實施方式包括使 載帶640延伸，即，拉長載帶640，這可以通過對晶圓邊緣內的載帶640的背面按壓執行。這提供半導體單元650之間的更大的間隙(是寬度的兩倍)，即，100微米至140微米，如在圖6的底部附圖中顯示的。這使得提供更大的間隙，而無需實際上鋸切那樣大的切口。在該例示中，製成50微米至70微米的切口，但實現100微米至140微米的寬度。 Carrier tape 640 maintains the spatial layout of semiconductor unit 650 and adheres to the edge of the wafer (not shown) to provide a rigid frame. Another embodiment includes making The carrier tape 640 extends, i.e., the carrier tape 640 is elongated, which can be performed by pressing the back side of the carrier tape 640 within the edge of the wafer. This provides a larger gap (twice the width) between the semiconductor cells 650, i.e., 100 microns to 140 microns, as shown in the bottom drawing of Figure 6. This allows for a larger gap without the need for a saw cut as large as it actually cuts. In this illustration, a cut of 50 microns to 70 microns is made, but a width of 100 microns to 140 microns is achieved.

圖7是顯示缺少圖6的載帶640的剖視圖。另一個膠帶720黏至半導體單元710的焊球的底表面。附貼至膠帶720的半導體單元710可以是與圖6相同的半導體單元和相同的佈局，或者半導體單元710可以是黏至膠帶720用於進一步處理的幾個選擇單元。膠帶720可以是圍繞焊球的黏帶或者非黏帶。保護塗層730從半導體單元710的上位置填充到劃片街區槽中，並且在半導體單元710與膠帶720之間的活性表面上。替代地，保護塗層730在上表面仍黏至圖6中顯示的載帶640的同時從半導體單元710的下表面填充。 FIG. 7 is a cross-sectional view showing the carrier tape 640 lacking FIG. Another tape 720 is adhered to the bottom surface of the solder ball of the semiconductor unit 710. The semiconductor unit 710 attached to the tape 720 may be the same semiconductor unit and the same layout as in FIG. 6, or the semiconductor unit 710 may be several selection units adhered to the tape 720 for further processing. Tape 720 can be an adhesive tape or a non-adhesive tape that surrounds the solder balls. The protective coating 730 is filled from the upper position of the semiconductor unit 710 into the dicing street groove and on the active surface between the semiconductor unit 710 and the tape 720. Alternatively, the protective coating 730 is filled from the lower surface of the semiconductor unit 710 while the upper surface remains adhered to the carrier tape 640 shown in FIG.

在圖8A中，在每個相鄰的裸片之間切割保護塗層，但是沒有切穿半導體單元的任何有源電路。分離的半導體單元800除了具有活性表面上圍繞焊球的保護塗層，還具有在所有的四個側邊緣的整個表面上的保護塗層。圖8B是分離的半導體單元800的底部三維圖示。 In Figure 8A, a protective coating is cut between each adjacent die, but without any active circuitry that cuts through the semiconductor unit. The separated semiconductor unit 800 has a protective coating on the entire surface of all four side edges in addition to the protective coating surrounding the solder balls on the active surface. FIG. 8B is a bottom three-dimensional illustration of a separate semiconductor unit 800.

圖9是在與上述實施方式類似的處理之後的黏至四個半導體單元920的膠帶910的剖視圖。膠帶910也可以是膠帶圍繞焊球的非黏帶。保護材料930填充在半導體單元920之間及頂部上。保護材料930也填充在每個半導體單元920與膠帶910之間的間隙。 FIG. 9 is a cross-sectional view of the tape 910 adhered to the four semiconductor units 920 after the process similar to the above embodiment. Tape 910 can also be a non-adhesive tape around the solder ball. A protective material 930 is filled between and on the top of the semiconductor cells 920. The protective material 930 also fills the gap between each of the semiconductor units 920 and the tape 910.

圖10A是顯示四個半導體單元的分離的剖視圖。充滿保護材料的劃片街區被切割，但是半導體單元的有源電路未被切割。除了焊球的下表面，最終封裝的半導體單元1000完全被保護材料包圍。圖10B是封裝的半導體單元1000的底部與頂部三維圖示。 Figure 10A is a cross-sectional view showing the separation of four semiconductor units. The dicing block filled with protective material is cut, but the active circuitry of the semiconductor unit is not cut. In addition to the lower surface of the solder ball, the final packaged semiconductor unit 1000 is completely surrounded by the protective material. FIG. 10B is a three-dimensional illustration of the bottom and top of the packaged semiconductor unit 1000.

參考圖3A至圖10描述的實施方式，針對倒裝晶片類型的裝置，在該裝置中，焊球、支柱、或者圓柱連接至半 導體單元的有源表面。圖11A是顯示在IC 1110的有源表面上具有焊料凸塊1130的IC 1110的框圖。IC 1110“翻轉”使得有源表面在下邊緣上。這允許焊料凸塊1130直接連接至另一個裝置或者基板，例如基板1120。雖然未圖示，基板1120在其上表面上具有與IC 1110上的焊料凸塊1130的圖案匹配的接觸焊盤。焊料凸塊1130被帶入與基板1120的接觸焊盤接觸，並上升至焊料凸塊1130開始回流或者液化的溫度。當溫度降低時，回流的焊料凸塊1130凝固，並且變得電性地且機械地連接至基板1120上的接觸焊盤。 Referring to the embodiment depicted in Figures 3A through 10, for a flip chip type device in which solder balls, struts, or cylinders are connected to the half The active surface of the conductor unit. FIG. 11A is a block diagram showing an IC 1110 having solder bumps 1130 on the active surface of IC 1110. The IC 1110 "flips" such that the active surface is on the lower edge. This allows the solder bump 1130 to be directly connected to another device or substrate, such as the substrate 1120. Although not shown, the substrate 1120 has contact pads on its upper surface that match the pattern of the solder bumps 1130 on the IC 1110. The solder bumps 1130 are brought into contact with the contact pads of the substrate 1120 and rise to a temperature at which the solder bumps 1130 begin to reflow or liquefy. When the temperature is lowered, the reflowed solder bumps 1130 solidify and become electrically and mechanically connected to the contact pads on the substrate 1120.

以上參考圖3A至圖5描述的實施方式在形成並且填充劃片街區之前並在半導體單元的分離之前，處理為在步驟早期使焊球連接至有源電路層。替代地，可以首先執行劃片街區的形成與填充，並且焊球或者其他導電性結構可以在處理的末尾連接至半導體單元。 The embodiments described above with reference to Figures 3A through 5 are processed prior to forming and filling the dicing streets and prior to the separation of the semiconductor cells, to connect the solder balls to the active circuit layers early in the step. Alternatively, the formation and filling of the dicing streets may be performed first, and solder balls or other conductive structures may be attached to the semiconductor unit at the end of the process.

現在回到圖3A至圖5描述替代實施方式。在該替代實施方式中，圖3A至圖3B的晶圓315與晶圓345不具有此時連接至晶圓的焊球330或者導體支柱360。在圖4A中，載帶440黏至晶圓410的後表面，並且在晶圓410的活性表面中的劃片街區中製成第一切口450。在該替代實施方式中未使用圖4B中的膠帶460。替代地，保護材料470填充在劃片街區中的第一切口450內，並且還完全覆蓋晶圓410的活性表面。焊接遮罩或者焊料範本，在使半導體單元分離之前施加在覆蓋有源電路層的保護塗層上。焊接遮罩可以由在暴露於紫外線(UV)光時可以圖案化的聚合物或者感光成像材料製成。包含與半導體單元的活性表面上的接觸焊盤匹配的複數個開口的焊接遮罩放置在晶圓上的保護塗層上。紫外線光穿過焊接遮罩中的開口暴露保護塗層。隨後去除焊接遮罩，並且去除保護塗層的暴露區域。焊球放置在接觸焊盤上的保護塗層的開口內，在圖5中顯示的分離之前或分離之後。焊球回流連接至半導體單元的接觸焊盤。 An alternative embodiment will now be described with reference to Figures 3A-5. In this alternative embodiment, wafer 315 and wafer 345 of FIGS. 3A-3B do not have solder balls 330 or conductor posts 360 that are now connected to the wafer. In FIG. 4A, carrier tape 440 is adhered to the back surface of wafer 410 and a first slit 450 is made in the dicing street in the active surface of wafer 410. The tape 460 of Figure 4B is not used in this alternative embodiment. Alternatively, the protective material 470 is filled within the first slit 450 in the dicing block and also completely covers the active surface of the wafer 410. A solder mask or solder template is applied over the protective coating overlying the active circuit layer prior to separating the semiconductor unit. The solder mask can be made of a polymer or photoimageable material that can be patterned when exposed to ultraviolet (UV) light. A solder mask comprising a plurality of openings matching the contact pads on the active surface of the semiconductor unit is placed over the protective coating on the wafer. Ultraviolet light exposes the protective coating through openings in the solder mask. The solder mask is then removed and the exposed areas of the protective coating are removed. The solder balls are placed in the opening of the protective coating on the contact pads, either before or after the separation shown in FIG. The solder balls are reflowed to the contact pads of the semiconductor unit.

圖11B是顯示另一種類型的裝置，稱為焊線接合裝置的方塊圖。IC 1110相對於膠黏劑連接的基板1120直立放 置。上活性表面包含接合焊盤1135，接合焊盤1135通過接合線1150連接至基板1120的接合焊盤1145。圖11B僅顯示焊線接合裝置的一種實施方式。本文中描述的實施方式考慮用於焊線接合至其他裝置和/或其他類型的基板的幾個其他配置。 Figure 11B is a block diagram showing another type of device, called a wire bonding device. IC 1110 is placed upright with respect to the substrate 1120 to which the adhesive is attached Set. The upper active surface includes bond pads 1135 that are connected to bond pads 1145 of substrate 1120 by bond wires 1150. Figure 11B shows only one embodiment of a wire bonding apparatus. Embodiments described herein contemplate several other configurations for wire bonding to other devices and/or other types of substrates.

現在將描述用於隨後期望焊線接合的IC的實施方式。圖12A顯示半導體晶圓1210，半導體晶圓1210包含有源電路層1220。如在圖12B中顯示的，為了準備用於晶圓切割的晶圓，載帶1230附貼至半導體晶圓1210的非活性表面。晶圓切口或者第一凹槽1240通過半導體晶圓1210的劃片街區形成。晶圓切口或者第一凹槽1240可以通過雷射刻槽、電漿腐蝕、或者機械鋸切形成。在一種實施方式中，晶圓切口或者第一凹槽1240從劃片街區去除任何鈍化層、金屬噴鍍層、及層間介電材料，並且部分地切穿矽基板。 Embodiments of an IC for subsequent wire bonding will now be described. FIG. 12A shows a semiconductor wafer 1210 that includes an active circuit layer 1220. As shown in FIG. 12B, in order to prepare a wafer for wafer dicing, carrier tape 1230 is attached to the inactive surface of semiconductor wafer 1210. The wafer cut or first recess 1240 is formed by a dicing street of the semiconductor wafer 1210. The wafer cut or first recess 1240 can be formed by laser notching, plasma etching, or mechanical sawing. In one embodiment, the wafer slit or first recess 1240 removes any passivation layer, metallization, and interlayer dielectric material from the dicing street and partially cuts through the germanium substrate.

圖13A顯示遮罩帶1310施加至晶圓1330的活性表面1320，以為填充劃片街區1340作準備。載帶1350仍黏至晶圓1330的非活性表面。圖13B顯示直接在劃片街區1340上的遮罩帶1310內的開口1360的形成。開口1360可以通過雷射圖案化形成，例如雷射直射或者蝕刻。開口1360可以部分暴露劃片街區1340，如在圖13B中顯示的，或者開口1360可以完全暴露劃片街區1340。 FIG. 13A shows the mask strip 1310 applied to the active surface 1320 of the wafer 1330 in preparation for filling the dicing block 1340. Carrier tape 1350 remains adhered to the inactive surface of wafer 1330. FIG. 13B shows the formation of an opening 1360 in the mask strip 1310 directly on the dicing block 1340. The opening 1360 can be formed by laser patterning, such as direct laser or etching. The opening 1360 can partially expose the dicing block 1340, as shown in FIG. 13B, or the opening 1360 can completely expose the dicing block 1340.

圖13C顯示利用保護密封填充材料1370填充劃片街區1340。保護密封填充材料1370包括，但不限於模塑料、熱固性環氧樹脂、樹脂、或者膠黏劑。填充步驟包括，但不限於鑄模成型、真空鑄模成型、沉浸塗層、噴塗、及旋轉塗層。 FIG. 13C shows filling the dicing block 1340 with a protective seal fill material 1370. Protective seal fill material 1370 includes, but is not limited to, molding compound, thermoset epoxy, resin, or adhesive. Filling steps include, but are not limited to, mold forming, vacuum casting, immersion coating, spray coating, and spin coating.

圖14A顯示圖示13C的遮罩帶1310已經去除並且半導體單元1410分離以形成單獨的封裝的半導體單元1420。在一種實施方式中，晶圓劃片穿透保護材料1430並且切割通過剩餘的晶圓1440。晶圓分離的其他方法包括，但不限於蝕刻切割、雷射燒蝕、隱形切片、及電漿切片。封裝的半導體單元1420包含完全圍繞封裝的半導體單元1420的下週邊的保護材料1430，使得有源電路層1450 的所有的邊緣被保護材料1430保護。圖14B是封裝的半導體單元1420的底部三維圖示。 FIG. 14A shows that the mask strip 1310 of FIG. 13C has been removed and the semiconductor unit 1410 is separated to form a separate packaged semiconductor unit 1420. In one embodiment, the wafer scribes through the protective material 1430 and is diced through the remaining wafer 1440. Other methods of wafer separation include, but are not limited to, etch cutting, laser ablation, invisible slicing, and plasma slicing. The packaged semiconductor unit 1420 includes a protective material 1430 that completely surrounds the lower perimeter of the packaged semiconductor unit 1420 such that the active circuit layer 1450 All of the edges are protected by a protective material 1430. FIG. 14B is a three-dimensional illustration of the bottom of packaged semiconductor unit 1420.

圖15顯示用於期望隨後的焊線接合的IC的晶圓級處理的另一種實施方式。包含複數個IC的晶圓1510具有有源電路層1520。載帶1530黏至晶圓1510的非活性表面。在晶圓1510與有源電路層1520內的劃片街區中製成複數個第一切口或者第一凹槽1540。例如，晶圓切口或者晶圓凹槽(第一凹槽)1540可以通過雷射刻槽、電漿腐蝕、或者機械鋸切形成。在一種實施方式中，晶圓切口或者晶圓凹槽1540從劃片街區去除任何鈍化層、金屬噴鍍層、及層間介電材料，並且部分地通過矽基板切割。第二切口或者第二凹槽1550完全通過晶圓1510製成並且部分地到載帶1530中。在實施方式中，第二切口或者第二凹槽1550通過晶圓鋸切製成。圖15顯示第一切口或者第一凹槽1540在寬度上比第二切口或者第二凹槽1550大。在一種實施方式中，較大的第一凹槽1540通過雷射刻槽或者電漿腐蝕形成，而第二凹槽1550通過晶圓鋸切形成。大部分的載帶1530仍然具有黏性，因此，繼續將分離的半導體單元相對於彼此保持在原位。 Figure 15 shows another embodiment of a wafer level process for an IC that is expected to be followed by wire bonding. The wafer 1510 including a plurality of ICs has an active circuit layer 1520. Carrier tape 1530 is adhered to the inactive surface of wafer 1510. A plurality of first slits or first recesses 1540 are formed in the dicing streets within the wafer 1510 and the active circuit layer 1520. For example, a wafer cut or wafer recess (first recess) 1540 can be formed by laser notching, plasma etching, or mechanical sawing. In one embodiment, the wafer scribe or wafer recess 1540 removes any passivation layer, metallization, and interlayer dielectric material from the dicing streets and is partially cut through the ruthenium substrate. The second slit or second recess 1550 is made entirely through the wafer 1510 and partially into the carrier tape 1530. In an embodiment, the second slit or second groove 1550 is formed by wafer sawing. FIG. 15 shows that the first slit or first groove 1540 is larger in width than the second slit or the second groove 1550. In one embodiment, the larger first groove 1540 is formed by laser grooving or plasma etching, while the second groove 1550 is formed by wafer sawing. Most of the carrier tape 1530 remains viscous and, therefore, continues to hold the separated semiconductor units in place relative to one another.

在另一種實施方式中，代替上述的第二切口或者第二凹槽，晶圓的背表面可以後磨削至第一凹槽的頂部。黏性載體或者使晶圓穩定的其他手段可用於在後磨削步驟中將晶圓保持在原位。該方法在較小的最後裸片方面佔優勢。 In another embodiment, instead of the second slit or the second recess described above, the back surface of the wafer may be post-grinded to the top of the first recess. Adhesive carriers or other means of stabilizing the wafer can be used to hold the wafer in place during the post-grinding step. This method predominates in the smaller final die.

圖16顯示黏至晶圓1630的有源電路層1620的遮罩帶1610。圖17A顯示圖示15的載帶1530已經去除。保護密封材料1710從晶圓1720的背面填充在劃片街區中。遮罩帶1730為保護密封材料1710提供備用。圖17B顯示另一種實施方式，其中，保護密封材料1710施加至晶圓的後非活性表面，以及劃片街區內。保護密封材料1710包括，但不限於模塑料、熱固性環氧樹脂、樹脂、或者膠黏劑。保護密封材料1710可以通過鑄模成型、真空輔助鑄模成型、浸沒施加、噴塗層、及旋轉塗層施加。本文中描述的實施方式亦考慮其他施加方法。 FIG. 16 shows mask strip 1610 adhered to active circuit layer 1620 of wafer 1630. Figure 17A shows that the carrier tape 1530 of Figure 15 has been removed. The protective sealing material 1710 is filled from the back side of the wafer 1720 in the dicing block. The mask strip 1730 provides a backup for the protective sealing material 1710. Figure 17B shows another embodiment in which the protective sealing material 1710 is applied to the rear inactive surface of the wafer, as well as the dicing block. The protective sealing material 1710 includes, but is not limited to, a molding compound, a thermosetting epoxy resin, a resin, or an adhesive. The protective sealing material 1710 can be applied by die casting, vacuum assisted molding, immersion application, spray coating, and spin coating. Embodiments described herein also contemplate other methods of application.

圖18A是圖17A的實施方式的剖視圖，其中，利用保 護密封材料填充劃片街區。半導體單元在劃片街區內的保護密封材料之間分離1810，其中，在分離1810步驟中電路未被切割。最後封裝的半導體單元1820顯示保護密封材料1830完全圍繞IC1840的週邊以覆蓋IC的側邊緣與有源電路層1850的邊緣。圖18B是封裝的半導體單元1820的底部三維圖示。 Figure 18A is a cross-sectional view of the embodiment of Figure 17A, wherein The sealing material fills the diced block. The semiconductor unit separates 1810 between the protective sealing materials within the dicing block, wherein the circuit is not cut during the separation 1810 step. The last packaged semiconductor unit 1820 shows that the protective sealing material 1830 completely surrounds the perimeter of the IC 1840 to cover the side edges of the IC and the edges of the active circuit layer 1850. FIG. 18B is a three-dimensional illustration of the bottom of packaged semiconductor unit 1820.

圖18C是圖17B的實施方式的剖視圖，其中，利用保護密封材料填充劃片街區並覆蓋晶圓的後非活性表面。半導體單元在劃片街區內的保護密封材料之間分離1810，其中，在分離1810步驟中電路未被切割。最後封裝的半導體單元1820顯示保護密封材料1830完全圍繞週邊與IC1840的後非活性表面。除了有源電路層1850的底表面，最後封裝的半導體單元1820完全被保護密封材料1830覆蓋。圖18D是封裝的半導體單元1820的底部與頂部三維圖示。 Figure 18C is a cross-sectional view of the embodiment of Figure 17B in which the dicing street is filled with a protective sealing material and covers the back inactive surface of the wafer. The semiconductor unit separates 1810 between the protective sealing materials within the dicing block, wherein the circuit is not cut during the separation 1810 step. The last packaged semiconductor unit 1820 shows that the protective sealing material 1830 completely surrounds the perimeter and the rear inactive surface of the IC 1840. In addition to the bottom surface of the active circuit layer 1850, the last packaged semiconductor unit 1820 is completely covered by the protective sealing material 1830. Figure 18D is a three-dimensional illustration of the bottom and top of the packaged semiconductor unit 1820.

現在回到圖12A至圖14描述替代實施方式。圖12A的半導體晶圓1210包含有源電路層1220。圖12B顯示半導體晶圓1210的背面上的載帶1230。第一切口或者第一凹槽1240通過有源電路層1220製成並且部分地通過半導體單元之間的矽晶圓。在圖13A中顯示的遮罩帶1310未施加至該替代實施方式。替代地，圖13C的保護密封填充材料1370填充在第一切口或者第一凹槽1240內，並且還覆蓋有源電路層1220。這在整個晶圓1330的活性表面上產生保護密封填充材料1370的連續層。 An alternative embodiment will now be described with reference to Figures 12A-14. The semiconductor wafer 1210 of FIG. 12A includes an active circuit layer 1220. FIG. 12B shows carrier tape 1230 on the back side of semiconductor wafer 1210. The first slit or first recess 1240 is made through the active circuit layer 1220 and partially through the germanium wafer between the semiconductor units. The mask strip 1310 shown in Figure 13A is not applied to this alternative embodiment. Alternatively, the protective seal fill material 1370 of FIG. 13C is filled within the first slit or first recess 1240 and also covers the active circuit layer 1220. This creates a continuous layer of protective seal fill material 1370 over the active surface of the entire wafer 1330.

包含與半導體晶圓的活性表面上的接觸焊盤匹配的複數個開口的焊接遮罩放置在晶圓上的保護密封填充材料1370上。焊接遮罩可以由聚合物或者感光成像材料製成，聚合物或者感光成像材料在暴露於紫外線(UV)光時可以圖案化。紫外線光通過焊接遮罩中的開口暴露保護密封填充材料1370。隨後去除焊接遮罩，並且去除保護密封填充材料1370的暴露區域。接合線可以連接至保護密封填充材料1370的開口內有源電路層上的接觸焊盤。 A solder mask comprising a plurality of openings matching the contact pads on the active surface of the semiconductor wafer is placed over the protective seal fill material 1370 on the wafer. The solder mask can be made of a polymer or photoimageable material that can be patterned when exposed to ultraviolet (UV) light. Ultraviolet light exposes the protective seal fill material 1370 through the opening in the solder mask. The solder mask is then removed and the exposed areas of the protective seal fill material 1370 are removed. The bond wires can be connected to contact pads on the active circuit layer within the opening of the protective seal fill material 1370.

參考圖19，將描述製造半導體封裝的方法1900。在步驟S1910，載帶黏至半導體晶圓的非活性表面。在步驟S1920，在半導體晶圓的半導體單元之間切割或者蝕刻凹 槽。凹槽切穿或者蝕刻穿過半導體晶圓的有源電路層。在一種實施方式中，凹槽利用切割與蝕刻步驟的組合形成。在步驟S1930，保護密封塗層材料施加到半導體單元之間的凹槽裡。在一種實施方式中，施加步驟出現在連接外部導電連接器至半導體單元之前。在步驟S1940，半導體單元通過保護密封塗層材料分離。在一種實施方式中，方法1900還包括將膜黏至半導體晶圓的外部導電連接器，並圍繞外部導電連接器施加保護密封塗層材料。在另一種實施方式中，方法還包括穿過半導體單元之間的半導體晶圓完全切割或者蝕刻凹槽。在另一種實施方式中，方法還包括照射並去除通過遮罩中的開口暴露的保護密封塗層材料，其中，開口與有源電路層的下面的接合焊盤對應。 Referring to Figure 19, a method 1900 of fabricating a semiconductor package will be described. In step S1910, the carrier tape is adhered to the inactive surface of the semiconductor wafer. Cutting or etching the recess between the semiconductor units of the semiconductor wafer in step S1920 groove. The recess cuts through or etches through the active circuit layer of the semiconductor wafer. In one embodiment, the grooves are formed using a combination of cutting and etching steps. In step S1930, the protective seal coat material is applied to the grooves between the semiconductor units. In one embodiment, the applying step occurs prior to connecting the external conductive connector to the semiconductor unit. At step S1940, the semiconductor unit is separated by a protective seal coat material. In one embodiment, the method 1900 further includes adhering the film to an outer conductive connector of the semiconductor wafer and applying a protective seal coating material around the outer conductive connector. In another embodiment, the method further includes completely cutting or etching the recess through the semiconductor wafer between the semiconductor units. In another embodiment, the method further includes illuminating and removing the protective seal coating material exposed through the opening in the mask, wherein the opening corresponds to the underlying bond pad of the active circuit layer.

本文中描述的方法與裝置可以施加至晶圓級裝置，如上所述，或者方法和裝置可以施加至重組裝置，如下前述。重組裝置與晶圓形成分離並且經受複數個測試。丟棄在一個或複數個測試中失敗的裝置，重裝通過測試的裝置用於進一步製造。這僅提供繼續處理好裝置的優勢，而不是完全通過處理攜載不好的裝置並在處理結束時丟棄它們。 The methods and devices described herein can be applied to a wafer level device, as described above, or the methods and devices can be applied to a recombination device, as described above. The recombination device is separated from the wafer and is subjected to a plurality of tests. Devices that failed in one or more tests were discarded and the devices that passed the test were reloaded for further manufacturing. This only provides the advantage of continuing to handle the device, rather than completely disposing of the devices that are not well loaded and discarding them at the end of the process.

圖20A顯示黏至黏性載體2020的重組半導體元件2010的3×8陣列。圖20A顯示重組半導體元件2010的矩形陣列。然而，本文中描述的實施方式考慮其他陣列，例如裝置板條、裝置的四方陣列、或者裝置的重組圓形晶圓陣列。圖20A還顯示在裝置的活性表面上具有以球柵陣列(BGA)的複數個焊球2030的重組半導體元件2010。然而，本文中描述的實施方式考慮其他外部互連，例如引腳柵格陣列、圓柱柵格陣列、或者配置用於隨後的焊線接合的複數個接觸焊盤。 Figure 20A shows a 3 x 8 array of recombined semiconductor components 2010 bonded to a viscous carrier 2020. Figure 20A shows a rectangular array of recombined semiconductor components 2010. However, the embodiments described herein contemplate other arrays, such as device slats, quadrilateral arrays of devices, or reconstituted circular wafer arrays of devices. Figure 20A also shows a recombined semiconductor component 2010 having a plurality of solder balls 2030 in a ball grid array (BGA) on the active surface of the device. However, the embodiments described herein contemplate other external interconnects, such as a pin grid array, a cylindrical grid array, or a plurality of contact pads configured for subsequent wire bonding.

圖20B顯示覆蓋焊球2030與有源電路層，以及在重組半導體元件2010中間的保護塗層材料2040，例如模塑料或者環氧樹脂。圖20C顯示暴露焊球2030的下部分。在一種實施方式中，雷射燒蝕被用於暴露焊球2030。近似焊球高度的一半通過模塑料暴露。然而，可以根據期望的最終產品使用其他暴露大小。在另一種實施方式中，膜放置在焊球2030的底表面上。保護塗層材料2040填充在重 組半導體元件2010的膜與有源表面之間，並圍繞單個焊球2030。 Figure 20B shows a cover solder ball 2030 with an active circuit layer, and a protective coating material 2040, such as a molding compound or epoxy, intermediate the recombined semiconductor component 2010. FIG. 20C shows the lower portion of the exposed solder ball 2030. In one embodiment, laser ablation is used to expose solder balls 2030. Approximately half of the height of the solder ball is exposed through the molding compound. However, other exposure sizes can be used depending on the desired end product. In another embodiment, the film is placed on the bottom surface of the solder ball 2030. Protective coating material 2040 is filled in heavy The film of the semiconductor component 2010 is sandwiched between the active surface and the individual solder balls 2030.

圖20D顯示將重組半導體元件2010分離為單個單元2050。單個單元2050的例示包括，但不限於球柵陣列(BGA)或者晶片級封裝(CSP)。分離可以通過鋸切、切割、或者蝕刻的一種或多種發生。分離僅通過模塑料發生，無需切割重組半導體元件2010。如在圖20E中顯示的，單個單元2050從黏性載體2020去除。 FIG. 20D shows the separation of the recombined semiconductor component 2010 into a single unit 2050. Illustrative of a single unit 2050 includes, but is not limited to, a ball grid array (BGA) or a wafer level package (CSP). Separation can occur by one or more of sawing, cutting, or etching. Separation occurs only through the molding compound, without the need to cut the recombined semiconductor component 2010. As shown in Figure 20E, a single unit 2050 is removed from the viscous carrier 2020.

圖20F顯示單個單元2050的剖視圖示。保護塗層材料2040沿著單個單元2050的側面保留並且繼續圍繞拐角表面且向內朝向單個單元2050的周邊焊球2030。這提供密封有源電路層的邊緣以防止分層的優勢，還提供結構支撐至周邊焊球2030。 FIG. 20F shows a cross-sectional view of a single unit 2050. The protective coating material 2040 remains along the sides of the single unit 2050 and continues around the corner surface and inward toward the peripheral solder balls 2030 of the single unit 2050. This provides the advantage of sealing the edges of the active circuit layer to prevent delamination and also provides structural support to the perimeter solder balls 2030.

側壁模塑料的厚度可以依據最後的封裝產品改變。在一種實施方式中，模塑料的側壁厚度在從10μm至90μm的範圍內。在一種實施方式中，模注半導體元件(在去除任何模塑料之前)從裝置的背面至模塑料的頂表面可以近似560μm。通過雷射燒蝕或者其他方法去除的模塑料的量可以是190μm。該量的模塑料去除暴露近似焊球的一半。上述大小僅出於例示性目的，本文中描述的實施方式考慮設計用於具體的最終產品的其他大小。 The thickness of the sidewall molding compound can vary depending on the final packaged product. In one embodiment, the sidewall thickness of the molding compound ranges from 10 μm to 90 μm. In one embodiment, the molded semiconductor component (before removing any molding compound) may be approximately 560 [mu]m from the back side of the device to the top surface of the molding compound. The amount of molding compound removed by laser ablation or other methods may be 190 μm. This amount of molding compound removes approximately half of the exposed solder balls. The above dimensions are for illustrative purposes only, and the embodiments described herein contemplate other sizes designed for a particular end product.

圖21顯示重組半導體元件的焊球黏至黏性載體的一種實施方式。模塑料填充在重組半導體元件之間，以及每個裝置的活性層與黏性載體之間的間隙。圖21顯示模塑料也駐留在重組半導體元件的後非活性表面上。另一種實施方式包括利用膜或者膠帶覆蓋後表面，因此後表面上沒有施加模塑料。圖21進一步顯示黏性載體去除，並且重組半導體元件分離為單個單元。在其他實施方式中，模塑料可以以暴露的裸片模套或者通過壓縮模塑施加。圖22A顯示背表面黏至載體的複數個半導體元件。焊料凸塊嵌入柔性焊盤，因此焊料凸塊的上半部被覆蓋並且焊料凸塊的緊貼著裸片的下半部被暴露用於接收模塑料。在模塑料滲透開放空間並且設定之後，去除裸片模套與柔性焊盤。半導體元件被分離為單個單元。 Figure 21 shows an embodiment in which the solder balls of the recombined semiconductor component are adhered to the viscous carrier. The molding compound is filled between the recombined semiconductor elements and the gap between the active layer of each device and the viscous carrier. Figure 21 shows that the molding compound also resides on the rear inactive surface of the recombined semiconductor component. Another embodiment includes covering the back surface with a film or tape so that no molding compound is applied to the back surface. Figure 21 further shows the removal of the viscous carrier and the separation of the recombined semiconductor components into a single unit. In other embodiments, the molding compound can be applied in an exposed die sleeve or by compression molding. Figure 22A shows a plurality of semiconductor elements having a back surface adhered to a carrier. The solder bumps are embedded in the flexible pads so that the upper half of the solder bumps are covered and the lower half of the solder bumps that are in close proximity to the die are exposed for receiving the molding compound. After the molding compound penetrates the open space and is set, the die sleeve and the compliant pad are removed. The semiconductor component is separated into a single unit.

圖22B顯示與圖22A的步驟類似的步驟，除了在施加裸片模套與柔性焊盤之前施加模塑料接近複數個裝置的中心。圖22A與圖22B的步驟可以施加至晶圓級半導體元件或者施加至重組半導體元件。 Figure 22B shows a similar procedure to the step of Figure 22A except that the molding compound is applied near the center of the plurality of devices prior to application of the die sleeve and the compliant pad. The steps of Figures 22A and 22B can be applied to a wafer level semiconductor component or to a recombined semiconductor device.

本文中描述的實施方式的多用性允許在幾個可能的處理階段進行測試。可以在以晶圓形式的劃片街區封裝之後，在以面板形式的裸片重組與鑄模成型之後，在鑄模成型的面板被分成板條形式，或者作為分離的IC單元的最後測試之後，使用裸片探測器進行測試。由於不同的供應商可以利用不同的測試平臺，所以測試靈活度提供成本節約。 The versatility of the embodiments described herein allows for testing at several possible processing stages. After the diced block in the form of a wafer, after the die reassembly and molding in the form of a panel, the molded panel is divided into slabs, or after the final test as a separate IC unit, the bare is used. The film detector is tested. Test flexibility provides cost savings as different vendors can leverage different test platforms.

圖23是製造半導體封裝的方法2300的流程圖。在步驟S2310，複數個半導體元件以板條格式或陣列格式黏至黏性載體。格式包含相鄰的每對半導體元件之間的間隙。在步驟S2320，模塑料被施加至間隙。模塑料圍繞所有暴露的有源電路邊緣。在步驟S2330，複數個半導體元件通過施加的模塑料分離。 23 is a flow diagram of a method 2300 of fabricating a semiconductor package. In step S2310, the plurality of semiconductor elements are adhered to the viscous carrier in a strip format or an array format. The format includes a gap between each adjacent pair of semiconductor elements. At step S2320, a molding compound is applied to the gap. The molding compound surrounds all exposed active circuit edges. In step S2330, a plurality of semiconductor elements are separated by the applied molding compound.

方法2300還可以包括將外部焊球連接至有源電路層的相應的接觸焊盤，並且在有源電路層上施加模塑料以包圍連接的外部焊球。方法2300還可以包括在有源電路層與施加至外部焊球的底表面的膜之間的有源電路層上施加模塑料，雷射燒蝕施加至外部焊球的底表面的模塑料，通過暴露的裸片模套或者壓模之一將模塑料施加在間隙內並且在有源電路層上，或者在施加至複數個半導體元件的背表面的模塑料上標記複數個半導體元件的步驟的一個或複數個。在一種實施方式中，複數個半導體元件包括重組半導體元件。 Method 2300 can also include attaching external solder balls to respective contact pads of the active circuit layer and applying a molding compound over the active circuit layer to surround the connected external solder balls. The method 2300 can also include applying a molding compound on the active circuit layer between the active circuit layer and the film applied to the bottom surface of the outer solder ball, and laser abating the molding compound applied to the bottom surface of the outer solder ball, through One of the steps of exposing a plurality of semiconductor components to one or more of the exposed die or the stamper, applying the molding compound to the gap and on the active circuit layer, or on the molding compound applied to the back surface of the plurality of semiconductor components Or plural. In one embodiment, the plurality of semiconductor components comprises a recombination semiconductor component.

半導體元件被處理多次並且經過幾個處理及測試程式。傳統的裝置趨向於在接近有源電路層的邊緣形成缺口(chipped-out)區域，尤其當裝置受到撞擊時。該缺口區域趨向於導致電路層與裸片的隨後分層，引起裝置的最終失敗。 The semiconductor components are processed multiple times and pass through several processing and test programs. Conventional devices tend to form a chipped-out region near the edge of the active circuit layer, especially when the device is impacted. This notched area tends to cause subsequent delamination of the circuit layer and the die, causing a final failure of the device.

本文中描述的實施方式提供更堅固的半導體元件。保護邊緣密封劑密封全部在裸片的所有四個側面的周圍的有源電路層的邊緣。保護邊緣密封劑在有源電路層上延伸以 包圍外部連接器，例如焊球。這提供焊球支撐並且保護位於裝置週邊的焊球的額外益處，增加裝置的可靠性。作為減少分層與增加的可靠性的結果，半導體封裝可以容納更大的裸片。作為一個例子，僅出於例示性目的，傳統的半導體封裝可以具有近似5mm x 5mm的裸片。較大尺寸的傳統裸片存在在處理與測試的步驟中出現缺口與分層頻率較高的風險。通過使用本文中描述的實施方式，可以使用8mm x 8mm或者10mm x 10mm的裸片尺寸並且仍然保持最小的分層與缺口，並具有增加的可靠性。使用本文中描述的實施方式的更大裸片也進行要求連接至基板以提供穩定性或者保護，引起成本節約。 Embodiments described herein provide a more robust semiconductor component. The protective edge sealant seals all of the edges of the active circuit layer around all four sides of the die. The protective edge sealant extends over the active circuit layer Enclose an external connector, such as a solder ball. This provides additional benefits to the solder ball support and protects the solder balls located around the device, increasing the reliability of the device. As a result of reduced delamination and increased reliability, semiconductor packages can accommodate larger dies. As an example, a conventional semiconductor package may have a die of approximately 5 mm x 5 mm for illustrative purposes only. Larger sized conventional dies present a higher risk of gaps and stratification in the processing and testing steps. By using the embodiments described herein, a die size of 8 mm x 8 mm or 10 mm x 10 mm can be used and still maintain minimal delamination and gaps with increased reliability. Larger dies using the embodiments described herein also require connection to the substrate to provide stability or protection, resulting in cost savings.

本文中描述的方法與裝置是例示性的並顯示某些實施方式的特徵和步驟。實施方式不局限於任何具體順序或者本文中描述的例示性順序。 The methods and apparatus described herein are illustrative and show the features and steps of certain embodiments. The embodiments are not limited to any specific order or exemplary order described herein.

本文中描述的用於半導體封裝的實施方式可被用於許多施加，包括但不限於網路、移動、無線、可攜帶電子設備、及寬頻。在網路施加中，本文中描述的半導體封裝可被用於多核處理器、智能型處理器、伺服器消息塊(SMB)處理器、加密協同處理器、及安全處理器。在移動、無線施加、及可攜帶施加中，本文中描述的半導體封裝可被用於3G基帶處理器、LTE基帶處理器、移動視訊處理器、移動圖形處理器、施加處理器、觸摸控制器、無線功率、物聯網(IoT)及可佩帶的系統晶片(SoC)、無線視訊、及天線。在寬頻施加中，本文中描述的半導體封裝可被用於電纜機頂盒(STB)、衛星STB、網路協定(IP)STB、地面STB、超高清(HD)處理器、STB圖形處理器、及STB安全處理器。這些裝置和系統可被用於包括但不限於路由器、智慧手機、平板電腦、個人電腦、及例如手錶、鞋子、衣服、及眼鏡的可攜帶設備的產品。在一些實施方式中，本文中描述的裝置與系統可被用於WiFi組合晶片、施加處理器、功率管理晶片、及藍牙晶片。 Embodiments for semiconductor packaging described herein can be used for many applications including, but not limited to, networking, mobile, wireless, portable electronic devices, and broadband. In network application, the semiconductor packages described herein can be used in multi-core processors, smart processors, server message block (SMB) processors, cryptographic co-processors, and security processors. The semiconductor package described herein can be used in 3G baseband processors, LTE baseband processors, mobile video processors, mobile graphics processors, application processors, touch controllers, in mobile, wireless application, and portable applications. Wireless power, Internet of Things (IoT) and wearable system-on-chip (SoC), wireless video, and antennas. The semiconductor package described herein can be used in cable set top boxes (STBs), satellite STBs, network protocol (IP) STBs, terrestrial STBs, ultra high definition (HD) processors, STB graphics processors, and STBs in broadband applications. Security processor. These devices and systems can be used in products including, but not limited to, routers, smart phones, tablets, personal computers, and portable devices such as watches, shoes, clothing, and glasses. In some embodiments, the devices and systems described herein can be used with WiFi combo chips, application processors, power management chips, and Bluetooth chips.

上述討論僅公開並描述例示性實施方式。本技術領域中具有通常知識者會理解的是，在不背離其精神或基本特性的情況下，本公開內容可表現為其他具體的形式。因此， 本實施方式的本公開內容旨在進行說明，而非限制實施方式的範圍以及申請專利範圍。在此包括教導的可容易辨別的任何變體的公開內容部分限定上述申請專利範圍的術語的範圍，從而任何主題都不公開使用。 The above discussion discloses and describes merely exemplary embodiments. It will be understood by those of ordinary skill in the art that the present disclosure may be embodied in other specific forms without departing from the spirit or essential characteristics. therefore, The disclosure of the present embodiments is intended to be illustrative, and not to limit the scope of the embodiments. The disclosure of any variation that can be readily discerned by the teachings herein is intended to define the scope of the terms of the above-mentioned claims, such that any subject matter is not disclosed.

400‧‧‧WLBGA 400‧‧‧WLBGA

410‧‧‧晶圓 410‧‧‧ wafer

420‧‧‧半導體單元 420‧‧‧Semiconductor unit

430‧‧‧焊球 430‧‧‧ solder balls

435‧‧‧活性表面 435‧‧‧active surface

440‧‧‧載帶 440‧‧‧ Carrier tape

450‧‧‧第一切口 450‧‧‧ first incision

Claims (10)

一種半導體封裝，包括：半導體單元，包含有源電路層；複數個焊球連接至前述有源電路層並被配置為連接至相應的外部導電連接器；以及使用保護密封塗層填充前述有源電路層的凹槽邊緣，其中，前述保護密封塗層包含外部晶圓分離表面；以及前述複數個焊球延伸通過前述保護密封塗層的外表面的平面。 A semiconductor package comprising: a semiconductor unit including an active circuit layer; a plurality of solder balls connected to the foregoing active circuit layer and configured to be connected to a corresponding external conductive connector; and filling the foregoing active circuit with a protective sealing coating a groove edge of the layer, wherein the protective seal coating comprises an outer wafer separation surface; and the plurality of solder balls extend through a plane of the outer surface of the protective seal coating. 如請求項1所記載的半導體封裝，其中前述外部晶圓分離表面包括鋸切邊緣、蝕刻邊緣或者雷射改變的邊緣中的一個或複數個。 The semiconductor package of claim 1, wherein the outer wafer separation surface comprises one or more of a saw edge, an etched edge, or a laser-changed edge. 如請求項1所記載的半導體封裝，其中前述保護密封塗層至少部分地覆蓋前述半導體單元的裸片的周邊。 The semiconductor package of claim 1, wherein the protective seal coating at least partially covers a periphery of the die of the semiconductor unit. 如請求項1所記載的半導體封裝，進一步包括焊球外部導電連接器或接合線外部導電連接器。 The semiconductor package as recited in claim 1, further comprising a solder ball external conductive connector or a bond wire external conductive connector. 如請求項1所記載的半導體封裝，進一步包括附加保護密封塗層，係圍繞前述有源電路層上的前述外部導電連接器。 The semiconductor package of claim 1, further comprising an additional protective sealing coating surrounding the aforementioned external conductive connector on the active circuit layer. 如請求項1所記載的半導體封裝，進一步包括附加保護密封塗層，係在前述半導體單元的非活性表面上。 The semiconductor package of claim 1, further comprising an additional protective sealing coating on the inactive surface of the semiconductor unit. 如請求項1所記載的半導體封裝，其中前述保護密封塗層減少或者去除圍繞每個前述半導體單元的密封圈。 The semiconductor package of claim 1, wherein the protective seal coating reduces or removes a seal ring surrounding each of the foregoing semiconductor units. 一種半導體封裝，包括： 半導體單元包含有源電路層；複數個焊球直接設置在前述有源電路層；以及使用保護密封塗層填充前述有源電路層的凹槽邊緣，其中前述保護密封塗層包含外部晶圓分離表面；每個前述複數個焊球延伸通過前述保護密封塗層的外表面的平面；以及每個前述複數個焊球設置在同一個平面。 A semiconductor package comprising: The semiconductor unit includes an active circuit layer; a plurality of solder balls are directly disposed on the active circuit layer; and a groove edge of the active circuit layer is filled with a protective sealing coating, wherein the protective seal coating includes an outer wafer separation surface Each of the plurality of solder balls extends through a plane of the outer surface of the protective seal coating; and each of the plurality of solder balls is disposed in the same plane. 一種製造半導體封裝的方法，包括：將載帶黏至半導體晶圓的非活性表面；在前述半導體晶圓的各半導體單元之間切割或者蝕刻至少一凹槽，其中，前述至少一凹槽切割穿過或者蝕刻穿過前述半導體晶圓的有源電路層；將保護密封塗層施加到前述半導體單元之間的前述至少一凹槽中；其中，複數個焊球設置在同一個平面上並且延伸通過前述保護密封塗層的外表面。 A method of fabricating a semiconductor package, comprising: bonding a carrier tape to an inactive surface of a semiconductor wafer; cutting or etching at least one recess between each semiconductor unit of the semiconductor wafer, wherein the at least one recess is cut through Passing or etching an active circuit layer through the semiconductor wafer; applying a protective sealing coating to the at least one recess between the semiconductor units; wherein the plurality of solder balls are disposed on the same plane and extend through The foregoing protects the outer surface of the seal coat. 如請求項9所記載的製造半導體封裝的方法，進一步包括：將複數個半導體元件以條格式或陣列格式黏至黏性載體，其中前述格式包含相鄰的每對半導體元件之間的間隙；在前述間隙內施加模塑料，其中前述模塑料圍繞暴露的有源電路邊緣；以及通過施加的前述模塑料分離前述複數個半導體元件。 The method of manufacturing a semiconductor package according to claim 9, further comprising: bonding the plurality of semiconductor elements to the adhesive carrier in a strip format or an array format, wherein the format includes a gap between each adjacent pair of semiconductor elements; A molding compound is applied in the aforementioned gap, wherein the molding compound surrounds the exposed active circuit edge; and the plurality of semiconductor elements are separated by the aforementioned molding compound applied.
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