CN114512589A - Photoelectric hybrid packaging structure and manufacturing method thereof - Google Patents
Photoelectric hybrid packaging structure and manufacturing method thereof Download PDFInfo
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- CN114512589A CN114512589A CN202210417726.XA CN202210417726A CN114512589A CN 114512589 A CN114512589 A CN 114512589A CN 202210417726 A CN202210417726 A CN 202210417726A CN 114512589 A CN114512589 A CN 114512589A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 230000003287 optical effect Effects 0.000 claims abstract description 45
- 238000003466 welding Methods 0.000 claims abstract description 30
- 239000011521 glass Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 230000004907 flux Effects 0.000 claims abstract description 10
- 229910000679 solder Inorganic materials 0.000 claims description 33
- 230000005693 optoelectronics Effects 0.000 claims description 23
- 238000005520 cutting process Methods 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 11
- 239000000919 ceramic Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000004904 shortening Methods 0.000 abstract description 2
- 238000012360 testing method Methods 0.000 abstract description 2
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 230000014509 gene expression Effects 0.000 description 3
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
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- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 239000013307 optical fiber Substances 0.000 description 1
- 239000000049 pigment Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/02002—Arrangements for conducting electric current to or from the device in operations
- H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/024—Arrangements for cooling, heating, ventilating or temperature compensation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/58—Optical field-shaping elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0058—Processes relating to semiconductor body packages relating to optical field-shaping elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Led Device Packages (AREA)
Abstract
The invention provides a photoelectric hybrid packaging structure and a manufacturing method thereof, and relates to the field of semiconductor chip packaging test. In the photoelectric hybrid packaging structure, the light guide assembly is embedded in the opening of the second wiring layer and protrudes out of the second wiring layer by a certain height, so that when the photoelectric hybrid packaging structure is welded to a glass substrate, a plurality of welding balls cannot collapse, the welding reliability is guaranteed, and the light guide assembly is protected. Furthermore, the welding flux with the exposed side surface is arranged in the insulating heat conduction block and is directly electrically connected to the welding pad on the side wall of the chip mounting groove of the glass substrate, so that the welding flexibility can be increased, and the shortening of the driving path of the optical chip and the electric chip can be ensured.
Description
Technical Field
The invention relates to the field of semiconductor chip packaging test, in particular to a photoelectric hybrid packaging structure and a manufacturing method thereof.
Background
The optical communication module generally packages an electrical chip and an optical chip into a whole, and the integrated chip is mostly a power type chip in a limited volume, which needs to release a large amount of heat in a short time, so the heat balance problem needs to be solved. Further, to the optical path of the optical chip. It is necessary to arrange a light guide member at a position where light is emitted or received to achieve collimation of light and reliability of light propagation.
Disclosure of Invention
Based on solving the above problems, the present invention provides a method for manufacturing an optoelectronic hybrid package structure, comprising the following steps:
(1) sequentially forming an optical chip layer, a first wiring layer, a battery cell layer and a radiator on a carrier;
(2) removing the carrier, and forming a second wiring layer on the exposed lower surface of the optical chip layer by taking the radiator as a support body;
(3) forming a plurality of openings in the second wiring layer, and inserting an optical waveguide assembly into the openings, wherein the thickness of the optical waveguide assembly is greater than that of the second wiring layer, so that a part of the optical waveguide assembly protrudes out of the lower surface of the second wiring layer;
(4) cutting to be single, forming a plurality of photoelectric packaging pieces, and arranging solder balls on the lower surface of a second wiring layer of each photoelectric packaging piece;
(5) providing a glass substrate, wherein the glass substrate is provided with a chip mounting groove, embedding a photoelectric packaging piece into the chip mounting groove, and enabling the welding ball to be jointed with a first welding pad on the bottom surface of the chip mounting groove, and the bottom of the light guide component is jointed with the bottom surface of the chip mounting groove.
Further, the optical chip layer comprises a plurality of optical chips and a plurality of first insulating heat conduction blocks around the optical chips, and a first filling layer is arranged between the optical chips and the first insulating heat conduction blocks; the battery cell sheet layer comprises a plurality of electric chips and a plurality of second insulating heat-conducting blocks around the electric chips, and a second filling layer is arranged between the electric chips and the second insulating heat-conducting blocks.
Further, at least one first insulating heat conduction block is provided with a first groove facing the second wiring layer, first welding materials are filled in the first groove, and the first welding materials are electrically connected with the second wiring layer; at least one second insulating heat conduction block is provided with a second groove facing the first wiring layer, second welding materials are filled in the second groove, and the second welding materials are electrically connected with the first wiring layer.
Further, in step (4), the cutting specifically includes: and cutting along a cutting channel, wherein the cutting channel penetrates through at least parts of the first and second insulating heat conduction blocks and the first and second grooves, and the side surface of the photoelectric packaging piece is exposed out of the first welding flux and the second welding flux.
Furthermore, a plurality of second bonding pads are arranged on the side wall of the chip mounting groove, in the step (5), the side surface of the photoelectric packaging piece is attached to the side wall, and the side surfaces of the first welding flux and the second welding flux face the plurality of second bonding pads in a one-to-one correspondence manner.
Further, the method also comprises the step (6): ablating the first and second solders with a laser such that the first and second solders are electrically connected to the plurality of second pads, respectively.
Further, the method also comprises the step (7): and filling a third filling layer in the chip mounting groove.
Furthermore, the bottom of the first groove is provided with a third groove with a deeper depth, the bottom of the second groove is provided with a fourth groove with a deeper depth, and the cutting path penetrates through the third groove and the fourth groove.
Furthermore, the insulating heat conduction block is of a square LTCC ceramic block structure.
The invention also additionally provides an optoelectronic hybrid packaging structure, which is formed by the manufacturing method of the optoelectronic hybrid packaging structure.
The invention has the following beneficial effects: the light guide component is embedded in the opening of the second wiring layer and protrudes out of the second wiring layer by a certain height, so that the plurality of solder balls cannot collapse when being welded to the glass substrate, the welding reliability is ensured, and the light guide component is protected. Furthermore, the welding flux with the exposed side surface is arranged in the insulating heat conduction block and is directly electrically connected to the welding pad on the side wall of the chip mounting groove of the glass substrate, so that the welding flexibility can be increased, and the shortening of the driving path of the optical chip and the electric chip can be ensured.
Drawings
FIG. 1 is a cross-sectional view of an optoelectronic package on a carrier;
FIG. 2 is a cross-sectional view taken along line A1A2 of FIG. 1;
FIG. 3 is a cross-sectional view of the optoelectronic package of the present invention without singulation;
FIG. 4 is a cross-sectional view of the optoelectronic package of the present invention after singulation;
FIG. 5 is a cross-sectional view of the optical chip layer of FIG. 4;
FIG. 6 is a cross-sectional view of an optoelectronic package of the present invention embedded in a glass substrate;
fig. 7 is a cross-sectional view of the final opto-electronic hybrid package structure of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without inventive step, are within the scope of protection of the disclosure.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
Referring to fig. 1 and fig. 2, a method for manufacturing a hybrid optoelectronic package structure according to an embodiment of the present invention includes sequentially forming an optical chip layer 11, a first wiring layer 12, a cell layer 13, and a heat sink 14 on a carrier 10 from bottom to top. The carrier 10 may be a rigid stainless steel material, a ceramic material, a silicon material, or the like. The optical chip layer 11 includes a plurality of optical chips 15 and a plurality of first insulating thermal conductive blocks 16 surrounding the plurality of optical chips 15, and the optical chips 15 may be emitting optical chips or receiving optical chips, such as PIN diodes.
As shown in fig. 2, each of the first insulating and thermally conductive blocks 16 may have a different size. At least one of the first insulating and heat-conducting blocks 16 has a first groove 17 facing the carrier, the first groove 17 crossing the cutting street C1C 2. The bottom of the first groove 17 also has a deeper second groove 18, the second groove 18 also crossing the cutting lane C1C 2. The first groove 17 and the second groove 18 are filled with a first solder 19, and the first solder 19 may be a gold-tin solder, a tin-gold solder, or the like. The first insulating heat-conducting block 16 may be a square LTCC ceramic block structure, which has good heat-conducting property, and can conveniently form the first groove 17 and the second groove 18. Further, a first filling layer 20 is provided between the optical chip 15 and the first insulating heat-conductive block 16, and the first filling layer 20 may be a heat-cured transparent resin material.
The optical chip layer 11 has a flat upper surface, which may be formed by a CMP process. The first wiring layer 12 is formed on the optical chip layer 11, and may include a plurality of dielectric layers and a wiring pattern (not shown) interposed between the dielectric layers. The top surface of the first wiring layer 12 has bonded conductive portions to which the electrical chips 21 of the cell sheet layer 13 are electrically connected by solder balls.
The cell sheet layer 13 includes a plurality of electrical chips 21 and a plurality of second insulating heat-conducting blocks 22 surrounding the plurality of electrical chips 21. The electrical chip 21 may be a control chip or an optical adjusting chip, etc., wherein the second insulating and thermal conductive block 22 is made of the same material and has the same structure as the first insulating and thermal conductive block 16, and has a third groove 23 facing the first wiring layer 12 and a fourth groove 24 deeper at the bottom of the third groove 23, and likewise, the third groove 23 and the fourth groove 24 both cross the scribe line C1C2, and the third groove 23 and the fourth groove 24 are filled with a second solder 25, wherein the second solder 25 is physically and electrically connected to the conductive portion of the first wiring layer 12. A second filling layer 26 is provided between the electric chip 21 and the second insulating and heat-conducting block 22, and the second filling layer 26 is made of the same material as the first filling layer 20.
The cell sheet layer 13 also has a flat upper surface, and is also formed by a CMP process. The heat sink 14 is fixed on the electrical chip 13, the heat sink 14 may be a heat dissipation metal sheet, a heat dissipation fin or other heat sink structure, and the heat sink 14 is attached to the electrical chip 21 and the plurality of second insulating heat conduction blocks 22 to achieve rapid heat transfer upward.
Referring again to fig. 2, the first insulating and heat-conducting blocks 15 include two elongated insulating and heat-conducting blocks disposed on two opposite sides of the optical chips 16 to reinforce the strength of the optical chip layer 11. Similarly, the second insulating and heat-conducting block 15 has two elongated insulating and heat-conducting blocks disposed on two opposite sides of the plurality of electric chips 21.
Referring next to fig. 3, the carrier 10 is removed to expose the lower surface of the photonic chip layer 11. A second wiring layer 27 is formed on the lower surface of the optical chip layer, and the second wiring layer 27 may include a dielectric layer and a wiring pattern alternately arranged, and the wiring pattern thereof is electrically connected to the optical chip 15.
Then, a corresponding opening 28 is formed in the second wiring layer 27 directly below the plurality of optical chips 15, and an optical waveguide member 29 is embedded in the opening 28, the thickness of the optical waveguide member 29 being larger than that of the second wiring layer 27, so that a part of the optical waveguide member 29 protrudes from the lower surface of the second wiring layer 27. The light guide member 29 may be an optical fiber, an optical coupler, or the like, which is fixedly attached by an adhesive on the side wall of the opening 28.
A plurality of solder balls 30 are formed by ball-bonding on the lower surface of the second wiring layer 10, and the plurality of solder balls 30 are used as lead-out portions of the optoelectronic package. And a plurality of solder balls 30 are wrapped around the light guide assembly 29.
Singulation is performed by cutting along the cutting path C1C2 to obtain a plurality of singulated optoelectronic packages, as shown in fig. 4 and 5. The cut penetrates the first to fourth grooves so that the side surfaces of the optoelectronic package expose the first solder 19 and the second solder 25. The deeper second and fourth grooves 18 and 24 ensure that a sufficient amount of solder is exposed laterally, and that a portion of the solder is saved and the heat transfer efficiency of the insulating and heat-conducting block is ensured.
Referring to fig. 5, a glass substrate 31 is provided, the glass substrate 31 having a chip mounting groove 32 and a wiring structure (not shown) thereon, which is led out through a plurality of first pads 33 and second pads 34. Wherein, a plurality of first pads 33 are formed on the bottom of the chip mounting groove 32, and a plurality of second pads 34 are formed on the side wall of the chip mounting groove 32.
The photoelectric packaging piece is installed in the chip installation groove 32 in an embedded mode, wherein the solder balls 30 are welded on the first bonding pads 33 through a reflow process, and at the moment, the bottom of the light guide assembly 29 is attached to the bottom surface of the chip installation groove 32, so that the heights of the solder balls 30 can be guaranteed, the solder balls 30 are prevented from collapsing, and the solder balls are further attached to the light guide assembly 29. Meanwhile, the side surfaces of the optoelectronic package are attached to the side walls of the chip mounting groove 32, and the side surfaces of the first solder 19 and the second solder 25 are correspondingly faced to the plurality of second pads 34 one by one, as shown in fig. 6.
Specifically, the first solder 19 and the second solder 25 are disposed offset from the corresponding second pads 34, wherein the tips of the first solder 19 and the second solder 25 are higher than the tips of the corresponding second pads 34, so that the first solder 19 and the second solder 25 are electrically connected to the plurality of second pads 34, respectively, by laser ablation through the glass substrate 31, as shown in fig. 7.
Finally, the chip mounting groove 32 is filled with a non-light-transmitting resin material, and the resin material 35 may be doped with a dye or a pigment. The non-light-transmitting resin material 35 can prevent other light from affecting the light guide member 29, and ensure the reliability of light transmission.
Finally, the optoelectronic hybrid package structure shown in fig. 1 is obtained, wherein C1C2 represents a cutting line, thereby realizing the singulation. The expressions "exemplary embodiment," "example," and the like, as used herein, do not refer to the same embodiment, but are provided to emphasize different particular features. However, the above examples and exemplary embodiments do not preclude their implementation in combination with features of other examples. For example, even in a case where a description of a specific example is not provided in another example, unless otherwise stated or contrary to the description in the other example, the description may be understood as an explanation relating to the other example.
The terminology used in the present invention is for the purpose of illustrating examples only and is not intended to be limiting of the invention. Unless the context clearly dictates otherwise, singular expressions include plural expressions.
While example embodiments have been shown and described, it will be apparent to those skilled in the art that modifications and changes may be made without departing from the scope of the invention as defined by the claims.
Claims (10)
1. A manufacturing method of an optoelectronic hybrid package structure is characterized by comprising the following steps:
(1) sequentially forming an optical chip layer, a first wiring layer, a battery cell layer and a radiator on a carrier;
(2) removing the carrier, and forming a second wiring layer on the exposed lower surface of the optical chip layer by taking the radiator as a support body;
(3) forming a plurality of openings in the second wiring layer, and inserting an optical waveguide assembly into the openings, wherein the thickness of the optical waveguide assembly is greater than that of the second wiring layer, so that a part of the optical waveguide assembly protrudes out of the lower surface of the second wiring layer;
(4) cutting to be single, forming a plurality of photoelectric packaging pieces, and arranging solder balls on the lower surface of a second wiring layer of each photoelectric packaging piece;
(5) providing a glass substrate, wherein the glass substrate is provided with a chip mounting groove, embedding a photoelectric packaging piece into the chip mounting groove, and enabling the welding ball to be jointed with a first welding pad on the bottom surface of the chip mounting groove, and the bottom of the light guide component is jointed with the bottom surface of the chip mounting groove.
2. The method of manufacturing an optoelectronic hybrid package structure of claim 1, wherein: the optical chip layer comprises a plurality of optical chips and a plurality of first insulating heat conduction blocks around the optical chips, and a first filling layer is arranged between the optical chips and the first insulating heat conduction blocks; the battery cell sheet layer comprises a plurality of electric chips and a plurality of second insulating heat-conducting blocks around the electric chips, and a second filling layer is arranged between the electric chips and the second insulating heat-conducting blocks.
3. The method for manufacturing the optoelectronic hybrid package structure of claim 2, wherein: at least one first insulating heat conduction block is provided with a first groove facing the second wiring layer, first welding materials are filled in the first groove, and the first welding materials are electrically connected with the second wiring layer; at least one second insulating heat conduction block is provided with a second groove facing the first wiring layer, second welding materials are filled in the second groove, and the second welding materials are electrically connected with the first wiring layer.
4. The method of manufacturing an optoelectronic hybrid package structure of claim 3, wherein: in step (4), the cutting specifically comprises: and cutting along a cutting channel, wherein the cutting channel penetrates through at least parts of the first and second insulating heat conduction blocks and the first and second grooves, and the side surface of the photoelectric packaging piece is exposed out of the first welding flux and the second welding flux.
5. The method for manufacturing the optoelectronic hybrid package structure of claim 4, wherein: and (5) attaching the side surface of the photoelectric packaging piece to the side wall, wherein the side surfaces of the first welding flux and the second welding flux correspondingly face the second welding pads one to one.
6. The method of manufacturing an optoelectronic hybrid package structure of claim 5, wherein: further comprising the step (6): ablating the first and second solders with a laser such that the first and second solders are electrically connected to the plurality of second pads, respectively.
7. The method of manufacturing an optoelectronic hybrid package structure of claim 6, wherein: further comprising the step (7): and filling a third filling layer in the chip mounting groove.
8. The method for manufacturing the optoelectronic hybrid package structure of claim 4, wherein: the bottom of the first groove is provided with a third groove with deeper depth, the bottom of the second groove is provided with a fourth groove with deeper depth, and the cutting path penetrates through the third groove and the fourth groove.
9. The method for manufacturing the optoelectronic hybrid package structure of claim 1, wherein: the first insulating heat conduction block and the second insulating heat conduction block are of square LTCC ceramic block structures.
10. An opto-electric hybrid package structure formed by the method of manufacturing an opto-electric hybrid package structure according to any one of claims 1 to 9.
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| CN202210417726.XA CN114512589B (en) | 2022-04-21 | 2022-04-21 | Photoelectric hybrid packaging structure and manufacturing method thereof |
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| CN202210417726.XA CN114512589B (en) | 2022-04-21 | 2022-04-21 | Photoelectric hybrid packaging structure and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115084046A (en) * | 2022-07-20 | 2022-09-20 | 威海市泓淋电力技术股份有限公司 | Hybrid integrated semiconductor package and manufacturing method thereof |
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