CN104037146B - Encapsulating structure and method for packing - Google Patents
Encapsulating structure and method for packing Download PDFInfo
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- CN104037146B CN104037146B CN201410291048.2A CN201410291048A CN104037146B CN 104037146 B CN104037146 B CN 104037146B CN 201410291048 A CN201410291048 A CN 201410291048A CN 104037146 B CN104037146 B CN 104037146B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
Abstract
A kind of encapsulating structure and method for packing, wherein, encapsulating structure includes: image sensor chip, described image sensor chip have first and with described first relative second, image sensor chip the first mask has photo-sensitive cell and the first pad around described photo-sensitive cell, having metal column in image sensor chip, and one end of metal column electrically connects with the first pad, the other end relative with described one end flushes with image sensor chip the second face；Signal processing chip, signal processing chip have the 3rd and with described 3rd relative fourth face, signal processing chip the 3rd mask has the second pad, and described signal processing chip the 3rd and second fixed engagement of image sensor chip, and described second pad electrically connects with metal column；Run through the through hole of described signal processing chip fourth face, and described through hole exposes the second bond pad surface.The present invention, by being provided separately image sensor chip and signal processing chip, improves encapsulation performance.
Description
Technical field
The present invention relates to semiconductor packaging, particularly to a kind of encapsulating structure and method for packing.
Background technology
Image sensing chip is a kind of chip can experienced extraneous light and convert thereof into the signal of telecommunication.?
After image sensing chip manufacturing completes, then by image sensing chip is carried out a series of packaging technology, from
And form packaged image sensor, various for such as digital camera, DV etc.
Electronic equipment.
In prior art, image sensing chip is by image sensing (CIS, Contact Image Sensor)
Unit and signal processing (DSP, Digital Signal Processor) unit are dimerous, same
Arranging image sensing cell and signal processing unit on chip block, wherein, image sensing cell is used for simultaneously
Receiving optical signal and be converted into the signal of telecommunication, signal processing unit is at the signal of telecommunication converting optical signal
Reason.
But, in prior art, image sensing cell and signal processing unit are set on one chip
Time, the encapsulating structure performance of chip design difficulty and formation has much room for improvement.
Summary of the invention
The problem that the present invention solves is to provide a kind of encapsulating structure and method for packing, reduces packaging technology difficult
Degree, improves encapsulation performance simultaneously.
For solving the problems referred to above, the present invention provides a kind of encapsulating structure, including: image sensor chip, institute
State image sensor chip have first and with described first relative second, described image sensing
Chip first side has photo-sensitive cell and the first pad around described photo-sensitive cell, described image sensing core
There is in sheet metal column, and one end of described metal column electrically connects with the first pad, relative with described one end
The other end flush with image sensor chip the second face；Signal processing chip, described signal processing chip has
Have the 3rd and with described 3rd relative fourth face, described signal processing chip the 3rd mask has second
Pad, and described signal processing chip the 3rd and second fixed engagement of image sensor chip, described the
Two pads electrically connect with metal column；Run through the through hole of described signal processing chip fourth face, and described through hole
Expose the second bond pad surface.
Optionally, it is formed with adhesion layer between described image sensor chip and signal processing chip.
Optionally, also include: being positioned at described second pad and the opening of adhesion layer, open bottom is sudden and violent
Expose metal column surface, and described opening mutually runs through with through hole.
Optionally, also include: fill the conductive layer of full described opening, and described conductive layer and metal column with
And second pad contact.
Optionally, also include: be positioned at through-hole side wall and the insulating barrier of signal processing chip fourth face；Position
In the metal redistribution layer of surface of insulating layer, and described metal redistribution layer is also located at conductive layer surface；Position
Solder-bump in the metal redistribution layer surface of described signal processing chip fourth face.
Optionally, also include: fill the solder-bump of full described through hole, described solder-bump and conductive layer
Contact, and described solder-bump top is higher than signal processing chip fourth face.
Optionally, being formed with insulating barrier between described solder-bump and through-hole side wall, described insulating barrier is also
It is covered in signal processing chip fourth face.
Optionally, described signal processing chip the 3rd directly contacts with image sensor chip second, institute
State the second bond pad surface to contact with metal column surface.
Optionally, also include: be positioned at described through-hole side wall and the insulating barrier of signal processing chip fourth face；
It is positioned at the metal redistribution layer of described via bottoms and surface of insulating layer；It is positioned at described signal processing chip
The solder-bump on the metal redistribution layer surface of fourth face.
Optionally, filling the solder-bump of full described through hole, described solder-bump contacts with the second pad,
And described solder-bump top is higher than signal processing chip fourth face.
Optionally, also include: be positioned at the substrate of image sensor chip first.
Optionally, it is also formed with adhesive-layer between described substrate and image sensor chip first.
The present invention also provides for a kind of method for packing, including: image sensing wafer, described image sensing are provided
Wafer have first and with described first relative second, described image sensing wafer the first mask
There are some photo-sensitive cells and the first pad around described photo-sensitive cell, have in described image sensing wafer
Metal column, and described metal column one end electrically connects with the first pad, the other end relative with described one end with
Image sensing wafer the second face flushes；Thering is provided signal processing wafer, described signal processing wafer has the 3rd
Face and with described 3rd relative the 3rd, and described signal processing wafer the 3rd mask has some second
Pad；By described image sensing wafer second and the 3rd fixed engagement of signal processing wafer, make second
Pad is corresponding with the position of metal column；Described second pad is electrically connected with metal column；Formation runs through institute
State the through hole of signal processing wafer fourth face, and described through hole exposes the second bond pad surface；Cutting is described
Signal processing wafer and image sensing wafer, form the encapsulating structure of some single, described encapsulating structure
Including signal processing chip and image sensor chip.
Optionally, become adhesion layer at described image sensing wafer second or signal processing wafer third surface shape,
By described adhesion layer by image sensing wafer second and the 3rd fixed engagement of signal processing wafer.
Optionally, the method using some glue, plastic roll or print glue forms described adhesion layer.
Optionally, forming opening in described second pad and adhesion layer, described open bottom exposes
Metal column surface, and described opening mutually runs through with through hole.
Optionally, the processing step forming described opening includes: described signal processing wafer fourth face,
Via bottoms and sidewall form insulating barrier；Etching removes the insulating barrier being positioned at via bottoms, continues etching position
In the second pad and the adhesion layer of via bottoms, until exposing metal column surface, at the second pad and
Opening is formed in adhesion layer.
Optionally, using Radium art to form described opening, Radium art parameter is: frequency is 10kHZ
To 200kHZ, power is 0.5watts to 5watts, and spot size is 50 μm to 150 μm, and hot spot moves
Dynamic speed is 100mm/sec to 300mm/sec, and number of repetition is 1 to 10 time.
Optionally, the conductive layer filling full described opening is formed, by conductive layer by the second pad and metal
Post electrically connects.
Optionally, further comprise the steps of: formation solder-bump, and solder-bump electrically connects with conductive layer.
Optionally, the processing step forming described conductive layer and solder-bump includes: is formed and fills full gate
The conductive layer of mouth, forms metal redistribution layer, and the redistribution of described metal at described surface of insulating layer simultaneously
Layer is also located at conductive layer surface；Formed on the metal redistribution layer surface of described signal processing wafer fourth face
Solder-bump.
Optionally, the processing step forming described conductive layer and solder-bump includes: is formed and fills full institute
State the conductive layer of opening；Form the solder-bump filling full described through hole, and described solder-bump top is high
In signal processing wafer fourth face.
Optionally, by Direct Bonding technique, by image sensing wafer second and signal processing wafer the
Three fixed engagement, directly contact electrical connection by described second pad with metal column surface.
Optionally, further comprise the steps of: in described signal processing wafer fourth face, through-hole side wall formation insulation
Layer；Forming metal redistribution layer at described surface of insulating layer, described metal redistribution layer is also located at the bottom of through hole
Portion；Solder-bump is formed on the metal redistribution layer surface of described signal processing wafer fourth face.
Optionally, further comprise the steps of: and form the solder-bump filling full described through hole, and described welding is convex
Play top higher than signal processing wafer fourth face.
Optionally, at first formation substrate of described image sensing wafer.
Optionally, between described substrate and image sensing wafer, adhesive-layer is formed.
Optionally, spin coating process is used to cover liquid glass in image sensing wafer the first topcoating, at figure
As sensing first formation substrate of wafer.
Compared with prior art, technical scheme has the advantage that
The embodiment of the present invention provides the encapsulating structure that a kind of structural behaviour is superior, image sensor chip first
There is photo-sensitive cell and the first pad around described photo-sensitive cell, in described image sensor chip, there is gold
Belong to post, and described metal column one end electrically connects with the first pad, the other end relative with described one end and figure
As sensing chip the second face flushes；Signal processing chip the 3rd is fixing with image sensor chip second to be connect
Closing, signal processing chip the 3rd mask has the second pad, and described second pad electrically connects with metal column,
So that the image sensor chip in encapsulating structure electrically connects with signal processing chip；Run through at described signal
The through hole of reason chip fourth face, and described through hole exposes the second bond pad surface, described in expose second
Bond pad surface is for electrically connecting with external circuit, so that encapsulating structure electrically connects with external circuit.This
In bright encapsulating structure, image sensor chip and signal processing chip are oppositely arranged, image sensing core
Between sheet and signal processing chip, the restriction by the other side is little, therefore at image sensor chip and signal
Reason chip all can obtain optimal performance, improves encapsulation performance.
Simultaneously as image sensor chip and signal processing chip be not disposed on same chip, relatively
For prior art, the area of the image sensor chip of the embodiment of the present invention is less, therefore, and image sensing
The design cost of chip reduces, so that the low cost of encapsulating structure.Further, due to image sensing core
Sheet is provided separately with signal processing chip, image sensor chip and signal processing chip can in any combination,
Encapsulating structure is made to have higher motility.
Further, the embodiment of the present invention has in the second pad and adhesion layer opening, open bottom
Expose metal column surface, and described opening mutually runs through with through hole；Fill the conductive layer of full gate mouth, and
Described conductive layer contacts with metal column and the second pad, by described conductive layer make the second pad and
Metal column electrically connects, thus realizes the purpose that signal processing chip electrically connects with image sensor chip.Described
Adhesion layer improves the adhesiveness between image sensor chip and signal processing chip, thus improves encapsulating structure
Reliability.
Further, the embodiment of the present invention is provided with substrate, described substrate in image sensor chip the first face
Play support signal processing chip and the effect of image sensor chip, improve signal processing chip and figure
As the mechanical strength of sensing chip, thus improve the reliability of encapsulating structure further.
The embodiment of the present invention additionally provides a kind of method for packing, it is provided that image sensing wafer, at described image
Sensing wafer the first mask has the first pad of photo-sensitive cell and Ambience optical element, and described image sensing is brilliant
There is in circle metal column, and described metal column one end electrically connects with the first pad, relative with described one end
The other end flushes with image sensing wafer the second face；Signal processing wafer, described signal processing wafer are provided
3rd mask has some second pads；By described image sensing wafer second and signal processing wafer the 3rd
Face fixed engagement, makes the second pad corresponding with the position of metal column；By described second pad and metal column
Electrical connection；Form the through hole running through described signal processing wafer fourth face, and described through hole exposes second
Bond pad surface；Cut described signal processing wafer and image sensing wafer, form the encapsulation of some single
Structure, described encapsulating structure includes signal processing chip and image sensor chip.The present invention will be by scheming
As sensing wafer and signal processing wafer fixed engagement, and the mode that the second pad electrically connects with metal column,
Realize the electrical connection between image sensing wafer and signal processing wafer；Avoid arranging figure on one piece of wafer
As sensing chip and the required arrangement interconnection problems considered of signal processing chip so that in image sensing wafer
Image sensor chip there is optimal performance, the signal processing chip that synchronous signal processes in wafer has
Optimal performance, thus improve the encapsulation performance of formation.
Simultaneously as examine needed for avoiding arranging image sensor chip and signal processing chip on one piece of wafer
The arrangement interconnection problems considered, therefore reduces wafer design difficulty, thus reduces packaging technology difficulty；
Further, it is not disposed in same wafer due to image sensor chip and signal processing chip, it is to avoid at image
Reserving arrangement space for signal processing chip in sensing wafer, therefore the embodiment of the present invention reduces image biography
The area of sense wafer, thus reduce packaging cost.
Further, the embodiment of the present invention is brilliant with signal processing by image sensing wafer second by adhesion layer
The 3rd fixed engagement of circle, improves the adhesiveness between image sensing wafer and signal processing wafer, from
And improve the reliability of the encapsulating structure of formation.
Accompanying drawing explanation
Fig. 1 to Figure 13 is the cross-sectional view of one embodiment of the invention encapsulation process；
Figure 14 to Figure 17 is the cross-sectional view of another embodiment of the present invention encapsulation process.
Detailed description of the invention
From background technology, the existing chip package including image sensing cell and signal processing unit
Difficulty is big, and the performance of the encapsulating structure formed has much room for improvement.
It has been investigated that, in prior art, generally image sensing cell and signal processing unit are encapsulated
On the same chip.General, chip is acquisition after cutting crystal wafer, and therefore image is passed by prior art
Sense chip and signal processing chip are produced in same wafer, and described wafer can be described as image sensing wafer,
Signal processing chip is produced in image sensing wafer by prior art.
In prior art, image sensor chip should be formed in image sensing wafer and formed again at signal
Reason chip, needs to consider the arrangement between image sensor chip and signal processing chip and interconnection, this will lead
The difficulty causing chip manufacturing process and packaging technology increases；Simultaneously as the cost of image sensing wafer
Height, after signal processing chip being arranged in image sensing wafer, in order to consider with signal processing chip it
Between interconnection, the area of image sensing wafer will certainly be increased, cause chip manufacturing cost and encapsulation work
Skill cost is greatly increased；Further, owing to forming signal processing chip and image sensing on same wafer
During chip, in order to consider arrangement between the two and interconnection, signal processing chip and image sensing core
Sheet is mutually restricted so that signal processing chip and image sensor chip are difficult to reach optimal performance,
Thus result in the poor-performing of encapsulating structure.
The above analysis understands, if image sensing cell and signal processing unit being peeled away, forms two
(image sensing wafer and signal processing wafer, wherein, image sensing wafer is used for shape to individual single wafer
Becoming image sensor chip, signal processing wafer is used for forming signal processing chip), the most again by two the most individually
Wafer level packaging in same encapsulating structure, then then can solve that encapsulation difficulty is big and encapsulation performance is poor
Problem,
Meanwhile, if peeled away by two parts, form two single wafers, then image sensor chip
With signal processing chip can combination in any, for relatively conventional encapsulating structure, motility has the biggest
Improve.And when making image sensing wafer, it is not necessary to reserve arrangement space for signal processing chip, because of
It is smaller that this image sensing wafer can do, thus saves packaging technology cost.
To this end, the present invention provides a kind of encapsulating structure, including: image sensor chip, described image sensing
Chip have first and with described first relative second, described image sensor chip first
There is photo-sensitive cell and the first pad around described photo-sensitive cell, in described image sensor chip, there is gold
Belong to post, and one end of described metal column electrically connect with the first pad, the other end relative with described one end and
Image sensor chip the second face flushes；Signal processing chip, described signal processing chip have the 3rd and
With described 3rd relative fourth face, described signal processing chip the 3rd mask has the second pad, and institute
State signal processing chip the 3rd and second fixed engagement of image sensor chip, described second pad and gold
Belong to post electrical connection；Run through the through hole of described signal processing chip fourth face, and described through hole exposes second
Bond pad surface.Present invention reduces the difficulty of interconnection of arranging between image sensor chip and signal processing chip
Degree, thus reduce packaging technology difficulty；And it is provided separately image sensor chip and signal processing chip,
Make image sensor chip and signal processing chip be respectively provided with optimal performance, thus improve encapsulation performance.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.
Fig. 1 to Figure 13 is the structural representation of one embodiment of the invention encapsulation process.
Refer to Fig. 1, it is provided that image sensing wafer 100.
Described image sensing wafer 100 includes some chip areas arranged in arrays and is positioned at chip area
Between Cutting Road centrage 110, there is in each chip area an image sensor chip, each
Image sensor chip is correspondingly formed an encapsulating structure.Follow-up when cutting image sensing wafer 100, edge
Described Cutting Road centrage 110 and image sensing wafer 100 is cut into several image sensor chips.
In the present embodiment, due to be formed without in image sensing wafer 100 signal processing unit (or letter
Number process chip), it is not necessary to consider and signal processing unit between arrangement interconnection problems, therefore image sensing
Image sensor chip in wafer 100 has optimal performance；Further, image sensing wafer 100 is not required to
Signal processing chip to be reserves arrangement space, therefore, compared with prior art, and image sensing wafer 100
The area of interior image sensor chip is little many.Compared with prior art, for providing the figure of equal number
As, for sensing chip, in the present embodiment, the area of image sensing wafer 100 is little many, thus reduces
Process costs.
Described image sensing wafer 100 have first and with described first relative second, described
First image sensing wafer 100 surface being to have photo-sensitive cell 101 and the first pad 102, described
Second is pending thinning and follow-up and signal processing wafer fixed engagement surface.
First mask of described image sensing wafer 100 chip area has some photo-sensitive cells 101 and cincture
First pad 102 of described photo-sensitive cell 101.It is formed with image sensor list in described photo-sensitive cell 101
Unit and the associated circuit being connected with image sensor unit, utilize described image sensor unit by the external world
Light receiver is also converted into electrical signal, by described associated circuit, electrical signal passes to the first pad
102, recycle the first pad 102 and the metal redistribution layer being subsequently formed, solder-bump by electrical signal
Send other circuit to.General, described photo-sensitive cell 101 top is higher than the first pad 102 top.
In the present embodiment, for the ease of wiring, photo-sensitive cell 101 is positioned at the centre position of chip area,
First pad 102 is positioned at the marginal position of chip area, the follow-up position in described first pad 102 correspondence
Put and form the through hole running through described image sensing wafer 100 thickness, utilize through hole to will be located in image sensing brilliant
First pad 102 of circle 100 first is electrically connected with the signal processing wafer of follow-up offer.
It should be noted that in other embodiments, the position of the first pad and photo-sensitive cell can basis
The requirement of actual process is adjusted flexibly.
In the present embodiment, the first pad 102 of different chip areas is be independently arranged；Real at other
Execute in example, the first pad being connected can be formed at adjacent chip area, the first pad i.e. formed across
More Cutting Road region, this is because: Cutting Road region can be cut after packaging is accomplished and hold, described leap
First pad in Cutting Road region is cut to be opened, and does not interferes with the electric property of encapsulating structure.
After forming the first pad 102 and photo-sensitive cell 101, further comprise the steps of: and pass at described image
First formation of sense wafer 100 chip area is by described first pad 102 and photo-sensitive cell 101 electricity
The metal interconnection structure connected.
There is in described image sensing wafer 100 metal column 103, described metal column 103 one end and the first weldering
Dish 102 electrically connects, and the other end relative with described one end is positioned at image sensing wafer 100, and described
Between metal column 103 other end and image sensing wafer 100 second, there is a certain distance, described gold
Belonging to post 103 is the medium between follow-up connection image sensing wafer 100 and signal processing chip.
Refer to Fig. 2, at 100 first formation substrates 105 of described image sensing wafer.
In the present embodiment, the size of described substrate 105 is equivalently-sized with image sensing wafer 100.
Described substrate 105 provides a supporting role for image sensing wafer 100, improves image sensing wafer 100
Mechanical strength, prevent image sensing wafer 100 in the potting process such as follow-up thinning etching send out
Raw splintering problem；Described substrate 105 also signal processing wafer for follow-up offer provides a supporting role.
The material of described substrate 105 is unorganic glass, lucite, silicon, IR glass or AR glass.
If follow-up after forming encapsulating structure, photo-sensitive cell 101 needs to receive ambient, and ambient passes through
Described substrate 105, makes photo-sensitive cell 101 receive ambient smoothly, then substrate 105 has the property of printing opacity
Energy
In the present embodiment, the material of described substrate 105 is solid-state like unorganic glass.In order to improve substrate
Adhesiveness between 105 and image sensing wafer 100, prevents in follow-up encapsulation process substrate 105 from figure
Come off on sensing wafer 100, between substrate 105 and image sensing wafer 100, form adhesive-layer 104.
Concrete, form adhesive-layer 104 on substrate 105 surface, by image sensing wafer 100 first with have
The substrate 105 of adhesive-layer 104 carries out pressing.Described adhesive-layer 104 improves substrate 104 and image sensing
Adhesiveness between wafer 100.
As a specific embodiment, employing coating process is at substrate 105 surface coating liquid state glue, by institute
State substrate 105 and 100 first pressings of image sensing wafer with liquid glue, after liquid glue solidifies
It is converted into the adhesive-layer 104 between image sensing wafer 100 and substrate 105.
Refer to Fig. 3, described image sensing wafer 100 second face is carried out reduction processing, until exposing
Metal column 103 surface, makes metal column 103 surface flush with image sensing wafer 100 second face.
After image sensing wafer 100 is carried out reduction processing, it is beneficial to be subsequently formed the encapsulation of thinner thickness
Structure；Further, after reduction processing, is come out in metal column 103 surface, the letter of follow-up offer is provided
Number processing wafer electrically connects with metal column 103, thus realizes signal processing wafer and image sensing wafer 100
Between electrical connection.
The technique of described reduction processing can be mechanical lapping or cmp etc..
After reduction processing, metal column 103 one end electrically connects with the first pad 102, with described one end phase
To the other end flush with image sensing wafer 100 second face.
Refer to Fig. 4, it is provided that signal processing wafer 107, described signal processing wafer 107 has the 3rd
And with described 3rd relative fourth face, and signal processing wafer 107 the 3rd mask has the second pad 108.
There is in described signal processing wafer 107 multiple signal processing chip, described second pad 108
Quantity and position can according to actual process it needs to be determined that.
In the present embodiment, the size of described signal processing wafer 107 and the size of image sensing wafer 100
Unanimously, and, accordingly, described signal processing wafer 107 has the first chip area (sign)
And the first Cutting Road centrage (sign) between the first chip area.
Owing to signal processing wafer 107 only having signal processing chip, it is not necessary in view of signal processing core
Location problem between sheet and image sensor chip so that the signal processing chip of formation has higher property
Energy.
Refer to Fig. 5, by described image sensing wafer 100 second and signal processing wafer 107 the 3rd
Fixed engagement, makes the second pad 108 corresponding with the position of metal column 103.
Described second pad 108 is corresponding with the position of metal column 103, say, that the second pad 108
It is positioned at the underface of metal column 103, follow-up when etching the second pad 108 and forming opening, opening of formation
The bottom of mouth can expose the surface of metal column 103.
In the present embodiment, in order to improve gluing between image sensing wafer 100 and signal processing wafer 107
Attached property, becomes to adhere at described image sensing wafer 100 second or signal processing wafer 107 third surface shape
Layer 106, by described adhesion layer 106 by image sensing wafer 100 second and signal processing wafer 107
3rd fixed engagement, and make the position corresponding to metal column 103, the position of the second pad 108, signal
Process the first Cutting Road centrage of wafer 107 and the Cutting Road centrage 110 of image sensing wafer 100
Overlap.
The method using some glue, plastic roll or print glue forms described adhesion layer 106.
Refer to Fig. 6, described signal processing wafer 107 fourth face is performed etching process, formed and run through institute
State the through hole 109 of signal processing wafer 107 fourth face, and described through hole 109 exposes the second pad 108
Surface.
The technique of described etching processing is dry etching.As a specific embodiment, form through hole 109
Processing step include: described signal processing wafer 107 fourth face formed photoresist film；To described light
Photoresist film is exposed, development treatment, forms patterned photoresist layer；With described patterned photoetching
Glue-line is mask, etches described signal processing wafer 107 and forms through hole 109, until exposing the second pad
108 surfaces.
In the present embodiment, using plasma etching technics etches described signal processing wafer 107, described etc.
The technological parameter of ion etch process is: etching gas includes SF6And C4F8, wherein, SF6Gas flow
For 100sccm to 2000sccm, C4F8Gas flow is 200sccm to 1000sccm, etching source radio frequency
Power is 1000 watts to 5000 watts, and etching bias radio-frequency power is 0 watt to 500 watts, etch chamber chamber pressure
It is by force that 10 millitorrs are to 200 millitorrs.
It should be noted that in the present embodiment, described through hole 109 bottom-exposed goes out the second pad 108
Divide surface, i.e. described through hole 109 bottom area is less than described second pad 108 surface area, and it is good
Place is: time bottom follow-up continuation etching through hole 109 until exposing the first pad 102 surface, described
Etching technics can etch removes the second pad 108 come out, if by the second pad bottom through hole 109
All come out in 108 surfaces, then the second pad 108 is easily all etched removal, causes package failure；
And in the present embodiment, bottom through hole 109, only exposing the second pad 108 part surface, subsequent etching is led to
After the second pad 108 bottom hole 109, in signal processing wafer 107, still remain with the of area
Two pads 108, realize signal processing wafer 107 and image sensing wafer by remaining second pad 108
Electrical connection between 100.
In other embodiments of the present invention, via bottoms can also expose the second pad all surfaces, after
When continuing the second pad bottom etching through hole, it shall be noted that whole second bond-pad etch should not removed.
Refer to Fig. 7, formed with sidewall bottom described signal processing wafer 107 fourth face, through hole 109
Insulating barrier 111.
Described insulating barrier 111 provides electric isolution for signal processing wafer 107, and may also operate as protection
The effect of signal processing wafer 107 fourth face.
Chemical gaseous phase deposition, physical vapour deposition (PVD) or atom layer deposition process is used to form described insulating barrier
111；The material of described insulating barrier 111 is the insulation such as silicon oxide, silicon nitride, silicon oxynitride or insulating resin
Material.
In the present embodiment, the material of described insulating barrier 111 is silicon oxide.
Refer to Fig. 8, etching is removed and is positioned at the insulating barrier 111 bottom through hole 109, continues etching and is positioned at logical
The second pad 108 bottom hole 109 and adhesion layer 106, until exposing metal column 103 surface,
Opening 112 is formed in two pads 108 and adhesion layer 106.
In the present embodiment, described opening 112 bottom-exposed goes out metal column 103 surface, and due to through hole 109
Bottom-exposed goes out the second pad 108 part surface, therefore after forming opening 112, and metal column 103 table
Face and the second pad 108 sidewall surfaces are exposed, and described opening 112 is mutual with through hole 109
Run through.
The purpose forming described opening 112 is: due to opening 112 formed after, metal column 103 table
Face and the second pad 108 sidewall surfaces are exposed, follow-up leading at formation filling full gate mouth 112
After electric layer, conductive layer not only contacts with metal column 103 but also contacts with the second pad 108, therefore passes through
Described conductive layer makes metal column 103 and the second pad 108 electrically connect, thus realizes signal processing wafer 107
And the purpose of electrical connection between image sensing wafer 100.
Radium art or etching technics is used to form described opening 112.
As a specific embodiment, the processing step using etching technics to form opening 112 includes:
Described insulating barrier 111 surface forms patterned photoresist layer, and described patterned photoresist layer exposes
It is positioned at the insulating barrier 111 of through hole 109 lower surface；With described patterned photoresist layer as mask, etching
Remove and be positioned at the insulating barrier 111 bottom through hole 109, continue etching and be positioned at the second pad bottom through hole 109
108 and adhesion layer 106, in the second pad 108 and adhesion layer 106, form opening 112, until
Expose metal column 103 surface.
In the present embodiment, Radium art is used to form described opening 112, the technological parameter of described Radium art
For: frequency is 10kHZ to 200kHZ, and power is 0.5watts to 5watts, and spot size is 50 μm
To 150 μm, hot spot translational speed is 100mm/sec to 300mm/sec, and number of repetition is 1 to 10 time.
Refer to Fig. 9, form the conductive layer 116 filling full gate mouth 112 (refer to Fig. 8), exist simultaneously
Described insulating barrier 111 surface forms metal redistribution layer 113, and described metal redistribution layer 113 is also located at
Conductive layer 116 surface, is electrically connected the second pad 108 and metal column 103 by conductive layer 116.
The material of described metal redistribution layer 113 includes Cu, Al or W.In the present embodiment, metal divides again
Layer of cloth 113 is identical with the material of conductive layer 116, and with along with processing step is formed.
As an embodiment, the forming step of described metal redistribution layer 113 and conductive layer 116 includes:
Form the conductive layer 116 filling full gate mouth 112, be covered in described insulating barrier 111 table in described formation simultaneously
The metal film in face, simultaneously；Patterned photoresist layer is formed in described metallic film surface；With described figure
The photoresist layer changed is metal film described in mask etching, forms metal redistribution layer 113.
Refer to Figure 10, on metal redistribution layer 113 surface of described signal processing wafer 107 fourth face
Form solder-bump 115.
In the present embodiment, described solder-bump 115 electrically connects with conductive layer 116, concrete, by institute
State metal redistribution layer 113, it is achieved the electrical connection between solder-bump 115 and conductive layer 116.Described weldering
Connect protruding 115 for electrically connecting with external circuit, therefore can make metal by described solder-bump 115
Post the 103, second pad 108 electrically connects with external circuit.
The material of described solder-bump 115 is Sn, Au or Sn-Au alloy.Use screen printing and backflow
Technique or plant ball technique and form described solder-bump 115.
In the present embodiment, before forming solder-bump 115, at metal redistribution layer 113, conductive layer
116 and insulating barrier 111 surface formed welding resisting layer 114.The material of described welding resisting layer 114 is insulant,
Play the effect that protection metal redistribution layer 113 is not oxidized.
After forming welding resisting layer 114, etch described welding resisting layer 114 and expose part metals again to be formed
The groove on distribution layer 113 surface, fills full solder-bump 115, described solder-bump 115 in described groove
Electrically connect with metal redistribution layer 113.
In the present embodiment, make solder-bump 115 and conductive layer 116 by forming metal redistribution layer 113
Electrical connection.
In other embodiments of the present invention, as shown in figure 11, in order to reduce packaging technology step, envelope is improved
Dress efficiency, the processing step forming conductive layer 116 and solder-bump 115 includes: is formed and fills full institute
State the conductive layer 116 of opening 112 (refer to Fig. 8)；Form the full described through hole 109 of filling (to refer to
Solder-bump 115 Fig. 8), and described solder-bump 115 top is higher than signal processing wafer 107 the 4th
Face.And in order to avoid solder-bump 115 and signal processing wafer 107 occur unnecessary electrical connection,
Before forming solder-bump 115, forming insulating barrier 111 at through hole 109 sidewall, described insulating barrier 111 is also
It is positioned at signal processing wafer 107 fourth face.
Concrete, in one embodiment, conductive layer 116 and solder-bump 115 with along with technique walk
Being formed in rapid, the material of conductive layer 116 is identical with the material of solder-bump 115.In another embodiment,
Conductive layer 116 can also be initially formed, then form solder-bump 115, and conductive layer 116 and solder-bump 115
Material different.
Refer to Figure 12, cut described image along described Cutting Road centrage 110 (refer to Figure 10) and pass
Sense wafer 100 (refer to Figure 10) and signal processing wafer 107 (refer to Figure 10), formed some
Single encapsulating structure.
The technique cutting described image sensing wafer 100 and signal processing wafer 107 is microtome knife
Cutting or cut.Owing to cut has less kerf width, improve the accurate of cutting technique
Property, the present embodiment use laser image sensing wafer 100 and signal processing wafer 107 are cut.
Cut described image sensing wafer 100 and form some image sensor chips 200, cut at described signal
Reason wafer 107 forms some signal processing chips 207.
Owing to image sensing wafer 100 and signal processing wafer 107 are for be formed separately, reduce image
Sensing wafer 100 and the formation process difficulty of signal processing wafer 107, and avoid considering image sensing core
Sheet 200 and the signal processing chip 207 arrangement interconnection problems in same wafer, image sensor chip 200
Will not be limited by each other with signal processing chip 207, therefore the image in image sensing wafer 100
Sensing chip 200 has optimum performance, same, the signal processing chip in signal processing wafer 107
207 also have optimum performance, and therefore the performance of the encapsulating structure that the present embodiment is formed is high.
In an alternative embodiment of the invention, when solder-bump 115 fills full through hole, then along Cutting Road
Centrage 110 (refer to Figure 11) cutting image sensing wafer 100 (refer to Figure 11) and signal processing
After wafer 107 (refer to Figure 11), the encapsulating structure of formation as shown in figure 13, fill out by solder-bump 115
Being full of through hole, conductive layer 116 fills full gate mouth, and solder-bump 115 contacts with conductive layer 116, passes through
Second pad 108 and metal column 103 are electrically connected by conductive layer 116, and solder-bump 115 top is higher than
Signal processing chip 207 surface.
Accordingly, the embodiment of the present invention also provides for a kind of encapsulating structure, refer to Figure 12, and described encapsulation is tied
Structure includes:
Image sensor chip 200, described image sensor chip 200 have first and with described first
Relative second, described image sensor chip 200 first mask has photo-sensitive cell 101 and around described
First pad 102 of photo-sensitive cell 101, has metal column 103 in described image sensor chip 200, and
One end of described metal column 103 electrically connects with the first pad 102, the other end relative with described one end with
Image sensor chip 200 second face flushes；
Signal processing chip 207, described signal processing chip 207 have the 3rd and with described 3rd phase
To fourth face, described signal processing chip 207 the 3rd mask has at the second pad 108, and described signal
Reason chip 207 the 3rd and 200 second fixed engagement of image sensor chip, described second pad 108
Electrically connect with metal column 103；
Run through the through hole of described signal processing chip 207 fourth face, and described via bottoms exposes second
Pad 108 surface.
In the present embodiment, it is formed between described image sensor chip 200 and signal processing chip 207
Adhesion layer 106, improves the adhesiveness between image sensor chip 200 and signal processing chip 207, prevents
Separate between image sensor chip 200 with signal processing chip 207.
In the present embodiment, described via bottoms exposes the second pad 108 part surface, and described encapsulation is tied
Structure also includes: being positioned at the second pad 108 and the opening of adhesion layer 106, open bottom exposes gold
Belong to post 103 surface, and described opening mutually runs through with through hole.
Described encapsulating structure also includes: fill the conductive layer 116 of full described opening, and described conductive layer 116
Contact with metal column 103 and the second pad 108, make the second pad 108 by described conductive layer 116
Electrically connect with metal column 103.
In the present embodiment, described encapsulating structure also includes: be positioned at through-hole side wall and signal processing chip 207
The insulating barrier 111 of fourth face；It is positioned at the metal redistribution layer 113 on insulating barrier 111 surface, and described metal
Redistributing layer 113 is also located at conductive layer 116 surface；It is positioned at described signal processing chip 207 fourth face
The solder-bump 115 on metal redistribution layer 113 surface.
In order to improve the reliability of encapsulating structure, also include: be positioned at described metal redistribution layer 113 and lead
The welding resisting layer 114 on electric layer 112 surface；It is positioned at the welding resisting layer 114 of described signal processing chip 207 fourth face
In groove, and described bottom portion of groove exposes metal redistribution layer 113 surface, described solder-bump 115
Fill full described groove.
Described metal redistribution layer 113 contacts with conductive layer 116 surface, described conductive layer 116 and second
Pad 108 sidewall surfaces and metal column 103 surface contact, the most described conductive layer 116 as in
Between medium so that the second pad 108, metal column 103 electrically connect with metal redistribution layer 113, and weld
Protruding 115 electrically connect with metal redistribution layer 113, therefore make solder-bump by metal redistribution layer 113
115, electrically connect between signal processing chip 207 and image sensor chip 200.
Described solder-bump 115 be used for electrically connecting signal processing chip 207, image sensor chip 200 and
External circuit.
Described encapsulating structure also includes: be positioned at the substrate 105 of image sensor chip 200 first.This enforcement
In example, in order to improve the adhesiveness between substrate 105 and image sensor chip 200 first, described
Adhesion layer 104 it is also formed with between substrate 105 and image sensor chip 200；In other embodiments, base
Plate directly contacts with image sensor chip first.
Described substrate 105 provides a supporting role for image sensor chip 200 and signal processing chip 207,
Improve image sensor chip 200 and the mechanical strength of signal processing chip 207, prevent image sensor chip
200 or signal processing chip 207 there is splintering problem, improve the reliability of encapsulating structure.And external light
Through described substrate 105, arrive the region at photo-sensitive cell 101 place, so that image sensor chip 200 connects
Receive ambient.
Image sensor chip 200 and signal processing chip 207 are separately arranged by the embodiment of the present invention, tool
Body, signal processing chip 207 is set image sensor chip 200 second, it is to avoid consider at same core
Image sensor chip 200 and the arrangement of signal processing chip 207 and interconnection problems are set in sheet, reduce
Design difficulty；Further, owing to being subject between image sensor chip 200 and signal processing chip 207
The impact of the other side's arrangement and area is little, therefore image sensor chip 200 and signal processing chip 207
All can obtain optimal performance, improve the encapsulation performance of encapsulating structure；Simultaneously as image sensing core
Sheet 200 and signal processing chip 207 are also not disposed on same chip, for hinge structure, this
The area of the image sensor chip 200 of inventive embodiments is less, therefore, and setting of image sensor chip 200
Meter cost reduces.
In an alternative embodiment of the invention, as shown in figure 13, described encapsulating structure includes: fill full through hole
Solder-bump 115, described solder-bump 115 contacts with conductive layer 116, and described solder-bump 115
Top is higher than signal processing chip 207 fourth face.Described solder-bump 115 directly connects with conductive layer 116
Touching to be electrically connected, conductive layer 116 electrically connects, therefore with the second pad 108 and metal column 103
Signal processing chip 207, image sensor chip 200 and external circuit is made by described solder-bump 115
Between electrically connect.In order to prevent solder-bump 115 from signal processing chip 207, unnecessary being electrically connected occurring
Connecing, be formed with insulating barrier 111 between solder-bump 115 and through-hole side wall, described insulating barrier 111 also covers
It is placed on signal processing chip 207 fourth face.
Another embodiment of the present invention also provides for a kind of method for packing, and Figure 14 to Figure 17 is another reality of the present invention
Execute the cross-sectional view of example encapsulation process, it should be noted that in the present embodiment with above-described embodiment
Middle mutually isostructural parameter and effect etc. limit and repeat no more in the present embodiment, specifically refer to above-mentioned reality
Execute example.
Refer to Figure 14, it is provided that image sensing wafer 300, described image sensing wafer 300 has some
Chip area and the Cutting Road centrage 310 between chip area.
Described image sensing wafer 300 has first and second be oppositely arranged with described first face,
Described image sensing wafer 300 first mask has some photo-sensitive cells 301 and around described photo-sensitive cell 301
The first pad 302, there is metal column 303, metal column 303 one end and the in image sensing wafer 300
One pad 302 electrically connects, and the other end relative with described one end is neat with image sensing wafer 300 second
Flat.
In the present embodiment, at 300 first formation substrates 305 of image sensing wafer.If substrate 305 and figure
Between sensing wafer 300 first, there is stronger adhesiveness, such as, when the material of substrate 305 is
During liquid glass, directly substrate 305 is covered image sensing wafer 300 first.As a tool
Body embodiment, uses spin coating process (spin-on-coating) image sensing wafer 100 first
Coating liquid glass, at 300 first formation substrates 305 of image sensing wafer.
Please continue to refer to Figure 14, it is provided that signal processing wafer 307, described signal processing wafer 307 has
3rd and with described 3rd relative fourth face, and described signal processing wafer 307 the 3rd mask has
Second pad 308；By Direct Bonding technique, image sensing wafer 300 second is brilliant with signal processing
307 the 3rd fixed engagement of circle, described second pad 308 directly contacts with metal column 303 surface, will
Second pad 308 electrically connects with metal column 303.
Refer to Figure 15, described signal processing wafer 307 fourth face is performed etching process, formation runs through
The through hole 309 of described signal processing wafer 307 fourth face, and described through hole 309 exposes the second pad
308 surfaces.
In the present embodiment, described through hole 309 bottom-exposed goes out the second pad 308 lower surface (will be in second
The face that pad 308 flushes with signal processing wafer 307 the 3rd face is referred to as upper surface, with described upper surface phase
To another side be referred to as lower surface).In other embodiments, via bottoms exposes the second pad sidewall table
Face.
Refer to Figure 16, at described signal processing wafer 307 fourth face, through hole 309 (refer to Figure 15)
Sidewall forms insulating barrier 311；Metal redistribution layer 313, described gold is formed on described insulating barrier 311 surface
Belong to redistributing layer 313 to be also located at bottom through hole 309；Gold at described signal processing wafer 307 fourth face
Belong to redistributing layer 313 surface and form solder-bump 315.
Owing to the second pad 308 electrically connects with metal column 303, metal redistribution layer 313 is positioned at the second weldering
Dish 308 surface, then described metal redistribution layer 313 and the second pad 308 and metal column 303 all electricity
Connect.By the solder-bump 315 electrically connected with metal redistribution layer 313, make signal processing wafer 307
Electrically connect with external circuit with image sensing wafer 300.
In the present embodiment, in order to improve the reliability of encapsulating structure, before forming solder-bump 315,
Welding resisting layer 314 is formed on metal redistribution layer 313 surface and the second pad 308 surface；It is being positioned at signal
Forming groove in processing the welding resisting layer 314 of wafer 307 fourth face, described groove exposes part metals again
Distribution layer 313 surface；Form the solder-bump 315 filling full described groove.
In other embodiments of the present invention, in order to reduce processing step, improve packaging efficiency, formed and fill
The solder-bump of full described through hole, and described solder-bump top is higher than signal processing wafer fourth face；And
Prevent future solder-bump from signal processing wafer fourth face, unnecessary electrical connection occurring, in solder-bump
And form insulating barrier between through-hole side wall, and described insulating barrier is also located at signal processing wafer fourth face.
Refer to Figure 17, cut described image along described Cutting Road centrage 310 (refer to Figure 16) and pass
Sense wafer 300 (refer to Figure 16) and signal processing wafer 307 (refer to Figure 16), formed some
Single encapsulating structure.
Described cutting technique refers to the explanation of previous embodiment, does not repeats them here.Cutting image senses
Wafer 300 forms image sensor chip 400, and cutoff signal processes wafer 307 and forms signal processing chip
407。
Owing to image sensing wafer 300 and signal processing wafer 307 are for be formed separately, reduce image
Sensing wafer 300 and the formation process difficulty of signal processing wafer 307, and avoid considering image sensing core
Sheet 400 and the signal processing chip 407 arrangement interconnection problems in same wafer, image sensor chip 400
Will not be limited by each other with signal processing chip 407, therefore the image in image sensing wafer 400
Sensing chip 400 has optimum performance, same, the signal processing chip in signal processing wafer 307
407 also have optimum performance, and therefore the performance of the encapsulating structure that the present embodiment is formed is high.
Accordingly, the present embodiment improves a kind of encapsulating structure, refer to Figure 17, and described encapsulating structure includes:
Image sensor chip 400, described image sensor chip 400 have first and with described first
Relative second, described image sensor chip 400 first mask has photo-sensitive cell 301 and around described
First pad 302 of photo-sensitive cell 301, has metal column 303 in described image sensor chip 400, and
One end of described metal column 303 electrically connects with the first pad 302, the other end relative with described one end with
Image sensor chip 400 second face flushes；
Signal processing chip 407, described signal processing chip 407 have the 3rd and with described 3rd phase
To fourth face, described signal processing chip 407 the 3rd mask has at the second pad 308, and described signal
Reason chip 407 the 3rd and 400 second fixed engagement of image sensor chip, described second pad 308
Electrically connect with metal column 303；
Run through the through hole of described signal processing chip 407 fourth face, and described via bottoms exposes second
Pad 308 surface.
In the present embodiment, described signal processing chip 407 the 3rd and image sensor chip 400 second
Directly contact, described second pad 308 surface contacts with metal column 303 surface, the second pad 308
With metal column 303 by the way of directly contacting with electrical connection.
In the present embodiment, described through hole exposes the second pad 308 lower surface (will be in the second pad 308
The face flushed with signal processing wafer 307 the 3rd face is referred to as upper surface, another relative with described upper surface
Face is referred to as lower surface)；In other embodiments, through hole exposes the second land side wall surface.
In order to make signal processing chip 407 and image sensor chip 400 electrically connect with external circuit, institute
State encapsulating structure also to include: be positioned at described through-hole side wall and the insulation of signal processing chip 407 fourth face
Layer 311；It is positioned at described via bottoms and the metal redistribution layer 313 on insulating barrier 311 surface；It is positioned at institute
State the solder-bump 315 on metal redistribution layer 313 surface of signal processing chip 407 fourth face.
In order to improve the reliability of encapsulating structure, also include: be positioned at described metal redistribution layer 313 surface
Welding resisting layer 314；It is positioned at the groove of the welding resisting layer 314 of described signal processing chip 407 fourth face, and
Described bottom portion of groove exposes metal redistribution layer 313 surface, and described solder-bump 315 is filled full described
Groove.
In other embodiments of the present invention, in order to make signal processing chip and image sensor chip and external electrical
Road electrically connects, and described encapsulating structure also includes: filling the solder-bump of full described through hole, described welding is convex
Rise and contact with the second pad, and described solder-bump top is higher than signal processing chip fourth face.Future
Prevent solder-bump from signal processing chip, unnecessary electrical connection occurring, at solder-bump and through-hole side wall
Between be formed with insulating barrier, and described insulating barrier is also located at signal processing chip fourth face.
In the present embodiment, described encapsulating structure also includes: be positioned at the base of image sensor chip 400 first
Plate 305, described substrate 305 directly contacts with image sensor chip 400 first；In other embodiments,
Adhesive-layer can also be formed between image sensor chip and substrate.
Image sensor chip 400 and signal processing chip 407 are separately arranged by the embodiment of the present invention, tool
Body, signal processing chip 407 is set image sensor chip 400 second, it is to avoid consider at same core
Image sensor chip 400 and the arrangement of signal processing chip 407 and interconnection problems are set in sheet, reduce
Design difficulty；Further, owing to being subject between image sensor chip 400 and signal processing chip 407
The impact of the other side's arrangement and area is little, therefore image sensor chip 400 and signal processing chip 407
All can obtain optimal performance, improve the performance of encapsulating structure；Simultaneously as image sensor chip 400
With signal processing chip 407 being not disposed on same chip, for hinge structure, the present invention is real
The area of the image sensor chip 400 executing example is less, therefore, and the design cost of image sensor chip 400
Reduce so that the low cost of encapsulating structure.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (28)
1. an encapsulating structure, it is characterised in that including:
Image sensor chip, described image sensor chip have first and with described first relative
Second, described image sensor chip the first mask have photo-sensitive cell and around described photo-sensitive cell first
Pad, has metal column, and one end of described metal column is electric with the first pad in described image sensor chip
Connect, the other end relative with described one end flushes with image sensor chip the second face, described metal column and
One end of described first pad electrical connection is the first end, and the distance of described first end to described first is the
One distance, described first distance is equal to the thickness of described first pad；
Signal processing chip, described signal processing chip have the 3rd and with described 3rd relative
On four sides, described signal processing chip the 3rd mask has the second pad, and described signal processing chip the 3rd
With second fixed engagement of image sensor chip, described second pad electrically connects with metal column；
Run through the through hole of described signal processing chip fourth face, and described through hole exposes the second bond pad surface.
2. encapsulating structure as claimed in claim 1, it is characterised in that described image sensor chip and signal processing
Adhesion layer it is formed with between chip.
3. as claimed in claim 2 encapsulating structure, it is characterised in that also include: be positioned at described second pad with
And the opening in adhesion layer, open bottom exposes metal column surface, and described opening is mutual with through hole
Run through.
4. encapsulating structure as claimed in claim 3, it is characterised in that also include: fill leading of full described opening
Electric layer, and described conductive layer contacts with metal column and the second pad.
5. encapsulating structure as claimed in claim 4, it is characterised in that also include: be positioned at through-hole side wall and letter
Number process chip fourth face insulating barrier；It is positioned at the metal redistribution layer of surface of insulating layer, and described gold
Belong to redistributing layer and be also located at conductive layer surface；The metal being positioned at described signal processing chip fourth face divides again
The solder-bump on layer of cloth surface.
6. encapsulating structure as claimed in claim 4, it is characterised in that also include: fill the weldering of full described through hole
Connecing projection, described solder-bump contacts with conductive layer, and described solder-bump top is higher than at signal
Reason chip fourth face.
7. as claimed in claim 6 encapsulating structure, it is characterised in that described solder-bump and through-hole side wall it
Between be formed with insulating barrier, described insulating barrier is also covered in signal processing chip fourth face.
8. encapsulating structure as claimed in claim 1, it is characterised in that described signal processing chip the 3rd and figure
As second direct contact of sensing chip, described second bond pad surface contacts with metal column surface.
9. as claimed in claim 8 encapsulating structure, it is characterised in that also include: be positioned at described through-hole side wall with
And the insulating barrier of signal processing chip fourth face；It is positioned at the gold of described via bottoms and surface of insulating layer
Belong to redistributing layer；The welding on the metal redistribution layer surface being positioned at described signal processing chip fourth face is convex
Rise.
10. encapsulating structure as claimed in claim 8, it is characterised in that fill the solder-bump of full described through hole,
Described solder-bump contacts with the second pad, and described solder-bump top is higher than signal processing chip
Fourth face.
11. encapsulating structures as claimed in claim 1, it is characterised in that also include: be positioned at image sensor chip
The substrate of one side.
12. encapsulating structures as claimed in claim 11, it is characterised in that described substrate and image sensor chip first
Adhesive-layer it is also formed with between face.
13. 1 kinds of method for packing, it is characterised in that including:
There is provided image sensing wafer, described image sensing wafer have first and with described first relative
Second, described image sensing wafer the first mask has some photo-sensitive cells and around described photo-sensitive cell
The first pad, there is metal column, and described metal column one end and the first weldering in described image sensing wafer
Dish electrically connects, and the other end relative with described one end flushes with image sensing wafer the second face；
There is provided signal processing wafer, described signal processing wafer have the 3rd and with described 3rd relative
The 3rd, and described signal processing wafer the 3rd mask has some second pads；
By described image sensing wafer second and the 3rd fixed engagement of signal processing wafer, make the second weldering
Dish is corresponding with the position of metal column；
Described second pad is electrically connected with metal column；
Form the through hole running through described signal processing wafer fourth face, and described through hole exposes the second pad
Surface；
Cut described signal processing wafer and image sensing wafer, form the encapsulating structure of some single,
Described encapsulating structure includes signal processing chip and image sensor chip.
14. method for packing as claimed in claim 13, it is characterised in that described image sensing wafer second or
Signal processing wafer third surface shape becomes adhesion layer, by described adhesion layer by image sensing wafer second
With the 3rd fixed engagement of signal processing wafer.
15. method for packing as claimed in claim 14, it is characterised in that use some glue, plastic roll or the method for print glue
Form described adhesion layer.
16. method for packing as claimed in claim 14, it is characterised in that in described second pad and adhesion layer
Forming opening, described open bottom exposes metal column surface, and described opening mutually runs through with through hole.
17. method for packing as claimed in claim 16, it is characterised in that the processing step forming described opening includes:
Insulating barrier is formed at described signal processing wafer fourth face, via bottoms and sidewall；Etching removal is positioned at
The insulating barrier of via bottoms, continues etching and is positioned at the second pad and the adhesion layer of via bottoms, until cruelly
Expose metal column surface, in the second pad and adhesion layer, form opening.
18. method for packing as claimed in claim 16, it is characterised in that use Radium art to form described opening,
Radium art parameter is: frequency is 10kHZ to 200kHZ, and power is 0.5W to 5W, hot spot chi
Very little is 50 μm to 150 μm, and hot spot translational speed is 100mm/sec to 300mm/sec, repeats secondary
Number is 1 to 10 time.
19. method for packing as claimed in claim 17, it is characterised in that form the conductive layer filling full described opening,
By conductive layer, the second pad and metal column are electrically connected.
20. method for packing as claimed in claim 19, it is characterised in that further comprise the steps of: formation solder-bump,
And solder-bump electrically connects with conductive layer.
21. method for packing as claimed in claim 20, it is characterised in that form described conductive layer and solder-bump
Processing step include: form the conductive layer filling full gate mouth, formed at described surface of insulating layer simultaneously
Metal redistribution layer, and described metal redistribution layer is also located at conductive layer surface；At described signal processing
The metal redistribution layer surface of wafer fourth face forms solder-bump.
22. method for packing as claimed in claim 20, it is characterised in that form described conductive layer and solder-bump
Processing step include: form the conductive layer filling full described opening；Formed and fill full described through hole
Solder-bump, and described solder-bump top is higher than signal processing wafer fourth face.
23. method for packing as claimed in claim 13, it is characterised in that by Direct Bonding technique, image is passed
Sense wafer second and the 3rd fixed engagement of signal processing wafer, by described second pad and metal column
Surface directly contacts electrical connection.
24. method for packing as claimed in claim 23, it is characterised in that further comprise the steps of: at described signal processing
Wafer fourth face, through-hole side wall form insulating barrier；Metal redistribution layer is formed at described surface of insulating layer,
Described metal redistribution layer is also located at via bottoms；Described signal processing wafer fourth face metal again
Distribution layer surface forms solder-bump.
25. method for packing as claimed in claim 23, it is characterised in that further comprise the steps of: formation and fill full described
The solder-bump of through hole, and described solder-bump top is higher than signal processing wafer fourth face.
26. method for packing as claimed in claim 13, it is characterised in that in first shape of described image sensing wafer
Become substrate.
27. method for packing as claimed in claim 26, it is characterised in that described substrate and image sensing wafer it
Between formed adhesive-layer.
28. method for packing as claimed in claim 26, it is characterised in that use spin coating process at image sensing
Wafer the first topcoating covers liquid glass, at first formation substrate of image sensing wafer.
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| CN107342238A (en) * | 2017-06-28 | 2017-11-10 | 华进半导体封装先导技术研发中心有限公司 | A kind of wafer upside-down mounting stacking encapsulation method and structure |
| CN109950237A (en) * | 2017-12-21 | 2019-06-28 | 北京万应科技有限公司 | Sensor microsystems packaging method and sensor microsystems |
| CN112310135B (en) * | 2020-10-19 | 2024-02-06 | 锐芯微电子股份有限公司 | Sensor structure and method for forming sensor structure |
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| KR20060122767A (en) * | 2005-05-27 | 2006-11-30 | 디엔제이 클럽 인코 | 3d structure image sensor package device |
| CN101211945A (en) * | 2006-12-29 | 2008-07-02 | 育霈科技股份有限公司 | Semiconductor image element package structure with die receiving through-hole and method of the same |
| CN103000649A (en) * | 2012-11-22 | 2013-03-27 | 北京工业大学 | Packaging structure and manufacture method for complementary metal-oxide-semiconductor transistor (CMOS) image sensors |
| CN204029810U (en) * | 2014-06-25 | 2014-12-17 | 苏州晶方半导体科技股份有限公司 | A kind of encapsulating structure |
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| US20080191297A1 (en) * | 2007-02-12 | 2008-08-14 | Advanced Chip Engineering Technology Inc. | Wafer level image sensor package with die receiving cavity and method of the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060122767A (en) * | 2005-05-27 | 2006-11-30 | 디엔제이 클럽 인코 | 3d structure image sensor package device |
| CN101211945A (en) * | 2006-12-29 | 2008-07-02 | 育霈科技股份有限公司 | Semiconductor image element package structure with die receiving through-hole and method of the same |
| CN103000649A (en) * | 2012-11-22 | 2013-03-27 | 北京工业大学 | Packaging structure and manufacture method for complementary metal-oxide-semiconductor transistor (CMOS) image sensors |
| CN204029810U (en) * | 2014-06-25 | 2014-12-17 | 苏州晶方半导体科技股份有限公司 | A kind of encapsulating structure |
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