CN105226074A - Image sensing chip-packaging structure and method for packing - Google Patents
Image sensing chip-packaging structure and method for packing Download PDFInfo
- Publication number
- CN105226074A CN105226074A CN201510716297.6A CN201510716297A CN105226074A CN 105226074 A CN105226074 A CN 105226074A CN 201510716297 A CN201510716297 A CN 201510716297A CN 105226074 A CN105226074 A CN 105226074A
- Authority
- CN
- China
- Prior art keywords
- image sensing
- layer
- hole
- electrical wiring
- passivation layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 title claims description 42
- 238000012856 packing Methods 0.000 title claims description 10
- 238000002161 passivation Methods 0.000 claims abstract description 60
- 238000009429 electrical wiring Methods 0.000 claims abstract description 50
- 239000011248 coating agent Substances 0.000 claims abstract description 41
- 238000000576 coating method Methods 0.000 claims abstract description 41
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims abstract description 37
- 239000005304 optical glass Substances 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 24
- 229910000679 solder Inorganic materials 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 230000008569 process Effects 0.000 claims description 12
- 238000003825 pressing Methods 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 238000003384 imaging method Methods 0.000 claims description 7
- 238000004528 spin coating Methods 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 238000011049 filling Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 10
- 239000010410 layer Substances 0.000 description 128
- 235000012431 wafers Nutrition 0.000 description 24
- 238000010276 construction Methods 0.000 description 16
- 239000000758 substrate Substances 0.000 description 13
- 239000007769 metal material Substances 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 230000000694 effects Effects 0.000 description 9
- 229910052782 aluminium Inorganic materials 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 8
- 239000010949 copper Substances 0.000 description 6
- 238000005520 cutting process Methods 0.000 description 6
- 239000012790 adhesive layer Substances 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 238000003466 welding Methods 0.000 description 5
- 239000004411 aluminium Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000011133 lead Substances 0.000 description 3
- 229920000620 organic polymer Polymers 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 238000005507 spraying Methods 0.000 description 3
- 239000004925 Acrylic resin Substances 0.000 description 2
- 229920000178 Acrylic resin Polymers 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 208000003351 Melanosis Diseases 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 238000010010 raising Methods 0.000 description 2
- -1 such as Polymers 0.000 description 2
- 239000011135 tin Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical group [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- UCKMPCXJQFINFW-UHFFFAOYSA-N Sulphide Chemical compound [S-2] UCKMPCXJQFINFW-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000006089 photosensitive glass Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 1
- 239000004926 polymethyl methacrylate Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14632—Wafer-level processed structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14685—Process for coatings or optical elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14687—Wafer level processing
Abstract
The invention provides a kind of image sensing chip-packaging structure, comprising: image sensing chip, it has relative first surface and second surface, the weld pad being provided with image sensing district on the first surface and being positioned at around image sensing district; From the through through hole to weld pad of second surface; Be arranged at the passivation layer on through-hole side wall and second surface; Be arranged at the electrical wiring layer on through hole bottom surface and passivation layer; Be electrically connected on the pedestal of electrical wiring layer; Resilient coating between electrical wiring layer and passivation layer.This encapsulating structure reduces the latent defect of image sensing chip-packaging structure.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of image sensing chip-packaging structure and method for packing thereof.
Background technology
At present, wafer-level packaging (WaferLevelPackaging) technology is cut after carrying out test package to full wafer wafer again, and obtain the technology of single finished product chip, it replaces wire bond package technology gradually, becomes the mainstream technology of encapsulation.
In the encapsulation of image sensor, also adopt Wafer level packaging more, as shown in Figure 1, for existing traditional image sensor package, this structure comprises image sensing chip 10 and cover plate 20, the first surface of image sensing chip is provided with image sensing district 12 and weld pad 14, cover plate 20 is arranged on above image sensing district 12, for the protection of image sensing district, common, cover plate 20 is made up of the supporting construction 24 on glass substrate 22 and glass substrate 22, supporting construction 24 surrounds cavity, be bonded to the first surface at place, image sensing district in supporting construction 24 after, image sensing district 12 is covered in the cavities, play the effect in protection image sensing district.The pedestal 22 being provided with the through guide hole to weld pad 14 on a second surface and being electrically connected with guide hole, thus, realize and outside electrical connection, guide hole comprise in through hole and through hole side second surface on insulating barrier 16, electrical wiring layer 18 and solder mask 22, pedestal 22 is formed on the electrical wiring layer 18 of guide hole side, thus realizes electrical connection that is outside and weld pad.
But in the structure shown here, insulating barrier more than 16 adopts organic material to be formed, and the insulating barrier that organic material is formed is comparatively weak at the edge of through hole, especially for step-like through hole (figure is not depending on going out), easily produce defect at edge.In addition, when follow-up formation electrical wiring layer, need by the radium-shine opening carrying out insulating barrier, after opening, insulating barrier and liner are all breakdown, like this, as shown in Figure 1, the electrical wiring layer 18 formed is formed with liner 14 sidewall and is electrically connected, and the contact area of this connection is less, when wafer is stressed, easy generation fracture, even lost efficacy.
Summary of the invention
In view of this, a first aspect of the present invention provides a kind of image sensing chip-packaging structure, to reduce the defect of image sensing chip-packaging structure.
For solving the problem, embodiments providing a kind of image sensing chip-packaging structure, comprising:
Image sensing chip, it has relative first surface and second surface, the weld pad being provided with image sensing district on the first surface and being positioned at around image sensing district;
From the through through hole to weld pad of second surface;
Be arranged at the passivation layer on through-hole side wall and second surface;
Be arranged at the electrical wiring layer on through hole bottom surface and passivation layer;
Be electrically connected on the pedestal of electrical wiring layer;
Resilient coating between electrical wiring layer and passivation layer.
Optionally, also comprise: light shield layer, to be positioned on second surface and to cover described image sensing district.
Optionally, the material of described light shield layer is metal.
Optionally, described metal is the Al through surperficial Darkening process.
Optionally, the material of described resilient coating is photoresists.
Optionally, also comprise and cover electrical wiring layer the solder mask of filling vias.
Optionally, the cover sheet with described image sensing chip contraposition pressing is also comprised.
Optionally, described cover sheet is optical glass, and at least one of optical glass is provided with anti-reflection layer on the surface.
Optionally, the thickness range of described resilient coating is 5-25 micron.
In addition, present invention also offers a kind of method for packing of image sensing chip, comprising:
Wafer is provided, there is the image sensing chip of many array arrangements, it has relative first surface and second surface, the weld pad that image sensing chip has image sensing district and is positioned at around image sensing district, and described image sensing district and weld pad are positioned at first surface;
Cover sheet is provided, and by itself and described Wafer alignment pressing;
The through through hole to weld pad is formed from second surface;
The second surface of through-hole side wall and through hole both sides forms passivation layer;
Passivation layer on a second surface forms resilient coating;
Form the electrical wiring layer covering through-hole wall and resilient coating;
Electrical wiring layer is formed the pedestal be electrically connected with described electrical wiring layer.
Optionally, before formation through hole, also comprise: form light shield layer in the position in the corresponding image sensing district of second surface.
Optionally, the step forming light shield layer comprises:
Splash-proofing sputtering metal layer on a second surface, and etch, form light shield layer with the position in corresponding image sensing district.
Optionally, described metal level is Al, after the metal level of sputtering Al, also carries out surperficial Darkening process, then etches.
Optionally, after covering electrical wiring layer, before forming pedestal, also comprise:
Form solder mask, and form opening in solder mask on a second surface;
Form pedestal in the opening.
Optionally, described cover sheet is optical glass, and at least one of optical glass is provided with anti-reflection layer on the surface.
Optionally, the step second surface of through-hole side wall and through hole both sides forming passivation layer comprises:
Deposit passivation layer;
Etching removes the passivation layer of via bottoms.
Optionally, the material of described resilient coating is photoresists, and step passivation layer on a second surface being formed resilient coating comprises:
Spin coating photoresists on a second surface;
Resilient coating is formed by exposure imaging technique.
The image sensing chip-packaging structure that the embodiment of the present invention provides and method for packing thereof, adopt passivation layer as insulating barrier at electrical wiring layer and chip chamber, and between electrical wiring layer under pedestal and passivation layer, resilient coating is set, passivation layer has good step coverage, in the spreadability that the edge of through hole has also had, and by Reflow Soldering during resilient coating release formation pedestal to the impulsive force of passivation layer.In addition, for passivation layer, when removing the passivation layer of via bottoms, can be removed by the method for etching and expose liner, like this, electrical wiring layer and the liner of follow-up formation are that face contacts, and have larger contact area, the adhesion of both raisings, reduce further the latent defect of image sensing chip-packaging structure on the whole.
Accompanying drawing explanation
Fig. 1 shows the cross-sectional view of the image sensing chip-packaging structure of prior art;
Fig. 2 shows the cross-sectional view of image sensing chip-packaging structure according to an embodiment of the invention;
Fig. 3 shows the cross-sectional view of the image sensing chip-packaging structure according to another embodiment of invention;
Fig. 4 A to Figure 13 shows the structural representation of the intermediate structure formed in the method for packing of the image sensing chip of the embodiment of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when describing the embodiment of the present invention in detail; for ease of explanation; represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.In addition, fisrt feature described below second feature it " on " structure can comprise the embodiment that the first and second features are formed as directly contact, also can comprise other feature and be formed in embodiment between the first and second features, such first and second features may not be direct contacts.
In order to reduce the defect of image sensing chip-packaging structure, the especially defect of the edge weakness of through hole, the present invention proposes a kind of image sensing chip-packaging structure, referring to figs. 2 and 3 shown, it comprises:
Image sensing chip 100, it has relative first surface 1001 and second surface 1002, first surface 1001 is provided with image sensing district 102 and is positioned at the weld pad 104 around image sensing district 102;
From the through through hole 105 to weld pad 1004 of second surface 1002;
Be arranged at the passivation layer 106 on through hole 105 sidewall and second surface 1002;
Be arranged at the electrical wiring layer 108 on through hole 105 bottom surface and passivation layer 106;
Be electrically connected on the pedestal 122 of electrical wiring layer 108;
Resilient coating 107 between electrical wiring layer 108 and passivation layer 106.
In the present invention, adopt passivation layer as insulating barrier at electrical wiring layer and chip chamber, and between electrical wiring layer under pedestal and passivation layer, resilient coating is set, passivation layer has good step coverage, in the spreadability that the edge of through hole has also had, and by Reflow Soldering during resilient coating release formation pedestal to the impulsive force of passivation layer.In addition, for passivation layer, when removing the passivation layer of via bottoms, can be removed by the method for etching and expose liner, like this, electrical wiring layer and the liner of follow-up formation are that face contacts, and have larger contact area, the adhesion of both raisings, reduce further the latent defect of image sensing chip on the whole.
In embodiments of the present invention, this image sensing chip-packaging structure can not yet carry out the structure of cutting for being formed in guide hole and pedestal processing, also can be the structure of the single finished product chip after cutting.
For image sensing chip, this chip is at least formed with image sensing district and weld pad, in embodiments of the present invention, the weld pad 104 first surface of image sensing chip being provided with image sensing district 102 and being positioned at around image sensing district 102, described image sensing district 102 is for receiving extraneous light and being converted to electrical signal, at least image sensor unit is formed with in described image sensing district 102, the associated circuit be connected with image sensor unit can also be formed with further, as the driver element (scheming not shown) for driving chip, obtain the reading unit (scheming not shown) of photosensitive area electric current and the processing unit (scheming not shown) etc. of process photosensitive area electric current.
Certainly, according to concrete design requirement, this image sensing chip can also be provided with other parts, due to these parts and inventive point of the present invention not closely related, be not described in further detail at this.
Normally, for the ease of wiring, image sensing district 102 is positioned at the centre position of one single chip unit, the rectangular distribution of weld pad 104, be positioned at the surrounding in image sensing district 102 and be positioned at the marginal position of one single chip unit unit, each side can be formed with several weld pads 104, weld pad 104 is the input/output port of device and external circuit in image sensing district, the electrical signal in image sensing district 102 can be spread out of external circuit, the material of weld pad is electric conducting material, can be metal material, such as Al, Au and Cu etc.
Be understandable that, according to different designs and demand, can adjust image sensing district and the position of weld pad and the quantity of weld pad, such as, weld pad only can be arranged on side or certain both sides in image sensing district.
In embodiments of the present invention; also comprise the cover sheet 200 with image sensing district 102 contraposition pressing; cover sheet 200 is the parts for the protection of image sensing district 102; it has the space in accommodating image sensing district; thus; image sensing district forms protective cover, while protection image sensing district is not damaged, does not affect light and enter image sensing district.In an embodiment of the present invention; described cover sheet 200 is optical glass; optical glass is provided with supporting construction 220; by supporting construction 220 and image sensing district 102 contraposition pressing; image sensing district 102 is accommodated therein by the cavity surrounded between supporting construction 220, forms a cloche and protect image sensing district 102.Be understandable that, cover sheet 200 also can adopt other structure, as adopted lighttight substrate to be formed, and arranges opening in the region that substrate is corresponding with image sensing district or has the light openings of blocking.
But, for the cover sheet of optical glass, the defect of mirror-reflection can be there is, reduce the light entering into image sensing district, and then affect the quality of imaging, for this reason, shown in figure 3, in embodiments of the present invention, the surface of the cover sheet 200 of optical glass is provided with anti-reflection layer 201, this anti-reflection layer 201 can be arranged on optical glass on the surface in image sensing district 102 or on the surface relative with this surface, also this anti-reflection layer 201 can be all set on two of an optical glass surface, the region that this anti-reflection layer is at least corresponding with covering image sensing district 102, the material of suitable anti-reflection coating can be selected according to selected optical glass.By arranging anti-reflection layer on the surface of optical glass, reducing reverberation, increasing the light entering into image sensing district, and then improve the quality of imaging.
In the present invention, realized the electrical connection of weld pad 104 and external circuit by through hole 105, thus, the signal of telecommunication in image sensing district 102 is led to external circuit.
In an embodiment of the present invention, as shown in Figures 2 and 3, by realizing the electrical connection of weld pad 104 and external circuit with lower component: from the through through hole 105 to weld pad 1004 of second surface 1002; Be arranged at the passivation layer 106 on through hole 105 sidewall and second surface 1002; Be arranged at the electrical wiring layer 108 on through hole 105 bottom surface and passivation layer 106; Be electrically connected on the pedestal 122 of electrical wiring layer 108.In addition, resilient coating 107 is set between electrical wiring layer 108 and passivation layer 106, to alleviate the impulsive force to passivation layer in pedestal technique.
Wherein, through hole 105 runs through image sensing chip 100 to solder joint 104, through hole 105 is made to expose weld pad 104, through hole 105 can be through to the surface of weld pad 104, also can be through to further in the weld pad 104 of segment thickness, described through hole 105 can be inverted trapezoidal or stepped bore, and namely the cross section of through hole is inverted trapezoidal or stairstepping.
Passivation layer 106 is the electric insulation layer of electrical wiring layer 108, in embodiments of the present invention, passivation layer 106 is the inorganic dielectric material such as oxide or nitride, as silica, silicon nitride or silicon oxynitride or their lamination etc., passivation layer is as the insulating barrier of electrical wiring layer, there is good step coverage, in the spreadability that the edge of through hole has also had, avoid through hole edge weak and the defect that causes.
Described electrical wiring layer 108 covers above-mentioned through-hole wall, and on the second surface extending to through hole both sides, be convenient to be connected with pedestal 122, the material of electrical wiring layer 108 is electric conducting material, can be metal material, such as Al, Au and Cu etc.
Owing to have employed passivation layer 106 as electric insulation layer, in the processing technology of carrying out pedestal, can impact passivation layer, for this reason, in the present invention, between electrical wiring layer 108 below pedestal 122 and passivation layer 106, resilient coating 107 is set, the impulsive force that resilient coating 107 causes passivation layer for discharging pedestal, the material of described resilient coating 107 can be organic polymer photoresist, such as, epoxy resin or acrylic resin etc., the thickness of resilient coating 107 can be 5-25 micron.In addition, more preferably, resilient coating 107 can select photoresists, and like this, resilient coating, except alleviating except the impulsive force of passivation layer, also has absorption effects, light can be avoided to enter image sensing district from second surface.
Further, in further embodiments, can light shield layer 101 be set on a second surface, this light shield layer 101 covers described image sensing district 102, as shown in Figure 3, light shield layer 101 avoid light particularly Infrared enter into image sensing district 102 through wafer, described light shield layer 101 can be metal material, metal material can be such as aluminium, aluminium alloy or other suitable metal materials, light is made to form mirror-reflection on its surface, light is avoided to enter image sensing district, more preferably, this metal material can through the metal A l of Darkening process, the absorption effects that the Al of Darkening process has had further.
In addition; above-mentioned treating, image sensing chip is formed with solder mask 120; solder mask 120 covers electrical wiring layer 108 and filling vias; solder mask plays the effect of insulating protective layer in pedestal technique to other layers; solder mask can be such as anti-welding photosensitive-ink; solder mask can adopt the dielectric material identical with resilient coating 107, to discharge impulsive force that pedestal causes passivation layer further and to protect image sensing chip.
Described pedestal 122 is electrically connected on electric connection layer 108, in the present embodiment, be arranged on the electrical wiring layer 108 on through hole both sides second surface 1002, contact with electrical wiring layer and connect, pedestal is used for the electrical connection with external circuit, described pedestal 122 can be the syndeton such as soldered ball, metal column, and material can be the metal materials such as copper, aluminium, gold, tin or lead.
Above the embodiment of image sensing chip-packaging structure of the present invention is described in detail, in addition, present invention also offers the method for packing of above-mentioned encapsulating structure, below with reference to specific embodiment, this method for packing is described in detail.
First, wafer 1000 is provided, there is the image sensing chip of many array arrangements, it has relative first surface 1001 and second surface 1002, image sensing chip 100 has image sensing district 102 and is positioned at the weld pad 104 around image sensing district, described image sensing district 102 and weld pad 104 are positioned at first surface 1002, shown in figure 4 and Fig. 4 A, wherein, Fig. 4 A is the plan structure schematic diagram of wafer 1000, Fig. 4 and subsequent related figures be image sensing chip 100 unit along AA1 to cross section structure schematic diagram.
In the present embodiment, described wafer 1000 is Semiconductor substrate, and described Semiconductor substrate can be body substrate or the laminated substrate comprising semi-conducting material, as Si substrate, Ge substrate, SiGe substrate or SOI etc.
In embodiments of the present invention, described wafer 1000 is formed with multiple image sensing chip 100, these image sensing chips 100 are arranged in array, Cutting Road region 1100 is provided with between adjacent image sensing chip 100, for cutting described wafer 1000 in subsequent technique, thus form independently image sensing chip-packaging structure.
In embodiments of the present invention, described image sensing chip has image sensing district 102 and is positioned at the weld pad 104 around image sensing district, described image sensing district 102 and weld pad 104 are positioned at first surface 1002, described image sensing district 102 is for receiving extraneous light and being converted to electrical signal, at least image sensor unit is formed with in described image sensing district 102, image sensor unit such as can be arranged by multiple photodiode array and be formed, the associated circuit be connected with image sensor unit can also be formed with further, as the driver element (scheming not shown) for driving chip, obtain the reading unit (scheming not shown) of photosensitive area electric current and the processing unit (scheming not shown) etc. of process photosensitive area electric current.
Then, cover sheet 200 is provided, and by cover sheet 200 and described wafer 1000 contraposition pressing, shown in figure 5-6.
In the present embodiment; as shown in Figure 5; described cover sheet 200 is optical glass; optical glass is provided with supporting construction 220; by supporting construction 220 and image sensing district 102 contraposition pressing; image sensing district 102 is accommodated therein by the cavity surrounded between supporting construction 220, forms a cloche and protect image sensing district 102.Described optical glass can for unorganic glass, polymethyl methacrylate or other there is the light transmissive material of certain strength, the thickness of optical glass can be 300 μm ~ 500 μm.
Described supporting construction 220 is generally dielectric material, such as, can be silica, silicon nitride, silicon oxynitride or photoresists etc.In a specific embodiment, the material of supporting construction is photoresists, first, can on the surface of optical glass spin coating photoresists, then carry out exposure imaging technique, thus, photosensitive glass is formed supporting construction 220.
Because this cover sheet adopts optical glass to be formed, the defect of mirror-reflection can be there is, reduce the light entering into image sensing district, and then affect the quality of imaging, for this reason, shown in figure 5, before formation supporting construction, first anti-reflection layer 201 can be set on the surface of optical glass, this anti-reflection layer 201 can be arranged on optical glass on the surface in image sensing district 102 or on the surface relative with this surface, also this anti-reflection layer 201 can be all set on two of an optical glass surface, anti-reflection layer can be formed on the glass substrate by the mode of spraying, this anti-reflection layer at least covers the region of image sensing district 102 correspondence, the material of suitable anti-reflection coating can be selected according to selected glass substrate.
In this embodiment, as shown in Figure 6, this cover sheet 200 is combined with the first surface of wafer 1000, make supporting construction 220 and image sensing district 102 contraposition pressing, can by arranging adhesive layer (scheming not shown) between the first surface of supporting construction 220 and/or wafer 1000, realize the contraposition pressing of cover sheet 200 and wafer 1000, such as, can in the corresponding position of the first surface of the surface of supporting construction 220 and/or wafer 1000, by spraying, spin coating or the technique pasted arrange adhesive layer, again the two is carried out pressing, realize combining by described adhesive layer.Described adhesive layer both can realize bonding effect, can play again insulation and sealing function.Described adhesive layer can be the polymeric materials such as polymeric adhesion material, such as silica gel, epoxy resin, benzocyclobutene.
Then, realized the electrical connection of weld pad 104 and external circuit by through hole 105 technique, thus, the signal of telecommunication in image sensing district 102 is led to external circuit.
Concrete, first, thus second surface 1002 pairs of wafers 1000 carry out thinning, so that the etching of follow-up through hole, mechanical-chemistry grinding, chemical mechanical milling tech or the combination of the two can be adopted to carry out thinning.
Then, in order to avoid or reduce light particularly Infrared enter into image sensing district 102 from second surface, as shown in Figure 7, light shield layer 101 can be set at least in second surface corresponding image sensing district 102.Described light shield layer 101 can be metal material, such as, can be aluminium, aluminium alloy or other suitable metal materials.In a preferred embodiment, first, metal level can be formed on the second surface of wafer 1000, as aluminum metal by sputtering technology; Then, Darkening process is carried out to this metal level, melanism can be carried out to described metal level by soda acid liquid medicine, such as, the aqueous slkali of sulfur-bearing can be adopted to process described aluminum metal layer, the thickness of the metal level after melanism can be 1 μm ~ 10 μm, preferably, can be 5 μm, 6 μm of grades form the sulfide rete of black on described aluminum metal layer, improve the shaded effect of described layer of aluminum; Then, carry out graphically to metal material layer, only the position of image sensing district 102 correspondence forms light shield layer 101 on a second surface, and this light shield layer also can have larger area compared with image sensing district 102, to hide image sensing district completely, play better shaded effect.
Then, the through through hole 105 to weld pad 104 is formed from second surface 1002, as shown in Figure 8.Concrete, lithographic technique can be utilized, as reactive ion etching or induction coupling plasma etching etc., wafer 1000 is etched, until expose weld pad 104, also can carry out over etching to weld pad 104 further, namely etch away the weld pad of segment thickness, thus, form the through hole 105 exposing weld pad.
Then, the second surface 1002 of through hole 105 sidewall and through hole 105 both sides forms passivation layer 106, as shown in Figure 9.Described passivation layer 106 can be the dielectric material of oxide or nitride, as silica, silicon nitride or silicon oxynitride or their lamination etc.Concrete, first, deposition layer of passivation material, as silica, can adopt the method for chemical vapour deposition (CVD) to deposit, then, carry out masking process, etch under the sheltering of mask, the layer of passivation material on weld pad 104 is removed, thus, only on the second surface 1002 of through hole 105 sidewall and through hole 105 both sides, form passivation layer 106.The electric insulation layer adopting passivation layer to be formed has better spreadability, meanwhile, the passivation layer on etching technics selective removal weld pad can be adopted, thus, ensure that the electrical wiring layer of follow-up formation and weld pad are that face contacts, ensure therebetween better contact and adhesion.
Then, the passivation layer 106 on second surface 1002 forms resilient coating 107, as shown in Figure 10.The material of described resilient coating 107 can be organic polymer photoresist, such as, epoxy resin or acrylic resin etc., more preferably, resilient coating can be photoresists, the technique such as spin coating or spraying can be passed through, form cushioned material layer, then, cushioned material layer is exposed and develops, thus, passivation layer 106 only on second surface 1002 forms resilient coating 107, this resilient coating at least forms pedestal region on a second surface, or extend along the electrical wiring layer that will be formed further, larger area can be had compared with pedestal region resilient coating.
Then, the electrical wiring layer 108 covering through hole 105 inwall and resilient coating 107 is formed, as shown in figure 11.The material of described electrical wiring layer is electric conducting material, it can be metallic material film, such as Al, Au and Cu etc., RDL (reroute layer) technology can be passed through and form electrical wiring layer or other suitable depositing operations, RDL technology such as can be adopted to carry out the plating of Cu, and sputtered with Ti carries out bottoming, form electrical wiring layer 108, RDL technology makes land positions layout again, can meet the requirement of welding zone to pedestal minimum spacing better.
Then, form solder mask 120, and form opening 121 in solder mask 120 on a second surface, as shown in figure 12.Solder mask 120 plays the effect of insulating protective layer in pedestal technique to other layers; solder mask can be such as anti-welding photosensitive-ink, also can adopt the material identical with resilient coating 107; such as organic polymer photoresist, to discharge the impulsive force that pedestal causes passivation layer further.Can form opening 121 by etching technics in solder mask, opening 121 exposes electrical wiring layer 108, for the formation of pedestal.In a specific embodiment, solder mask is anti-welding photosensitive-ink, the anti-welding photosensitive-ink of spin coating, then, forms opening 121, as shown in figure 12 by exposure imaging technique.
Then, in opening 121, pedestal 122 is formed, as shown in figure 13.In specific embodiment, first, can first form UBM (UnderBumpMetal, ball lower metal layer), then carry out planting ball technique, by mask plate, solder ball is positioned on UBM, then adopt reflow soldering process, in perforate, form pedestal 122, pedestal can be the syndeton such as soldered ball, metal column, and material can be metal material or their alloy materials such as copper, aluminium, gold, tin or lead.
Further; can cutting technique be proceeded, along the Cutting Road region 1100 of wafer 1000, wafer 1000 and cover sheet 200 be cut; the encapsulating structure of above-mentioned wafer is cut into single independently chip, thus obtains the encapsulating structure of independent image sensing chip.
In addition, with the method for packing of above-described embodiment unlike, in further embodiments, do not form light shield layer on a second surface, and resilient coating 107 selects photoresists, photoresists have absorption effects, except alleviating except the impulsive force of passivation layer, light can also be avoided to enter image sensing district from second surface.In these embodiments, it is identical that other processing technologys all lead to above-described embodiment, do not repeat them here.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (17)
1. an image sensing chip-packaging structure, is characterized in that, comprising:
Image sensing chip, it has relative first surface and second surface, the weld pad being provided with image sensing district on the first surface and being positioned at around image sensing district;
From the through through hole to weld pad of second surface;
Be arranged at the passivation layer on through-hole side wall and second surface;
Be arranged at the electrical wiring layer on through hole bottom surface and passivation layer;
Be electrically connected on the pedestal of electrical wiring layer;
Resilient coating between electrical wiring layer and passivation layer.
2. encapsulating structure according to claim 1, is characterized in that, also comprises: light shield layer, to be positioned on second surface and to cover described image sensing district.
3. encapsulating structure according to claim 2, is characterized in that, the material of described light shield layer is metal.
4. encapsulating structure according to claim 3, is characterized in that, described metal is the Al through surperficial Darkening process.
5. encapsulating structure according to claim 1, is characterized in that, the material of described resilient coating is photoresists.
6. encapsulating structure according to claim 1, is characterized in that, also comprises and covers electrical wiring layer and the solder mask of filling vias.
7. encapsulating structure according to claim 1, is characterized in that, also comprises the cover sheet with described image sensing chip contraposition pressing.
8. encapsulating structure according to claim 7, is characterized in that, described cover sheet is optical glass, and at least one of optical glass is provided with anti-reflection layer on the surface.
9. the encapsulating structure according to any one of claim 1-8, is characterized in that, the thickness range of described resilient coating is 5-25 micron.
10. a method for packing for image sensing chip, is characterized in that, comprising:
Wafer is provided, there is the image sensing chip of many array arrangements, it has relative first surface and second surface, the weld pad that image sensing chip has image sensing district and is positioned at around image sensing district, and described image sensing district and weld pad are positioned at first surface;
Cover sheet is provided, and by itself and described Wafer alignment pressing;
The through through hole to weld pad is formed from second surface;
The second surface of through-hole side wall and through hole both sides forms passivation layer;
Passivation layer on a second surface forms resilient coating;
Form the electrical wiring layer covering through-hole wall and resilient coating;
Electrical wiring layer is formed the pedestal be electrically connected with described electrical wiring layer.
11. methods according to claim 10, is characterized in that, before formation through hole, also comprise: form light shield layer in the position in the corresponding image sensing district of second surface.
12. methods according to claim 11, is characterized in that, the step forming light shield layer comprises:
Splash-proofing sputtering metal layer on a second surface, and etch, form light shield layer with the position in corresponding image sensing district.
13. methods according to claim 12, is characterized in that, described metal level is Al, after the metal level of sputtering Al, also carry out surperficial Darkening process, then etch.
14. methods according to claim 10, is characterized in that, after covering electrical wiring layer, before forming pedestal, also comprise:
Form solder mask, and form opening in solder mask on a second surface;
Form pedestal in the opening.
15. methods according to claim 10, is characterized in that, described cover sheet is optical glass, and at least one of optical glass is provided with anti-reflection layer on the surface.
16. methods according to any one of claim 10-15, is characterized in that, the step that the second surface of through-hole side wall and through hole both sides is formed passivation layer comprises:
Deposit passivation layer;
Etching removes the passivation layer of via bottoms.
17. methods according to any one of claim 10-15, it is characterized in that, the material of described resilient coating is photoresists, and step passivation layer on a second surface being formed resilient coating comprises:
Spin coating photoresists on a second surface;
Resilient coating is formed by exposure imaging technique.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/767,096 US20180301488A1 (en) | 2015-10-28 | 2015-10-28 | Image sensing chip packaging structure and packaging method |
| CN201510716297.6A CN105226074A (en) | 2015-10-28 | 2015-10-28 | Image sensing chip-packaging structure and method for packing |
| KR1020187011978A KR20180061298A (en) | 2015-10-28 | 2016-09-19 | Image sensing chip packaging structure and packaging method |
| JP2018521251A JP2018535549A (en) | 2015-10-28 | 2016-09-19 | Image detection chip mounting structure and mounting method |
| PCT/CN2016/099325 WO2017071427A1 (en) | 2015-10-28 | 2016-09-19 | Image sensing chip packaging structure and packaging method |
| TW105132982A TWI594409B (en) | 2015-10-28 | 2016-10-13 | Packaging structure and packaging method for image sensor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510716297.6A CN105226074A (en) | 2015-10-28 | 2015-10-28 | Image sensing chip-packaging structure and method for packing |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105226074A true CN105226074A (en) | 2016-01-06 |
Family
ID=54994917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510716297.6A Pending CN105226074A (en) | 2015-10-28 | 2015-10-28 | Image sensing chip-packaging structure and method for packing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105226074A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017071427A1 (en) * | 2015-10-28 | 2017-05-04 | 苏州晶方半导体科技股份有限公司 | Image sensing chip packaging structure and packaging method |
| CN107482029A (en) * | 2017-09-29 | 2017-12-15 | 华天科技（昆山）电子有限公司 | Imaging sensor and its packaging technology |
| CN109473402A (en) * | 2018-10-11 | 2019-03-15 | 北京工业大学 | A kind of encapsulating structure and production method of image chip |
| CN110649055A (en) * | 2019-09-27 | 2020-01-03 | 华天科技（昆山）电子有限公司 | Wafer-level packaging method and packaging structure for improving glare problem of CIS chip |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101355066A (en) * | 2008-05-26 | 2009-01-28 | 晶方半导体科技（苏州）有限公司 | Packaging structure and manufacturing method thereof |
| CN101699622A (en) * | 2009-11-18 | 2010-04-28 | 晶方半导体科技（苏州）有限公司 | Packaging structure and packaging method of semiconductor device |
| CN102263117A (en) * | 2010-05-26 | 2011-11-30 | 精材科技股份有限公司 | Chip package and method for forming the same |
| CN102610624A (en) * | 2012-03-13 | 2012-07-25 | 苏州晶方半导体股份有限公司 | Method for packaging semiconductor |
| CN102945840A (en) * | 2012-11-22 | 2013-02-27 | 苏州晶方半导体科技股份有限公司 | Semiconductor chip packaging structure and packaging method |
| US20140151840A1 (en) * | 2012-12-04 | 2014-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and Apparatus for CMOS Sensor Packaging |
| US20150041995A1 (en) * | 2011-02-10 | 2015-02-12 | Xintec Inc. | Chip package and fabrication method thereof |
| CN205159327U (en) * | 2015-10-28 | 2016-04-13 | 苏州晶方半导体科技股份有限公司 | Image sensor chip package structure |
-
2015
- 2015-10-28 CN CN201510716297.6A patent/CN105226074A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101355066A (en) * | 2008-05-26 | 2009-01-28 | 晶方半导体科技（苏州）有限公司 | Packaging structure and manufacturing method thereof |
| CN101699622A (en) * | 2009-11-18 | 2010-04-28 | 晶方半导体科技（苏州）有限公司 | Packaging structure and packaging method of semiconductor device |
| CN102263117A (en) * | 2010-05-26 | 2011-11-30 | 精材科技股份有限公司 | Chip package and method for forming the same |
| US20150041995A1 (en) * | 2011-02-10 | 2015-02-12 | Xintec Inc. | Chip package and fabrication method thereof |
| CN102610624A (en) * | 2012-03-13 | 2012-07-25 | 苏州晶方半导体股份有限公司 | Method for packaging semiconductor |
| CN102945840A (en) * | 2012-11-22 | 2013-02-27 | 苏州晶方半导体科技股份有限公司 | Semiconductor chip packaging structure and packaging method |
| US20140151840A1 (en) * | 2012-12-04 | 2014-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and Apparatus for CMOS Sensor Packaging |
| CN205159327U (en) * | 2015-10-28 | 2016-04-13 | 苏州晶方半导体科技股份有限公司 | Image sensor chip package structure |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017071427A1 (en) * | 2015-10-28 | 2017-05-04 | 苏州晶方半导体科技股份有限公司 | Image sensing chip packaging structure and packaging method |
| CN107482029A (en) * | 2017-09-29 | 2017-12-15 | 华天科技（昆山）电子有限公司 | Imaging sensor and its packaging technology |
| CN107482029B (en) * | 2017-09-29 | 2023-12-08 | 华天科技（昆山）电子有限公司 | Image sensor and packaging process thereof |
| CN109473402A (en) * | 2018-10-11 | 2019-03-15 | 北京工业大学 | A kind of encapsulating structure and production method of image chip |
| CN110649055A (en) * | 2019-09-27 | 2020-01-03 | 华天科技（昆山）电子有限公司 | Wafer-level packaging method and packaging structure for improving glare problem of CIS chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105244359A (en) | Image sensing chip packaging structure and packaging method | |
| CN100587962C (en) | Methods and apparatus for packaging integrated circuit devices | |
| US8349707B2 (en) | Process for making contact with and housing integrated circuits | |
| US10249672B2 (en) | Image pickup apparatus, semiconductor apparatus, and image pickup unit | |
| KR100657117B1 (en) | Integrated circuit device and method for manufacturing the same | |
| CN105070734A (en) | Packaging structure and packaging method | |
| US10541262B2 (en) | Image sensing chip packaging structure and packaging method | |
| CN105226074A (en) | Image sensing chip-packaging structure and method for packing | |
| JP2018531519A6 (en) | Image sensing chip packaging structure and packaging method | |
| CN103855173A (en) | Wafer level packaging method and packaging structure for image sensor | |
| KR20190003318A (en) | Protected chip-scale package(csp) pad structure | |
| CN204991711U (en) | Packaging structure | |
| CN205159327U (en) | Image sensor chip package structure | |
| CN205159328U (en) | Sensitization chip package structure | |
| TWI612624B (en) | An encapsulation structure and a method thereof | |
| CN105118843B (en) | Encapsulating structure and packaging method | |
| CN103779245A (en) | Chip packaging method and packaging structure | |
| CN205159326U (en) | Image sensor chip package structure | |
| CN204991710U (en) | Packaging structure | |
| CN205050824U (en) | Packaging structure | |
| CN108010929A (en) | A kind of method for packing of image sensing chip | |
| CN105097724A (en) | Package structure and packaging method | |
| TWI594409B (en) | Packaging structure and packaging method for image sensor chip | |
| TWI612651B (en) | Packaging structure and packaging method | |
| CN203746834U (en) | Packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160106 |
|
| RJ01 | Rejection of invention patent application after publication |