CN109473402A - A kind of encapsulating structure and production method of image chip - Google Patents
A kind of encapsulating structure and production method of image chip Download PDFInfo
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- CN109473402A CN109473402A CN201811181876.5A CN201811181876A CN109473402A CN 109473402 A CN109473402 A CN 109473402A CN 201811181876 A CN201811181876 A CN 201811181876A CN 109473402 A CN109473402 A CN 109473402A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 230000031700 light absorption Effects 0.000 claims abstract description 48
- 239000010410 layer Substances 0.000 claims description 82
- 239000011521 glass Substances 0.000 claims description 16
- 238000005520 cutting process Methods 0.000 claims description 12
- 239000011241 protective layer Substances 0.000 claims description 12
- 230000001154 acute effect Effects 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 230000008033 biological extinction Effects 0.000 claims description 5
- 238000005507 spraying Methods 0.000 claims description 5
- 238000004806 packaging method and process Methods 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000000608 laser ablation Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 238000007639 printing Methods 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000003384 imaging method Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004313 glare Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14685—Process for coatings or optical elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electromagnetism (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
The invention discloses a kind of encapsulating structure of image chip and production methods, belong to field of semiconductor package.The present invention makes light-absorption layer by the position and chip side wall of the non-functional surface face photosensitive area in image chip respectively, light can be effectively inhibited to inject the photodiode of chip device layer by image chip non-functional surface and side wall, the interference light for being incident on photosensitive area is reduced, the quality of imaging is improved.
Description
Technical field
The present invention relates to a kind of semiconductor chip package and production method more particularly to a kind of encapsulation of image chip
Structure and production method, belong to field of semiconductor package.
Background technique
The wafer-level packaging scheme of image chip, at present mainstream be by the photoresist cofferdam on glass cover-plate and its surface with
The wafer functional surfaces of image chip are bonded, and each cofferdam respectively corresponds each image sensor chip so that photosensitive zone position formed it is close
Seal cavity.TSV processing procedure is carried out in wafer non-functional surface, and makes metallic circuit and the weld pad of functional surfaces is open by TSV, is guided to
Wafer non-functional surface.After making salient point in non-functional surface, cutting forms single chip.
But current encapsulation scheme is primarily directed to the imaging device of middle low pixel, with pixel and shooting quality requirement
Raising, for light through glare caused by the photodiode of non-functional surface and side wall intake chip device layer, ghost etc. is existing
As the interference to shooting quality can not be ignored.
Summary of the invention
It in order to solve the above-mentioned technical problem, can the invention proposes a kind of encapsulating structure of image chip and production method
Effectively inhibit light to inject the photodiode of device layer through chip non-functional surface and side wall, reduces and be incident on the dry of device layer
Light is disturbed, image quality is improved.
The technical scheme of the present invention is realized as follows:
A kind of image chip encapsulating structure characterized by comprising
An at least image chip, the image chip are hexahedron, and the image chip contains functional surfaces, corresponding thereto
Non-functional surface and four side walls.The functional surfaces contain photosensitive area and several weld pads.On the functional surfaces of the image chip
The cofferdam of the photosensitive area is protected in bonding one, and a transparent glass cover board is bonded on the cofferdam and covers the photosensitive area.The shadow
As the position of the photosensitive area of the non-functional surface face functional surfaces of chip is covered with the first light-absorption layer, the side wall is covered with the second suction
Photosphere.Each bond pad locations of the non-functional surface face functional surfaces of the image chip are equipped with the first opening, and described first opens
Mouthful and the surface of the non-functional surface successively make and have insulating layer, draw the line layer of the weld pad of functional surfaces and protective layer and lead
Electric salient point.
As a further improvement of the present invention, the image chip encapsulating structure, which is characterized in that first extinction
Layer and the second light-absorption layer are black glue, and brown plated film etc. absorbs the black material of all light.And first light-absorption layer and described
The thickness of second light-absorption layer is greater than 4 μm, less than 10 μm.
As a further improvement of the present invention, the image chip encapsulating structure, which is characterized in that the image chip
The positions of photosensitive area of non-functional surface face functional surfaces cover the first light-absorption layer, the light-absorption layer is covered under insulating layer
Face, the area of first light-absorption layer are greater than the area of photosensitive area.
As a further improvement of the present invention, the image chip encapsulating structure, which is characterized in that the image chip
The exterior normal of side wall and the exterior normal of the non-functional surface between angle be acute angle, and the acute angle be not more than 80 °.
As a further improvement of the present invention, the image chip encapsulating structure, which is characterized in that the image core
The side wall of piece covers the second light-absorption layer, and second light-absorption layer is covered in below the protective layer.And the light-absorption layer and guarantor
Sheath encapsulates the side wall of image chip.
A kind of realization technique of the encapsulating structure of image chip, which comprises the following steps:
Step 1, an image chip wafer is provided, the wafer contains functional surfaces and non-functional surface corresponding thereto.It is described
The functional surfaces of wafer contain the photosensitive area and several chip bonding pads of several image chips；
Step 2, the glass cover-plate contains first surface and second surface corresponding thereto, and the first surface is covered with
One layer of cofferdam；
Step 3, the cofferdam of the functional surfaces of the wafer and the first surface of the glass cover-plate is bonded；
Step 4, the non-functional surface of the wafer is thinned；
Step 5, the non-functional surface of Yu Suoshu wafer makes the first light-absorption layer, wafer described in the first light-absorption layer face
The photosensitive area of functional surfaces；
Step 6, the first opening of each weld pad of the non-functional surface production exposure wafer functional surfaces of Yu Suoshu wafer；
Step 7, the non-functional surface of Yu Suoshu first is open inner wall and the wafer makes insulating layer；
Step 8, patterned metal wiring layer is made on Yu Suoshu insulating layer；
Step 9, the position of the non-functional surface face Cutting Road of Yu Suoshu wafer makes groove, described in the bottom-exposed of groove
Cofferdam；
Step 10, the second light-absorption layer is made in Yu Suoshu groove；
Step 11, protective layer and the second opening are formed on Yu Suoshu metal wiring layer；
Step 12, conductive salient point is formed in the opening of Yu Suoshu second；
Step 13, wafer and glass cover-plate are cut along Cutting Road, forms single image chip packaging body；
As a further improvement of the present invention, a kind of realization technique of image chip encapsulating structure, feature exist
In, the production method of the first light-absorption layer described in step 5 be spin coating or spraying, then exposure development.Second extinction described in step 10
The production method of layer is spraying or printing.
As a further improvement of the present invention, a kind of realization technique of image chip encapsulating structure, feature exist
In the production method of first opening is dry etching, wet etching, cutting, the group of one or more of laser ablation
It closes, the production method of the groove is etching or cutting.
The beneficial effects of the present invention are:
The invention discloses a kind of encapsulating structure of image chip and production methods.The present invention passes through in the non-of image chip
The position of functional surfaces face photosensitive area and chip side wall make light-absorption layer respectively, can effectively inhibit light non-by image chip
The photodiode of functional surfaces and side wall intake chip device layer, the interference light for how arriving photosensitive area reduced, imaging is improved
Quality.
Detailed description of the invention
Fig. 1 is the image chip package structure diagram drawn according to the embodiment of the present invention.
Fig. 2 is the encapsulating structure diagrammatic cross-section after step 1.
Fig. 3 is the encapsulating structure diagrammatic cross-section after step 2.
Fig. 4 is the encapsulating structure diagrammatic cross-section after step 3.
Fig. 5 is the encapsulating structure diagrammatic cross-section after step 4.
Fig. 6 is the encapsulating structure diagrammatic cross-section after step 5.
Fig. 7 is the encapsulating structure diagrammatic cross-section after step 6.
Fig. 8 is the encapsulating structure diagrammatic cross-section after step 7.
Fig. 9 is the encapsulating structure diagrammatic cross-section after step 8.
Figure 10 is the encapsulating structure diagrammatic cross-section after step 9.
Figure 11 is the encapsulating structure diagrammatic cross-section after step 10.
Figure 12 is the encapsulating structure diagrammatic cross-section after step 11.
Figure 13 is the encapsulating structure diagrammatic cross-section after step 12.
Figure 14 is the encapsulating structure diagrammatic cross-section after step 13.
In conjunction with attached drawing, make the following instructions:
1- image chip/wafer 101- image chip functional surfaces
The non-functional surface 103- photosensitive area of 102- image chip
The side wall of 1004- weld pad 105- image chip
106a- light-absorption layer 106b- light-absorption layer
The opening 108- groove of 107- first
The cofferdam 2- 3- glass cover-plate
The second surface of the first surface 302- glass cover-plate of 301- glass cover-plate
4- insulating layer 5- metallic circuit layer
6- protective layer 601- second is open
7- conductive salient point
Specific embodiment
In order to be more clearly understood that technology contents of the invention, spy lifts following embodiment and is described in detail, and cooperates attached
Figure elaborates to features described above and advantage of the invention.Its purpose, which is only that, to be best understood from the contents of the present invention rather than limits
Protection scope of the present invention.The semiconductor package of the embodiment of the present invention can be used for the preparation of micro convex point, but its application is simultaneously
It is without being limited thereto.
Referring to Fig.1, which is the image chip encapsulating structure of embodiment of the present invention, comprising:
An at least image chip (1), the image chip (1) are hexahedron, and the image chip (1) contains functional surfaces
(101), non-functional surface (102) and four side walls (105) corresponding thereto.The functional surfaces contain photosensitive area (103) and
Several weld pads (104).The cofferdam of the one protection photosensitive area (103) of bonding on the functional surfaces (101) of the image chip (1)
(2), a transparent glass cover board (3) is bonded on the cofferdam (2) covers the photosensitive area (103).The image chip (1) it is non-
The position of the photosensitive area (103) of functional surfaces (102) face functional surfaces (101) is covered with the first light-absorption layer (106a), the side wall
(105) it is covered with the second light-absorption layer (106b).Non-functional surface (102) the face functional surfaces (101) of the image chip (1) it is each
A bond pad locations are equipped with the first opening (107), and the surface of first opening (107) and the non-functional surface (102) is successively
Production has insulating layer (4), draws the line layer (5) and protective layer (6) and conductive salient point (7) of the weld pad (104) of functional surfaces.
Optionally, the encapsulating structure of the image chip, which is characterized in that first light-absorption layer (106a) and second is inhaled
Photosphere (106b) is black glue, and brown plated film etc. absorbs the black material of all light.And first light-absorption layer (106a) and institute
The thickness for stating the second light-absorption layer (106b) is greater than 4 μm, less than 10 μm.
Optionally, the encapsulating structure of the image chip, which is characterized in that the non-functional surface of the image chip (1)
(102) position of the photosensitive area (103) of face functional surfaces (101) covers the first light-absorption layer (106a), the light-absorption layer (106a)
It is covered in below insulating layer (4), the area of first light-absorption layer (106a) is greater than the area of photosensitive area (103).
Optionally, the encapsulating structure of the image chip, which is characterized in that the side wall (105) of the image chip (1)
Angle between exterior normal and the exterior normal of the non-functional surface (102) is acute angle, and the acute angle is not more than 80 °.
Optionally, the encapsulating structure of the image chip, which is characterized in that the side wall (105) of the image chip (1)
It covers the second light-absorption layer (106b), second light-absorption layer (106b) is covered in below the protective layer (6).And the extinction
Layer (106b) and protective layer (6) encapsulate the side wall (105) of image chip (1).
Fig. 2~Figure 14 is the schematic diagram for the image chip encapsulating structure production method drawn according to the embodiment of the present invention.
Referring to fig. 2 to Figure 14, image chip encapsulating structure of the invention the production method is as follows:
Step 1, as shown in Fig. 2, provide an image chip wafer (1), the wafer (1) containing functional surfaces (101) and with
Its opposite non-functional surface (102).The functional surfaces (101) of the wafer containing several image chips photosensitive area (103) and if
Dry chip bonding pad (104)；
Step 2, as shown in figure 3, second surface of the glass cover-plate (3) containing first surface (301) and corresponding thereto
(302), the first surface (301) is covered with one layer of cofferdam (2)；
Step 3, as shown in figure 4, by the first surface of the functional surfaces (101) of the wafer (1) and the glass cover-plate (3)
(301) cofferdam (2) bonding；
Step 4, as shown in figure 5, the non-functional surface (102) of the wafer (1) is thinned；
Step 5, described as shown in fig. 6, the non-functional surface (102) in the wafer (1) makes the first light-absorption layer (106a)
The photosensitive area (103) of wafer (1) functional surfaces (102) described in first light-absorption layer (106a) face；
Step 6, as shown in fig. 7, the function of non-functional surface (102) the production exposure wafer (1) in the wafer (1)
First opening (107) of each weld pad (104) in face (101)；
Step 7, as shown in figure 8, in the inner wall of first opening (107) and the non-functional surface (102) of the wafer (1)
It makes insulating layer (4)；
Step 8, as shown in figure 9, in making patterned metal wiring layer (5) on the insulating layer (4)；
Step 9, as shown in Figure 10, the position of non-functional surface (102) face Cutting Road of Yu Suoshu wafer (1) makes groove
(108), cofferdam (2) described in the bottom-exposed of groove (108)；
Step 10, as shown in figure 11, the second light-absorption layer (106b) is made in Yu Suoshu groove (108)；
Step 11, as shown in figure 12, protective layer (6) and the second opening (601) are formed on Yu Suoshu metal wiring layer (5)；
Step 12, as shown in figure 13, conductive salient point (7) are formed in the opening of Yu Suoshu second (601)；
Step 13, as shown in figure 14, wafer (1) and glass cover-plate (3) are cut along Cutting Road, forms single image core
Piece packaging body；
Optionally, the production method of the encapsulating structure of the image chip, which is characterized in that the first extinction described in step 5
The production method of layer (106a) is spin coating or spraying, is exposed, development.The production method of second light-absorption layer (106b) described in step 10
To spray or printing.
Optionally, the production method of the encapsulating structure of the image chip, which is characterized in that first opening (107)
Production method be dry etching, wet etching, cutting, the combination of one or more of laser ablation, the groove (108)
Production method be etching or cutting.
Although the embodiment of the present invention discloses as above, present invention is not limited to this.Anyone skilled in the art, not
It is detached from the spirit and scope of the present invention, can make various changes or modifications, therefore protection scope of the present invention should be with right
It is required that subject to limited range.
Claims (8)
1. a kind of encapsulating structure of image chip, which is characterized in that including an at least image chip (1), the image chip (1)
For hexahedron, the image chip (1) contains functional surfaces (101), non-functional surface (102) and four sides corresponding thereto
Wall (105)；The functional surfaces contain photosensitive area (103) and several weld pads (104)；The functional surfaces (101) of the image chip (1)
The cofferdam (2) of the photosensitive area (103) is protected in upper bonding one, and a transparent glass cover board (3) covering institute is bonded on the cofferdam (2)
State photosensitive area (103)；The position of the photosensitive area (103) of non-functional surface (102) the face functional surfaces (101) of the image chip (1)
It sets and is covered with the first light-absorption layer (106a), the side wall (105) is covered with the second light-absorption layer (106b)；The image chip (1)
Each bond pad locations of non-functional surface (102) face functional surfaces (101) be equipped with the first opening (107), first opening
(107) and the surface of the non-functional surface (102) successively makes insulating layer (4), draws the route of the weld pad (104) of functional surfaces
Layer (5) and protective layer (6) and conductive salient point (7).
2. image chip encapsulating structure according to claim 1, which is characterized in that first light-absorption layer (106a) and
Two light-absorption layers (106b) are the black material that can absorb all light；And first light-absorption layer (106a) and second extinction
The thickness of layer (106b) is greater than 4 μm, less than 10 μm.
3. image chip encapsulating structure according to claim 1, which is characterized in that the image chip (1) it is non-functional
The position of the photosensitive area (103) of face (102) face functional surfaces (101) covers the first light-absorption layer (106a), the light-absorption layer
(106a) is covered in below insulating layer (4), and the area of first light-absorption layer (106a) is greater than the area of photosensitive area (103).
4. the encapsulating structure of image chip according to claim 1, which is characterized in that the side wall of the image chip (1)
(105) angle between the exterior normal of exterior normal and the non-functional surface (102) is acute angle, and the acute angle is not more than 80 °.
5. image chip encapsulating structure according to claim 1, which is characterized in that the side wall of the image chip (1)
(105) the second light-absorption layer (106b) is covered, second light-absorption layer (106b) is covered in below the protective layer (6)；And institute
Light-absorption layer (106b) and protective layer (6) is stated to encapsulate the side wall (105) of image chip (1).
6. a kind of production method of the encapsulating structure of image chip, which comprises the following steps:
Step 1, an image chip wafer (1) is provided, the wafer (1) is non-functional containing functional surfaces (101) and corresponding thereto
Face (102)；The functional surfaces (101) of the wafer contain the photosensitive area (103) and several chip bonding pads of several image chips
(104)；
Step 2, the second surface (302) of the glass cover-plate (3) containing first surface (301) and corresponding thereto, described first
Surface (301) is covered with one layer of cofferdam (2)；
Step 3, by the cofferdam (2) of the functional surfaces (101) of the wafer (1) and the first surface (301) of the glass cover-plate (3)
Bonding；
Step 4, the non-functional surface (102) of the wafer (1) is thinned；
Step 5, the non-functional surface (102) of Yu Suoshu wafer (1) makes the first light-absorption layer (106a), first light-absorption layer
The photosensitive area (103) of wafer (1) functional surfaces (102) described in (106a) face；
Step 6, the functional surfaces (101) of non-functional surface (102) the production exposure wafer (1) of Yu Suoshu wafer (1) is each
First opening (107) of weld pad (104)；
Step 7, the non-functional surface (102) of the inner wall and the wafer (1) of the opening of Yu Suoshu first (107) makes insulating layer (4)；
Step 8, patterned metal wiring layer (5) are made on Yu Suoshu insulating layer (4)；
Step 9, the position of non-functional surface (102) face Cutting Road of Yu Suoshu wafer (1) makes groove (108), groove (108)
Bottom-exposed described in cofferdam (2)；
Step 10, the second light-absorption layer (106b) is made in Yu Suoshu groove (108)；
Step 11, protective layer (6) and the second opening (601) are formed on Yu Suoshu metal wiring layer (5)；
Step 12, conductive salient point (7) are formed in the opening of Yu Suoshu second (601)；
Step 13, wafer (1) and glass cover-plate (3) are cut along Cutting Road, forms single image chip packaging body.
7. a kind of production method of the encapsulating structure of image chip according to claim 6, which is characterized in that step 5 institute
The production method for stating the first light-absorption layer (106a) is spin coating or spraying, then exposure development；Second light-absorption layer described in step 10
The production method of (106b) is spraying or printing.
8. a kind of production method of the encapsulating structure of image chip according to claim 6, which is characterized in that described first
The production method of opening (107) is dry etching, and wet etching is cut, and the combination of one or more of laser ablation is described
The production method of groove (108) is etching or cutting.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811181876.5A CN109473402A (en) | 2018-10-11 | 2018-10-11 | A kind of encapsulating structure and production method of image chip |
| PCT/CN2018/112618 WO2020073371A1 (en) | 2018-10-11 | 2018-10-30 | Packaging structure of image chip and manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811181876.5A CN109473402A (en) | 2018-10-11 | 2018-10-11 | A kind of encapsulating structure and production method of image chip |
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| CN109473402A true CN109473402A (en) | 2019-03-15 |
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| CN201811181876.5A Pending CN109473402A (en) | 2018-10-11 | 2018-10-11 | A kind of encapsulating structure and production method of image chip |
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| WO (1) | WO2020073371A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110197835A (en) * | 2019-07-05 | 2019-09-03 | 中国电子科技集团公司第五十八研究所 | A kind of method for packaging photoelectric device and encapsulating structure |
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