CN105097724A - Package structure and packaging method - Google Patents
Package structure and packaging method Download PDFInfo
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- CN105097724A CN105097724A CN201510496625.6A CN201510496625A CN105097724A CN 105097724 A CN105097724 A CN 105097724A CN 201510496625 A CN201510496625 A CN 201510496625A CN 105097724 A CN105097724 A CN 105097724A
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- upper cover
- cover plate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
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Abstract
The invention provides a package structure and a packaging method. The package structure comprises a chip unit and an upper cover plate structure, wherein the first surface of the chip unit comprises a sensing area; the first surface of the upper cover plate structure has a groove structure; the first surface of the chip unit is oppositely bonded with the first surface of the upper cover plate structure, and the sensing area is positioned within the cavity encircled by the groove structure and the first surface of the chip unit; the upper cover plate structure further comprises a second surface opposite to the first surface, and the second surface of the upper cover plate structure is smaller than the first surface. The package structure and the packaging method can reduce interference rays shot to the sensing area.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of encapsulating structure and a kind of method for packing.
Background technology
On conventional art, the connection of IC chip and external circuit is realized by the mode of metal lead wire bonding (WireBonding).Along with the expansion with footprint of reducing of IC chip feature sizes, Wire Bonding Technology is no longer applicable.
Wafer stage chip encapsulation (WaferLevelChipsizePackaging, WLCSP) technology is that after carrying out packaging and testing to full wafer wafer, cutting obtains the technology of single finished product chip again, and the chip size after encapsulation is consistent with nude film.Wafer stage chip encapsulation technology has overturned the pattern of conventional package as ceramic leadless chip carrier (CeramicLeadlessChipCarrier), organic leadless chip carrier (OrganicLeadlessChipCarrier), has complied with that market is day by day light, little, short to microelectronic product, thinning and low priceization requirement.Chip after the encapsulation of wafer stage chip encapsulation technology reaches highly microminiaturized, and chip cost significantly reduces along with the reduction of chip and the increase of wafer size.Wafer stage chip encapsulation technology be IC can be designed, wafer manufacture, packaging and testing, the technology that integrates, be focus and the development trend in current encapsulation field.
Image sensor dice is as a kind of chip that optical imagery can be converted to electronic signal, and it has induction region.When utilizing existing wafer stage chip encapsulation technology to encapsulate image sensor dice, in order to protect above-mentioned induction region injury-free and pollute in encapsulation process, usually a upper cover substrate can be formed in induction region position.Described upper cover substrate, after completing wafer stage chip encapsulation, can continue to retain, and protects induction region from damage and pollution in the use procedure relaying continuation of insurance of image sensor dice.
But the image sensor performance adopting above-mentioned wafer stage chip encapsulation technology to be formed is not good.
Summary of the invention
The problem that the present invention solves is that the image sensor performance that prior art is formed is not good.
For solving the problem, embodiments provide a kind of encapsulating structure.Described encapsulating structure comprises: chip unit, and the first surface of described chip unit comprises induction region; And upper cover plate structure, the first surface of described upper cover plate structure has multiple groove structure; Wherein, the first surface of described chip unit is relative with the first surface of described upper cover plate structure combines, within the cavity that the first surface that described induction region is positioned at described groove structure and described chip unit surrounds; Described upper cover plate structure also comprises the second surface relative with first surface, and the area of described upper cover plate structure second surface is less than the area of first surface.
Alternatively, described upper cover plate structure also comprises sidewall, and described sidewall comprises vertical wall and inclined wall, the edge conjunction of the first end of described inclined wall and the second surface of described upper cover plate structure, and its second relative end is connected with the top of described vertical wall.
Alternatively, the angle between described inclined wall and described vertical wall is 120 ° ~ 150 °.
Alternatively, the difference in height of described vertical wall top and described upper cover plate structure second surface is determined based on the refractive index of the thickness of described upper cover plate structure, distance between described sunk structure madial wall and described upper cover plate structure vertical wall and described upper cover plate structure.
Alternatively, the difference in height of described vertical wall top and described upper cover plate structure second surface is 1/5 ~ 4/5 of described upper cover plate structural thickness.
Alternatively, the material of described upper cover plate structure is light transmissive material.
Alternatively, the material of described upper cover plate structure is unorganic glass or polymethyl methacrylate, and thickness is 300 μm ~ 500 μm.
Alternatively, described chip unit also comprises: be positioned at the weld pad outside described induction region; Run through the through hole of described chip unit from the second surface relative with first surface of described chip unit, described through hole exposes described weld pad; Cover the insulating barrier on described chip unit second surface and described through-hole side wall surface; Be positioned at described surface of insulating layer and the metal level be connected with described weld pad electricity; Be positioned at the solder mask of described metal level and described surface of insulating layer, described solder mask has the opening exposing the described metal level of part; Fill described opening, and be exposed to the external projection outside described solder mask surface.
Corresponding to above-mentioned encapsulating structure, the embodiment of the present invention additionally provides a kind of method for packing, described method for packing comprises: provide wafer to be wrapped, the first surface of described wafer to be wrapped comprises multiple chip unit and the Cutting Road region between chip unit, and described chip unit comprises induction region; There is provided capping substrate, form multiple groove structure at the first surface of described capping substrate, described groove structure is corresponding with the induction region on described wafer to be wrapped; Combine relative with the first surface of described wafer to be wrapped for the first surface of described capping substrate, make the first surface of described groove structure and described wafer to be wrapped surround cavity, described induction region is positioned at described cavity; Along described Cutting Road region, described wafer to be wrapped and described capping substrate are cut, form multiple chip-packaging structure, described chip-packaging structure comprises described chip unit and is positioned at the upper cover plate structure formed by the described capping substrate of cutting on described chip unit, described upper cover plate structure comprises the first surface and the second surface relative with described first surface that are positioned at described chip unit side, and described cutting makes the area of the second surface of described upper cover plate structure be less than the area of first surface.
Alternatively, carry out cutting along described Cutting Road region to described wafer to be wrapped and described capping substrate to comprise: perform the first cutting technique, comprise and cutting from the second surface relative with first surface of described wafer to be wrapped along described Cutting Road region, until the first surface arriving described wafer to be wrapped forms the first cutting groove; Perform the second cutting technique, comprise and from the second surface relative with first surface of described capping substrate, cut arrival predetermined depth along described Cutting Road region, form the second cutting groove, the width of described second cutting groove reduces gradually along the direction from the second surface of described capping substrate to first surface; And perform the 3rd cutting technique, comprise and continue the described capping substrate of cutting, until form the 3rd cutting groove of through described first cutting groove and described second cutting groove, form multiple chip-packaging structure simultaneously.
Alternatively, described predetermined depth is determined based on the refractive index of the thickness of the upper cover plate structure of described chip-packaging structure, the distance between described sunk structure madial wall and described upper cover plate structure side wall and described upper cover plate structure.
Alternatively, described predetermined depth is 1/5 ~ 4/5 of described capping substrate thickness.
Alternatively, described second cutting technique adopts drilling bit grinding technique, and the section of the second cutting groove that described second cutting technique is formed is del, inverted trapezoidal, circular arc or parabola shaped.
Alternatively, described second cutting technique adopts drilling bit grinding technique.
Alternatively, the described second angle cut between the sidewall of groove and the second surface of described capping substrate is 120 ° ~ 150 °.
Alternatively, described chip unit also comprises weld pad, described weld pad is positioned at outside described induction region, after being combined with the first surface of described wafer to be wrapped by the first surface of described capping substrate, described method for packing also comprises: carry out thinning from the second surface relative with first surface of described wafer to be wrapped; Etch described wafer to be wrapped from the second surface of described wafer to be wrapped, form through hole, described through hole exposes the weld pad of described chip unit; Insulating barrier is formed at the second surface of described wafer to be wrapped and the sidewall surfaces of through hole; The metal level connecting weld pad is formed at described surface of insulating layer; Form the solder mask with opening at described layer on surface of metal and surface of insulating layer, described opening exposes Metallschicht; Form external projection on the surface at described solder mask, described external projection fills described opening.
Compared with prior art, the technical scheme of the embodiment of the present invention has the following advantages:
The area of the second surface of the upper cover plate structure of the encapsulating structure of the embodiment of the present invention is less than the area of first surface.Such as, the sidewall of described upper cover plate structure includes vertical wall and inclined wall, the edge conjunction of the first end of described inclined wall and the second surface of described upper cover plate structure, and its second relative end is connected with the top of described vertical wall.Compared with the encapsulating structure of prior art, the side wall construction with inclined wall can make the light originally occurring to reflect on described sidewall can not enter upper cover plate structure again, decrease the interference light entering induction region from described upper cover plate structure side wall reflection, thus the image quality of the chip-packaging structure as image sensor can be improved.
Further, the difference in height of vertical wall top described in encapsulating structure of the present invention and described upper cover plate structure second surface is determined based on the refractive index of the thickness of described upper cover plate structure, the distance between described sunk structure madial wall and described upper cover plate structure side wall and described upper cover plate structure, the top surface that can only expose to described cavity wall of the sidewall total reflection light from described upper cover plate structure can be made, and described induction region can not be exposed to, further reduce the interference light entering described induction region.
Accordingly, the method for packing of the embodiment of the present invention also has above-mentioned advantage.
Accompanying drawing explanation
Fig. 1 shows the cross-sectional view of the image sensor dice of prior art;
Fig. 2 to Fig. 9 shows the structural representation of the intermediate structure formed in one embodiment of the invention method for packing;
Figure 10 shows the cross-sectional view of the encapsulating structure of one embodiment of the invention;
Figure 11 shows the partial enlarged drawing of the encapsulating structure shown in Figure 10.
Embodiment
From background technology, the performance of the image sensor that prior art is formed is not good.
The present inventor adopts wafer stage chip encapsulation technology to be studied the technique that image sensor dice encapsulates to prior art, the reason that the performance of the image sensor that discovery prior art is formed is not good is, the upper cover substrate be formed in chip package process on induction region can produce interference to the light entering induction region, reduces image quality.
Particularly, the cross-sectional view of the image sensor dice that prior art is formed is shown with reference to figure 1, Fig. 1.Described image sensor dice comprises: substrate 10; Be positioned at the induction region 20 of described substrate 10 first surface; Be positioned at described substrate 10 first surface, the weld pad 21 of described induction region 20 both sides; Run through the through hole (sign) of described substrate 10 from the second surface relative with described first surface of described substrate 10, described through hole exposes described weld pad 21; Be positioned at the insulating barrier 11 of described through-hole side wall and substrate 10 second surface; The line layer 12 of described weld pad 21 and partial insulative layer 11 is covered from described second surface; Cover the solder mask 13 of described line layer 12 and insulating barrier 11, described solder mask 13 has opening; Be positioned at the soldered ball 14 that described solder mask 13 opening is connected with described weld pad 21 electricity by described line layer 12; Cavity wall 31 around the induction region 20 being positioned at described substrate 10 first surface; And the upper cover substrate 30 be positioned on described cavity wall.Described upper cover substrate 30 forms cavity with the first surface of cavity wall 21 and substrate 10, makes described inductor 20 be positioned at described cavity, avoids induction zone 20 polluted in encapsulation and use procedure and damage.The thickness of usual described upper cover substrate 30 is comparatively large, such as 400 microns.
The present inventor finds, in the use procedure of above-mentioned image sensor dice, the upper cover substrate 30 of light I1 incidental image image-position sensor, the some light I2 entering upper cover substrate 30 can expose to the sidewall 30s of upper cover substrate 30, produce refraction and reflex, if reflection ray is incident to described induction region 20, interference will be caused to the imaging of image sensor.Especially, if the incident angle of light I2 meets specified conditions, such as, when described upper cover substrate 30 is glass, glass is outward air, and when the incidence angle of described light I2 to be greater than by glass to the critical angle of air, total reflection can be there is in described light I2 at the sidewall 30s place of described upper cover substrate 30, total reflection light I2 propagates in described upper cover substrate 30, until expose to described induction region 20, can cause severe jamming to described induction region 20.In the imaging process of concrete image sensor, described interference is presented as and forms the virtual image in the opposite direction of total reflection light I2 light path, reduces image quality.
In addition, along with the miniaturization trend of wafer stage chip encapsulation, the packaging body of sensor chip integrated on wafer stage chip is more, and the size of single finished product chip packing-body is less, the distance at upper cover substrate 30 sidewall and edge, induction zone 20 is also more and more nearer, and above-mentioned interference phenomenon is also more obvious.
Based on above research, the encapsulating structure embodiments providing a kind of method for packing and formed by described method for packing.Described method for packing comprises provides wafer to be wrapped and capping substrate respectively, combine relative with described wafer to be wrapped for described capping substrate, induction region on described wafer to be wrapped is positioned at the cavity that the groove structure of capping substrate and wafer to be wrapped surround, then carry out cutting to described wafer to be wrapped and described capping substrate along the Cutting Road region on described wafer to be wrapped and form single chip-packaging structure, described chip-packaging structure comprises described chip unit and is positioned at the upper cover plate structure formed by the described upper cover substrate of cutting on described chip unit, and in above-mentioned cutting process, described upper cover plate structure is made to be less than the area of the first surface near chip unit away from the area of the second surface of chip unit.The area of the second surface of described upper cover plate structure is less than the area of first surface, such as, the angle part that can form for the second surface of described upper cover plate structure and sidewall is removed, make to reduce from the light of the second surface incidence of described upper cover plate structure in the reflection of the sidewall of described upper cover plate structure, the reverberation entering light sensing region also reduces, thus can improve the image quality of the chip-packaging structure as image sensor.Accordingly, the encapsulating structure formed by above-mentioned method for packing also has above-mentioned advantage.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
It should be noted that, provide the object of these accompanying drawings to be contribute to understanding embodiments of the invention, and should not be construed as and limit improperly of the present invention.For the purpose of clearer, size shown in figure not drawn on scale, may make and amplify, to reduce or other change.
The embodiment of the present invention provide firstly a kind of method for packing, please refer to Fig. 2 to Fig. 9, is the structural representation of the encapsulation process of the image sensor dice of the embodiment of the present invention.
First, with reference to figure 2 and 3, provide wafer to be wrapped 200, wherein, Fig. 2 is the plan structure schematic diagram of described wafer to be wrapped 200, and Fig. 3 is the cutaway view of Fig. 2 along AA1.
Described wafer to be wrapped 200 has first surface 200a and the second surface 200b relative relative to 200a with described first surface.The first surface 200a of described wafer to be wrapped 200 have multiple chip unit 210 and the Cutting Road region 220 between described chip unit 210.
In the present embodiment, multiple chip units 210 on described wafer to be wrapped 200 are arranged in array, described Cutting Road region 220 is between adjacent chip unit 210, follow-uply along described Cutting Road region 220, described wafer to be wrapped 200 to be cut, multiple chip-packaging structure comprising described chip unit 210 can be formed.
In the present embodiment, described chip unit 210 is image sensor chip unit, the weld pad 212 that described chip unit 210 has induction zone 211 and is positioned at outside described induction region 211.Described induction region 211 is optical sensor district, and such as, can be arranged by multiple photodiode array and be formed, the optical signalling exposing to described induction region 211 can be converted into electrical signal by described photodiode.The input and output side that described weld pad 212 is connected with external circuit as device in described induction region 211.In certain embodiments, described chip unit 210 is formed on silicon substrate, and described chip unit 210 can also comprise other function elements be formed in silicon substrate.
It should be noted that, in the subsequent step of the method for packing of the embodiment of the present invention, for the purpose of simple and clear, be only described for the sectional view in the AA1 direction along described wafer to be wrapped 200 shown in Fig. 2, perform similar processing step in other regions.
Then, with reference to figure 4, capping substrate 300 is provided, described capping substrate 300 comprises first surface 300a and the second surface 300b relative with described first surface 300a, form multiple groove structure 310 at the first surface 300a of described capping substrate 300, described groove structure 310 is corresponding with the induction region 211 on described wafer to be wrapped 200.
In the present embodiment, described capping substrate 300 covers the first surface 200a of described wafer to be wrapped 200 in subsequent technique, for protecting the induction region 211 on described wafer to be wrapped 200.Because capping substrate 300 described in needs light therethrough arrives induction region 211, therefore, described capping substrate 300 has higher light transmission, is light transmissive material.Two surperficial 300a and 300b of described capping substrate 300 are all smooth, smooth, can not produce scattering, diffuse reflection etc. to incident ray.
Particularly, described capping substrate 300 material can for unorganic glass, polymethyl methacrylate or other there is the light transmissive material of certain strength.In the present embodiment, the thickness of described capping substrate 300 is 300 μm ~ 500 μm, such as, can be 400 μm.If the thickness of described capping substrate 300 is excessive, the thickness of the final chip-packaging structure formed can be caused excessive, the demand of thin lightization of electronic product can not be met; If the thickness of described capping substrate 300 is too small, then the intensity of capping substrate 300 can be caused less, easily damage, enough protective effects can not be played to follow-up covered induction region.
In the present embodiment, define multiple groove structure 310 at the first surface 300a of described capping substrate 300.Described groove structure 310 is surrounded with the cavity wall 320 be positioned on described first surface 300a by the first surface 300a of described capping substrate 300.
The present embodiment, described cavity wall 320 etches formation by deposit cavity wall material layer on the first surface 300a of described capping substrate 300 after.Particularly, first form the cavity wall material layer (not shown) covering described capping substrate 300 first surface 300a, then carry out graphically to described cavity wall material layer, remove the described cavity wall material layer of part, form described cavity wall 320.The first surface 300a of described cavity wall 320 and the described capping substrate 300 between cavity wall 320 constitutes groove structure 310.The position of described groove structure 310 on described capping substrate 300 and described induction region 211 position on described wafer to be wrapped 200 is corresponding, thus makes after follow-up combined process, and described induction region 211 can be positioned at described groove structure 310.In certain embodiments, the material of described cavity wall material layer is wet film or dry film photoresist, by spraying, spin coating or the technique such as to paste and formed, described cavity wall material layer is exposed and development carry out graphical after form described cavity wall 320.In certain embodiments, described cavity wall material layer can also be the insulating dielectric materials such as silica, silicon nitride, silicon oxynitride, and formed by depositing operation, follow-up employing photoetching and etching technics carry out graphically forming described cavity wall 320.
In some other embodiment, described cavity wall 320 can also by etching rear formation to described capping substrate 300.Particularly, patterned photoresist layer can be formed on described capping substrate 300, and then with described patterned photoresist layer for capping substrate 300 described in mask etching, in described capping substrate 300, form described groove structure 310, described cavity wall 320 is the bossing on described capping substrate 300 first surface 300a.
Then, with reference to figure 5, the first surface 300a of described capping substrate 300 is relative with the first surface 200a of described wafer to be wrapped 200 and combine, make described groove structure 310 surround cavity (sign) with the first surface 200a of described wafer to be wrapped 200, described induction region 211 is positioned at described cavity.
In the present embodiment, by adhesive layer (not shown), described capping substrate 300 and described wafer to be wrapped 200 are combined.Such as, can on the top surface of the cavity wall 320 of described capping substrate 300 first surface 300a, and/or on the first surface 200a of described wafer to be wrapped 200, described adhesive layer is formed by spraying, spin coating or the technique pasted, again by the first surface 200a relative pressing of the first surface 300a of described capping substrate 300 with described wafer to be wrapped 200, combined by described adhesive layer.Described adhesive layer both can realize bonding effect, can play again insulation and sealing function.Described adhesive layer can be the polymeric materials such as polymeric adhesion material, such as silica gel, epoxy resin, benzocyclobutene.
In the present embodiment, after relative with the first surface 200a of described wafer to be wrapped 200 for the first surface 300a of described capping substrate 300 combination, described groove structure 310 surrounds cavity with the first surface 200a of described wafer to be wrapped 200.The position of described cavity is corresponding with the position of described induction region 211, and described cavity area is slightly larger than the area of described induction region 211, and described induction region 211 can be made to be positioned at described cavity.In the present embodiment, after described capping substrate 300 and described wafer to be wrapped 200 being combined, the weld pad 212 on described wafer to be wrapped 200 is covered by the cavity wall 320 on described capping substrate 300.Described capping substrate 300 in subsequent technique, can play the effect protecting described wafer to be wrapped 200.
Then, with reference to figure 6, encapsulation process is carried out to described wafer to be wrapped 200.
Particularly, first, carry out thinning from the second surface 200b of described wafer to be wrapped 200 to described wafer to be wrapped 200, so that the etching of follow-up through hole, can mechanical lapping, chemical mechanical milling tech etc. be adopted to the thinning of described wafer to be wrapped 200; Then, etch from the second surface 200b of described wafer to be wrapped 200 described wafer to be wrapped 200, form through hole (sign), described through hole exposes the weld pad 212 of described wafer to be wrapped 200 first surface 200a side; Then, insulating barrier 213 is formed on the second surface 200b of described wafer to be wrapped 200 and on the sidewall of described through hole, described insulating barrier 213 exposes the weld pad 212 of described via bottoms, described insulating barrier 213 can provide electric insulation for the second surface 200b of described wafer to be wrapped 200, the substrate of the described wafer to be wrapped 200 that can also expose for described through hole provides electric insulation, and the material of described insulating barrier 213 can be silica, silicon nitride, silicon oxynitride or insulating resin; Then, the metal level 214 connecting described weld pad 212 is formed on described insulating barrier 213 surface, described metal level 214 can as wiring layer again, described weld pad 212 is caused on the second surface 200b of described wafer to be wrapped 200, be connected with external circuit again, described metal level 214 through deposit metal films and to the etching of metallic film after formed; Then, the solder mask 215 with opening (sign) is formed on described metal level 214 surface and described insulating barrier 213 surface, described opening exposes the surface of the described metal level 214 of part, the material of described solder mask 215 is the insulating dielectric materials such as silica, silicon nitride, for the protection of described metal level 214; Again then, the surface of described solder mask 215 forms external protruding 216, described external protruding 216 fill described opening, and described external protruding 216 can be the syndeton such as soldered ball, metal column, and material can be the metal materials such as copper, aluminium, gold, tin or lead.
After carrying out encapsulation process to described wafer to be wrapped 200, the chip-packaging structure that follow-up cutting can be made to obtain is connected with external circuit by described external protruding 216.The induction region 211 of described chip unit is after being converted to the signal of telecommunication by light signal, and the described signal of telecommunication can pass through described weld pad 212, metal level 214 and external protruding 216 successively, transfers to external circuit and processes.
Then, with reference to figure 7 to Fig. 9, the Cutting Road region 220 (simultaneously with reference to figure 3) along described wafer to be wrapped 200 is cut described wafer to be wrapped 200 and described capping substrate 300, forms multiple chip-packaging structure as shown in Figure 10.With reference to Figure 10, described chip-packaging structure comprises chip unit 210 and is positioned at the upper cover plate structure 330 formed by the described capping substrate 300 of cutting on described chip unit 210, described upper cover plate structure 330 comprises the first surface 330a and the second surface 330b relative with described first surface 330a that are positioned at described chip unit 210 side, and above-mentioned cutting makes the area of the second surface 330b of described upper cover plate structure 330 be less than the area of first surface 330a.
In the present embodiment, the first cutting technique, the second cutting technique and the 3rd cutting technique are included to the cutting of described wafer to be wrapped 200 and described capping substrate 300.Particularly, with reference to figure 7, first, perform the first cutting technique, described first cutting technique cuts from the second surface 200b of described wafer to be wrapped 200 along Cutting Road region 220 as shown in Figure 3, until the first surface 200a arriving described wafer to be wrapped 200 forms the first cutting groove 410.Described first cutting technique can adopt slicer to cut or laser cutting, and described slicer cutting can adopt steel edge or resin cutter.
Then, with reference to figure 8, perform the second cutting technique, described second cutting technique cuts from the second surface 300b of described capping substrate 300 along the region corresponding with the Cutting Road region 220 described in Fig. 3, until arrival predetermined depth, form the second cutting groove 420, the width of described second cutting groove 420 reduces gradually along the direction from the second surface 300b of described capping substrate 300 to first surface 300a.In certain embodiments, described second cutting technique adopts drilling bit grinding technique, described drilling bit grinding technique is also mobile at the second surface 300b spin finishing of described capping substrate 300 after adopting the drill bit pressurization with given shape, forms described second cutting groove 420.The top width of described drill bit is less than low side width, and the formed width of the second cutting groove 420 from the second surface 300b of described capping substrate 300 to first surface 300a can be made to reduce gradually.According to the shape of drill bit, the section shape of described second cutting groove 420 can be del, inverted trapezoidal, circular arc or parabola shaped etc., and the described second angle cut between the sidewall of groove 420 and the second surface 300b of described capping substrate 300 is 120 ° ~ 150 °.In the present embodiment, the angle between the sidewall of described second cutting groove 420 and the second surface 300b of described capping substrate 300 is 135 °.The predetermined depth of described second cutting groove 420 is 1/5 ~ 4/5 of described capping substrate 300 thickness.Such as, in the present embodiment, the predetermined depth of described second cutting groove 420 is 1/2 of described capping substrate 300 thickness.
Then, with reference to figure 9, perform the 3rd cutting technique, in certain embodiments, described 3rd cutting technique continues the described capping substrate 300 of cutting along described second cutting groove 420, until the first surface 200a arriving described wafer to be wrapped 200 forms the 3rd cutting groove 430.The through described second cutting groove 420 of described 3rd cutting groove 430 and described first cutting groove 410, thus complete whole cutting technique, form multiple chip-packaging structure.Described 3rd cutting technique also can adopt slicer to cut or laser cutting.But it should be noted that, the width of the 3rd cutting groove 430 that described 3rd cutting technique is formed should be less than the mean breadth of described second cutting groove 420.
In some other embodiment, described 3rd cutting technique also can continue the described capping substrate 300 of cutting along described first cutting groove 410, until form the 3rd cutting groove 430 of through described first groove 410 and described second groove 420.
After above-mentioned cutting technique, define chip-packaging structure as shown in Figure 10.Be described the course of work of the chip-packaging structure shown in Figure 10 below in conjunction with Figure 11, Figure 11 is the partial enlarged drawing of part in dotted line frame in Figure 10.Above-mentioned cutting technique makes the area of the second surface 330b of described upper cover plate structure 330 be less than the area of first surface 330a, and particularly, the angle part that in the present embodiment, namely the second surface 330b of described upper cover plate structure 330 and sidewall are formed is removed.The sidewall of the final chip-packaging structure formed is made to include vertical wall 330s and inclined wall 330t, the edge conjunction of the first end of described inclined wall 330t and the second surface 330b of described upper cover plate structure 330, its second relative end is connected with the top of described vertical wall 330s.Compared with the image sensor formed with the prior art shown in Fig. 1, in FIG, can there is total reflection at the sidewall 30s of image sensor in identical incident ray I1, the imaging of interference induction region 20; And with reference to Figure 11, in the chip-packaging structure of the embodiment of the present invention, the angle part formed due to second surface 330b and the vertical wall 330s of described upper cover plate structure 330 is removed, and described light I1 can incident described upper cover plate 330, also would not produce interference to induction region 211.
It should be noted that, the angle part that the inclined wall 330t in described upper cover plate structure 330 and vertical wall 330s is formed is formed in the second above-mentioned cutting technique, and its shape also depends on the shape of described second cutting groove 420 (with reference to figure 9).With reference to Figure 11, in certain embodiments, above-mentioned second cutting groove 420 predetermined depth based on the thickness of upper cover plate structure 330 in described chip-packaging structure, described sunk structure madial wall (in the present embodiment namely described cavity wall 320 near the sidewall of induction region 211) to described upper cover plate structure 330 sidewall 330s between distance d and the refractive index of described upper cover plate structure 330 determine.
Particularly, the air outside the refractive index of described upper cover plate structure 330 and upper cover plate structure 330 or the refractive index of other media determine the critical angle that total reflection occurs at described sidewall 330 place the light being incident to described upper cover plate structure 330.Continue with reference to Figure 11, in the present embodiment, suppose that described critical angle is α, described cavity wall 320 near induction region 211 sidewall to upper cover plate structure 330 sidewall 330s between distance d, and the sidewall 330s of described upper cover plate structure 330 is vertical with the top surface of described cavity wall 320, when the incidence angle of some light on described sidewall 330s of the incident described upper cover plate structure 330 of light I3 is α, the angle of the top surface of reflection ray I4 and described cavity wall 320 is also α, can determine height: h=tan (α) * d according to trigonometric function relation.Described height h can make, when the light I3 that total reflection may occur exposes to the vertical wall 330s of height below h, if there occurs total reflection, its reflection ray I4 also only can expose to the top surface of described cavity wall 320, and described induction region 211 can not be exposed to, interference can not be produced to the imaging of described induction region 211.Therefore, the predetermined depth of the second cutting groove 420 described in the present embodiment is set to be greater than the difference of described upper cover plate structure 320 and described height h, can make can not enter described induction region 211 from the sidewall total reflection light of described upper cover plate structure 330.
In some other embodiment, the determination of the degree of depth of described second cutting groove 420 also needs the distance considering described induction region 211 and described cavity wall 320 madial wall, the thickness of described cavity wall 320, and the 3rd cutting technique formed the factor such as width of the 3rd cutting groove 430.In a word, the shape of described second cutting groove 420 makes in described chip-packaging structure, can not enter described induction region 211 from the light of the sidewall total reflection of described upper cover plate structure 330.
Corresponding to the chip-packaging structure that above-mentioned method for packing is formed, the embodiment of the present invention additionally provides a kind of encapsulating structure.
With reference to Figure 10, described encapsulating structure comprises: chip unit 210, and the first surface 210a of described chip unit 210 comprises induction region 211; Upper cover plate structure 330, the first surface 330a of described upper cover plate structure 330 has multiple groove structure 310, and described groove structure is surrounded with the cavity wall 320 be positioned on described first surface 330a by the first surface 330a of described upper cover plate structure 330; Wherein, the first surface 210a of described chip unit 210 is relative with the first surface 330a of described upper cover plate structure 330 to be combined, within the cavity that the first surface 330a making described induction region 211 be positioned at described groove structure 310 and described chip unit 330 surrounds; Described upper cover plate structure 330 also comprises the second surface 330b relative with first surface 330a, and the area of described upper cover plate structure 330 second surface 330b is less than the area of first surface 330a.
In the present embodiment, described upper cover plate structure 330 also comprises sidewall between described first surface 330a and second surface 330b, described sidewall comprises vertical wall 330s and inclined wall 330t, the edge conjunction of the first end of described inclined wall 330t and the second surface 330b of described upper cover plate structure 330, its second relative end is connected with the top of described vertical wall 330s.The angle part that described inclined wall 330t can be formed for the second surface 330b of described upper cover plate structure 330 and described sidewall is removed rear formation.The angle part formed due to second surface 330b and the described sidewall of described upper cover plate structure 330 is removed, the light originally occurring to reflect on the sidewall of described angle part can not enter described upper cover plate structure 330 again, decrease the interference light entering induction region from described upper cover plate structure side wall reflection, thus the image quality of the chip-packaging structure as image sensor can be improved.
In the embodiment of the present invention, the angle between described inclined wall 330t and described vertical wall 330s is 120 ° ~ 150 °, and described inclined wall 330t can be plane, arc surface or parabola face.Such as, in one embodiment, described inclined wall 330t is plane, and the angle between described inclined wall 330t and described vertical wall 330s is 135 °.
In certain embodiments, the difference in height of described vertical wall 330s top and described upper cover plate structure 330 second surface 330b is determined based on the refractive index of the thickness of described upper cover plate structure 330, the distance between described cavity wall 320 madial wall and the sidewall of described upper cover plate structure 330 and described upper cover plate structure 330.The height of removed angle part is determined by said method, the top surface that can only expose to described cavity wall from the light of the sidewall total reflection of described upper cover plate structure can be made, and described induction region can not be exposed to, further reduce the interference light entering described induction region.In certain embodiments, the difference in height of the second surface 330b of described vertical wall 330s top and described upper cover plate structure 330 is 1/5 ~ 4/5 of described upper cover plate structure 300 thickness, such as, and 1/2.
In certain embodiments, the material of described upper cover plate structure 330 is light transmissive material, and the thickness of described upper cover plate structure is 300 μm ~ 500 μm.Particularly, such as, the material of described upper cover plate structure 330 is unorganic glass or polymethyl methacrylate, and thickness is 400 μm.
In the present embodiment, described chip unit 210 also comprises: be positioned at the weld pad 212 outside described induction region 211; Run through the through hole (sign) of described chip unit 210 from the second surface 210b relative with first surface 210a of described chip unit 210, described through hole exposes described weld pad 212; Cover the insulating barrier 213 on described chip unit 210 second surface 210b and described through-hole side wall surface; Be positioned at described insulating barrier 213 surface and the metal level 214 be connected with described weld pad 212 electricity; Be positioned at the solder mask 215 on described metal level 214 and described insulating barrier 213 surface, described solder mask 215 has the opening exposing the described metal level 214 of part; And fill described opening, and be exposed to external protruding 216 outside described solder mask 215 surface.
With reference to the description to above-mentioned method for packing, can also repeat no more about described encapsulating structure herein.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (15)
1. an encapsulating structure, is characterized in that, comprising:
Chip unit, the first surface of described chip unit comprises induction region; And
Upper cover plate structure, the first surface of described upper cover plate structure has groove structure;
Wherein, the first surface of described chip unit is relative with the first surface of described upper cover plate structure combines, within the cavity that the first surface that described induction region is positioned at described groove structure and described chip unit surrounds; Described upper cover plate structure also comprises the second surface relative with first surface, and the area of described upper cover plate structure second surface is less than the area of first surface.
2. encapsulating structure as claimed in claim 1, it is characterized in that, described upper cover plate structure also comprises sidewall, described sidewall comprises vertical wall and inclined wall, the edge conjunction of the first end of described inclined wall and the second surface of described upper cover plate structure, its second relative end is connected with the top of described vertical wall.
3. encapsulating structure as claimed in claim 2, it is characterized in that, the angle between described inclined wall and described vertical wall is 120 ° ~ 150 °.
4. encapsulating structure as claimed in claim 2, it is characterized in that, the difference in height of described vertical wall top and described upper cover plate structure second surface is determined based on the refractive index of the thickness of described upper cover plate structure, distance between described sunk structure madial wall and described upper cover plate structure vertical wall and described upper cover plate structure.
5. encapsulating structure as claimed in claim 4, it is characterized in that, the difference in height of described vertical wall top and described upper cover plate structure second surface is 1/5 ~ 4/5 of described upper cover plate structural thickness.
6. encapsulating structure as claimed in claim 1, it is characterized in that, the material of described upper cover plate structure is light transmissive material.
7. encapsulating structure as claimed in claim 6, it is characterized in that, the material of described upper cover plate structure is unorganic glass or polymethyl methacrylate, and thickness is 300 μm ~ 500 μm.
8. encapsulating structure as claimed in claim 1, it is characterized in that, described chip unit also comprises:
Be positioned at the weld pad outside described induction region;
Run through the through hole of described chip unit from the second surface relative with first surface of described chip unit, described through hole exposes described weld pad;
Cover the insulating barrier on described chip unit second surface and described through-hole side wall surface;
Be positioned at described surface of insulating layer and the metal level be connected with described weld pad electricity;
Be positioned at the solder mask of described metal level and described surface of insulating layer, described solder mask has the opening exposing the described metal level of part;
Fill described opening, and be exposed to the external projection outside described solder mask surface.
9. a method for packing, is characterized in that, comprising:
There is provided wafer to be wrapped, the first surface of described wafer to be wrapped comprises multiple chip unit and the Cutting Road region between chip unit, and described chip unit comprises induction region;
There is provided capping substrate, form multiple groove structure at the first surface of described capping substrate, described groove structure is corresponding with the induction region on described wafer to be wrapped;
Combine relative with the first surface of described wafer to be wrapped for the first surface of described capping substrate, make the first surface of described groove structure and described wafer to be wrapped surround cavity, described induction region is positioned at described cavity;
Along described Cutting Road region, described wafer to be wrapped and described capping substrate are cut, form multiple chip-packaging structure, described chip-packaging structure comprises described chip unit and is positioned at the upper cover plate structure formed by the described capping substrate of cutting on described chip unit, described upper cover plate structure comprises the first surface and the second surface relative with described first surface that are positioned at described chip unit side, and described cutting makes the area of the second surface of described upper cover plate structure be less than the area of first surface.
10. method for packing as claimed in claim 9, is characterized in that, carry out cutting comprise along described Cutting Road region to described wafer to be wrapped and described capping substrate:
Perform the first cutting technique, comprise and cutting from the second surface relative with first surface of described wafer to be wrapped along described Cutting Road region, until the first surface arriving described wafer to be wrapped forms the first cutting groove;
Perform the second cutting technique, comprise and from the second surface relative with first surface of described capping substrate, cut arrival predetermined depth along described Cutting Road region, form the second cutting groove, the width of described second cutting groove reduces gradually along the direction from the second surface of described capping substrate to first surface; And
Perform the 3rd cutting technique, comprise and continue the described capping substrate of cutting, until form the 3rd cutting groove of through described first cutting groove and described second cutting groove, form multiple chip-packaging structure simultaneously.
11. method for packing as claimed in claim 10, it is characterized in that, described predetermined depth is determined based on the refractive index of the thickness of the upper cover plate structure of described chip-packaging structure, the distance between described sunk structure madial wall and described upper cover plate structure side wall and described upper cover plate structure.
12. method for packing as claimed in claim 11, is characterized in that, described predetermined depth is 1/5 ~ 4/5 of described capping substrate thickness.
13. method for packing as claimed in claim 10, is characterized in that, described second cutting technique adopts drilling bit grinding technique, and the section of the second cutting groove that described second cutting technique is formed is del, inverted trapezoidal, circular arc or parabola shaped.
14. method for packing as claimed in claim 13, is characterized in that, the angle between the sidewall of described second cutting groove and the second surface of described capping substrate is 120 ° ~ 150 °.
15. method for packing as claimed in claim 9, it is characterized in that, described chip unit also comprises weld pad, and described weld pad is positioned at outside described induction region, after being combined with the first surface of described wafer to be wrapped by the first surface of described capping substrate, described method for packing also comprises:
Carry out thinning from the second surface relative with first surface of described wafer to be wrapped;
Etch described wafer to be wrapped from the second surface of described wafer to be wrapped, form through hole, described through hole exposes the weld pad of described chip unit;
Insulating barrier is formed at the second surface of described wafer to be wrapped and the sidewall surfaces of through hole;
The metal level connecting weld pad is formed at described surface of insulating layer;
Form the solder mask with opening at described layer on surface of metal and surface of insulating layer, described opening exposes Metallschicht;
Form external projection on the surface at described solder mask, described external projection fills described opening.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510496625.6A CN105097724A (en) | 2015-08-13 | 2015-08-13 | Package structure and packaging method |
| US15/748,651 US10490583B2 (en) | 2015-08-13 | 2016-08-05 | Packaging structure and packaging method |
| PCT/CN2016/093569 WO2017024994A1 (en) | 2015-08-13 | 2016-08-05 | Packaging structure and packaging method |
| TW105125153A TWI612624B (en) | 2015-08-13 | 2016-08-08 | An encapsulation structure and a method thereof |
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| CN201510496625.6A CN105097724A (en) | 2015-08-13 | 2015-08-13 | Package structure and packaging method |
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| CN105097724A true CN105097724A (en) | 2015-11-25 |
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| CN201510496625.6A Pending CN105097724A (en) | 2015-08-13 | 2015-08-13 | Package structure and packaging method |
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