CN204991710U - Packaging structure - Google Patents
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- CN204991710U CN204991710U CN201520673688.XU CN201520673688U CN204991710U CN 204991710 U CN204991710 U CN 204991710U CN 201520673688 U CN201520673688 U CN 201520673688U CN 204991710 U CN204991710 U CN 204991710U
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Abstract
The utility model provides a packaging structure, packaging structure includes: chip unit, chip unit's first surface includes induction area, the upper cover plate, the first surface of upper cover plate has bearing structure, the upper cover plate covers chip unit's first surface, bearing structure is located the upper cover plate with between the chip unit, just induction area is located bearing structure with within the cavity that chip unit's first surface encloses, wherein, the upper cover plate has the thickness of predetermineeing, makes and follows the light of the lateral wall reflection of upper cover plate can not the direct irradiation induction area. The utility model discloses a packaging structure can reduce incident extremely induction area's interference light.
Description
Technical field
The utility model relates to technical field of semiconductors, particularly relates to a kind of encapsulating structure.
Background technology
On conventional art, the connection of IC chip and external circuit is realized by the mode of metal lead wire bonding (WireBonding).Along with the expansion with footprint of reducing of IC chip feature sizes, Wire Bonding Technology is no longer applicable.
Wafer stage chip encapsulation (WaferLevelChipsizePackaging, WLCSP) technology is that after carrying out packaging and testing to full wafer wafer, cutting obtains the technology of single finished product chip again, and the chip size after encapsulation is consistent with nude film.Wafer stage chip encapsulation technology has overturned the pattern of conventional package as ceramic leadless chip carrier (CeramicLeadlessChipCarrier), organic leadless chip carrier (OrganicLeadlessChipCarrier), has complied with that market is day by day light, little, short to microelectronic product, thinning and low priceization requirement.Chip after the encapsulation of wafer stage chip encapsulation technology reaches highly microminiaturized, and chip cost significantly reduces along with the reduction of chip and the increase of wafer size.Wafer stage chip encapsulation technology be IC can be designed, wafer manufacture, packaging and testing, the technology that integrates, be focus and the development trend in current encapsulation field.
Image sensor dice is as a kind of chip that optical imagery can be converted to electronic signal, and it has induction region.When utilizing existing wafer stage chip encapsulation technology to encapsulate image sensor dice, in order to protect above-mentioned induction region injury-free and pollute in encapsulation process, usually a upper cover substrate can be formed in induction region position.Described upper cover substrate, after completing wafer stage chip encapsulation, can continue to retain, and protects induction region from damage and pollution in the use procedure relaying continuation of insurance of image sensor dice.
But the image sensor performance adopting above-mentioned wafer stage chip encapsulation technology to be formed is not good.
Utility model content
The problem that the utility model solves is that the image sensor performance that prior art is formed is not good.
For solving the problem, the utility model embodiment provides a kind of encapsulating structure.Described encapsulating structure comprises: chip unit, and the first surface of described chip unit comprises induction region; Upper cover plate, the first surface of described upper cover plate has supporting construction, described upper cover plate covers the first surface of described chip unit, described supporting construction between described upper cover plate and described chip unit, and within the cavity that surrounds of the first surface that described induction region is positioned at described supporting construction and described chip unit; Wherein, described upper cover plate has preset thickness, and making can not induction region described in direct irradiation from the light of the sidewall reflects of described upper cover plate.
Alternatively, described preset thickness is 50 μm ~ 200 μm.
Alternatively, described preset thickness is 100 μm.
Alternatively, described preset thickness is based on the width of described induction region, the width of described supporting construction with highly determine.
Alternatively, described encapsulating structure also comprises the adhesive layer between described chip unit first surface and described upper cover plate first surface.
Alternatively, described chip unit also comprises: be positioned at the weld pad outside described induction region; Run through the through hole of described chip unit from the second surface relative with first surface of described chip unit, described through hole exposes described weld pad; Cover the insulating barrier on described chip unit second surface and described through-hole side wall surface; Be positioned at described surface of insulating layer and the metal level be connected with described weld pad electricity; Be positioned at the solder mask of described metal level and described surface of insulating layer, described solder mask has the perforate exposing the described metal level of part; Fill described perforate, and be exposed to the external projection outside described solder mask surface.
Compared with prior art, the technical scheme of the utility model embodiment has the following advantages:
The encapsulating structure of the utility model embodiment comprises chip unit and upper cover plate, the first surface of described chip unit comprises induction region, the first surface of described upper cover plate has supporting construction, described upper cover plate covers the first surface of described chip unit, described supporting construction is between described upper cover plate and described chip unit, and within the cavity that surrounds of the first surface that described induction region is positioned at described supporting construction and described chip unit, and described upper cover plate has preset thickness, thinner thickness, making can not induction region described in direct irradiation from the light of the sidewall reflects of described upper cover plate, therefore improve the image quality of the encapsulating structure as image sensor.
Accompanying drawing explanation
Fig. 1 shows the cross-sectional view of the image sensor dice of prior art;
Fig. 2 shows the cross-sectional view of the encapsulating structure of the utility model one embodiment;
Fig. 3 to Fig. 9 shows the structural representation of the intermediate structure formed in the method for packing of the utility model one embodiment.
Embodiment
From background technology, the performance of the image sensor that prior art is formed is not good.
Inventor of the present utility model adopts wafer stage chip encapsulation technology to be studied the technique that image sensor dice encapsulates to prior art, the reason that the performance of the image sensor that discovery prior art is formed is not good is, the upper cover substrate be formed in chip package process on induction region can produce interference to the light entering induction region, reduces image quality.
Particularly, the cross-sectional view of the image sensor dice that prior art is formed is shown with reference to figure 1, Fig. 1.Described image sensor dice comprises: substrate 10; Be positioned at the induction region 20 of described substrate 10 first surface; Be positioned at described substrate 10 first surface, the weld pad 21 of described induction region 20 both sides; Run through the through hole (sign) of described substrate 10 from the second surface relative with described first surface of described substrate 10, described through hole exposes described weld pad 21; Be positioned at the insulating barrier 11 of described through-hole side wall and substrate 10 second surface; The line layer 12 of described weld pad 21 and partial insulative layer 11 is covered from described second surface; Cover the solder mask 13 of described line layer 12 and insulating barrier 11, described solder mask 13 has opening; Be positioned at the soldered ball 14 that described solder mask 13 opening is connected with described weld pad 21 electricity by described line layer 12; Cavity wall 31 around the induction region 20 being positioned at described substrate 10 first surface; And the upper cover substrate 30 be positioned on described cavity wall.Described upper cover substrate 30 forms cavity with the first surface of cavity wall 21 and substrate 10, makes described inductor 20 be positioned at described cavity, avoids induction zone 20 polluted in encapsulation and use procedure and damage.The thickness of usual described upper cover substrate 30 is comparatively large, such as 400 microns.
Inventor of the present utility model finds, in the use procedure of above-mentioned image sensor dice, the upper cover substrate 30 of light I1 incidental image image-position sensor, the some light entering upper cover substrate 30 can expose to the sidewall 30s of upper cover substrate 30, produce refraction and reflex, if reflection ray is incident to described induction region 20, interference will be caused to the imaging of image sensor.In the imaging process of concrete image sensor, described interference is presented as and forms the virtual image in the opposite direction of reflection ray I2 light path, reduces image quality.
In addition, along with the miniaturization trend of wafer stage chip encapsulation, the packaging body of sensor chip integrated on wafer stage chip is more, and the size of single finished product chip packing-body is less, the sidewall of upper cover substrate 30 and the distance at edge, induction zone 20 are also more and more nearer, and above-mentioned interference phenomenon is also more obvious.
Based on above research, the utility model embodiment provides a kind of encapsulating structure and forms the method for packing of described encapsulating structure.Described encapsulating structure comprises chip unit and upper cover plate, the first surface of described chip unit comprises induction region, the first surface of described upper cover plate has supporting construction, described upper cover plate covers the first surface of described chip unit, described supporting construction between described upper cover plate and described chip unit, and within the cavity that surrounds of the first surface that described induction region is positioned at described supporting construction and described chip unit.In encapsulating structure of the present utility model, described upper cover plate has preset thickness, making can not induction region described in direct irradiation from the light of the sidewall reflects of described upper cover plate, decreases the interference light entering induction region, improves the image quality of described induction region.Corresponding, the method for packing that the utility model embodiment forms above-mentioned encapsulating structure also has above advantage.
For enabling above-mentioned purpose of the present utility model, feature and advantage more become apparent, and are described in detail specific embodiment of the utility model below in conjunction with accompanying drawing.
It should be noted that, provide the object of these accompanying drawings to be contribute to understanding embodiment of the present utility model, and should not be construed as and limit improperly of the present utility model.For the purpose of clearer, size shown in figure not drawn on scale, may make and amplify, to reduce or other change.
First, the utility model embodiment provides a kind of encapsulating structure.With reference to figure 2, described encapsulating structure comprises chip unit 210, and described chip unit 210 has first surface 210a and the second surface 210b relative with described first surface 210a, and described first surface 210a comprises induction region 211; Upper cover plate 330, described upper cover plate 330 comprises first surface 330a and the second surface 330b relative with described first surface 330a, described first surface 330a has supporting construction 320, described upper cover plate 330 covers the first surface 210a of described chip unit 210, described supporting construction 320 between described upper cover plate 330 and described chip unit 210, and within the cavity that surrounds of the first surface 210a that described induction region 211 is positioned at described supporting construction 320 and described chip unit 210; Wherein, described upper cover plate 330 has preset thickness, makes the light that reflects from the sidewall 330s of described upper cover plate 330 can not induction region 211 described in direct irradiation.
In the utility model embodiment, the preset thickness of described upper cover plate 330 is 50 μm ~ 200 μm, such as 100 μm.Due to the thinner thickness of described upper cover plate 330, can make the light that reflects from the sidewall 330s of described upper cover plate 330 can not induction region 211 described in direct irradiation.Described direct irradiation refers to the irradiation that light produces without the reflection at other interfaces.Particularly, the encapsulating structure of the utility model embodiment is compared with the image sensor of the prior art shown in Fig. 1, identical incident ray I1, in FIG, the upper cover substrate 30 of the incident described image sensor of meeting, and reflect at the sidewall 30s place of above-mentioned upper cover substrate 30, irradiate induction region 20, the imaging of interference induction region 20; And with reference to figure 2, in the encapsulating structure of the utility model embodiment, described upper cover plate 330 has preset thickness, such as 100 μm, thinner thickness, described light I1 can not enter described upper cover plate 330, also would not produce reflection ray at the sidewall 330s of described upper cover plate 330, can not produce interference to induction region 211.
In certain embodiments, the preset thickness of described upper cover plate 330 is based on the width of described induction region 330, the width of described supporting construction 320 with highly determine.Particularly, continue with reference to figure 2, suppose that light I3 can incident described upper cover plate 330, and reflect at sidewall 330s, in some cases, described reflection ray is I4, I4 is after the sidewall 330s of described upper cover plate 330 reflects, expose to the top surface of described supporting construction 320, therefore, reflection ray I4 can direct irradiation to described induction region 211 relevant with the width of described supporting construction 320; In other cases, described reflection ray is I5, I5 is after the sidewall 330s of described upper cover plate 330 reflects, enter the cavity at described induction region 211 place, and cross described induction region 211 and expose in the supporting construction 320 of opposite side, therefore, reflection ray I5 can direct irradiation to described induction region 211 also relevant with the width of described induction region 221 with the height of described supporting construction 320, namely relevant with the shape of the cavity at described induction region 211 place.To sum up, during the utility model is implemented, in order to make the light that reflects from the sidewall 330s of described upper cover plate 330 can not induction region 211 described in direct irradiation, the preset thickness of described upper cover plate 330 needs based on the width of described induction region 211, the width of described supporting construction 320 and highly determines.
In some other embodiment, the determination of the preset thickness of described upper cover plate 330 also needs to consider the distance between described induction region 211 and described supporting construction 320 madial wall, and the factor such as the refractive index of described upper cover plate 330.In a word, as long as the light making the preset thickness of described upper cover plate 330 make to launch from the sidewall 330s of described upper cover plate 330 can not induction region 211 described in direct irradiation.
In the present embodiment, described encapsulating structure also comprises: be positioned at the weld pad 212 outside described induction region 211; Run through the through hole (sign) of described chip unit 210 from the second surface 210b relative with first surface 210a of described chip unit 210, described through hole exposes described weld pad 212; Cover the insulating barrier 213 on described chip unit 210 second surface 210b and described through-hole side wall surface; Be positioned at described insulating barrier 213 surface and the metal level 214 be connected with described weld pad 212 electricity; Be positioned at the solder mask 215 on described metal level 214 and described insulating barrier 213 surface, described solder mask 215 has the perforate (sign) exposing the described metal level 214 of part; Fill described perforate, and be exposed to external protruding 216 outside described solder mask 215 surface.Induction region 211 can be connected with external circuit with external protruding 216 by described weld pad 212, metal level 214 by above-mentioned structure, transmits the corresponding signal of telecommunication.
Accordingly, the utility model embodiment provides a kind of method for packing, for the formation of encapsulating structure as shown in Figure 2.Please refer to Fig. 3 to Fig. 9, the intermediate structure schematic diagram formed in the encapsulation process for the method for packing of the utility model embodiment.
First, with reference to figure 3 and 4, provide wafer to be wrapped 200, wherein, Fig. 3 is the plan structure schematic diagram of described wafer to be wrapped 200, and Fig. 4 is the cutaway view of Fig. 3 along AA1 direction.
Described wafer to be wrapped 200 has first surface 200a and the second surface 200b relative relative to 200a with described first surface.The first surface 200a of described wafer to be wrapped 200 have multiple chip unit 210 and the Cutting Road region 220 between described chip unit 210.
In the present embodiment, multiple chip units 210 on described wafer to be wrapped 200 are arranged in array, described Cutting Road region 220 is between adjacent chip unit 210, follow-uply along described Cutting Road region 220, described wafer to be wrapped 200 to be cut, multiple chip-packaging structure comprising described chip unit 210 can be formed.
In the present embodiment, described chip unit 210 is image sensor chip unit, the weld pad 212 that described chip unit 210 has induction zone 211 and is positioned at outside described induction region 211.Described induction region 211 is optical sensor district, and such as, can be arranged by multiple photodiode array and be formed, the optical signalling exposing to described induction region 211 can be converted into electrical signal by described photodiode.The input and output side that described weld pad 212 is connected with external circuit as device in described induction region 211.In certain embodiments, described chip unit 210 is formed on silicon substrate, and described chip unit 210 also comprises other function elements be formed in described silicon substrate.
It should be noted that, in the subsequent step of the method for packing of the utility model embodiment, for the purpose of simple and clear, be only described for the sectional view in the AA1 direction along described wafer to be wrapped 200 shown in Fig. 3, perform similar processing step in other regions.
Then, with reference to figure 5, capping substrate 300 is provided, described capping substrate 300 comprises first surface 300a and the second surface 300b relative with described first surface 300a, the first surface 300a of described capping substrate 300 is formed multiple supporting construction 320, and described supporting construction 320 is corresponding with the induction region 211 on the groove structure that described first surface 300a surrounds and described wafer to be wrapped 200.
In the present embodiment, described capping substrate 300 covers the first surface 200a of described wafer to be wrapped 200 in subsequent technique, for protecting the induction region 211 on described wafer to be wrapped 200.Because capping substrate 300 described in needs light therethrough arrives induction region 211, therefore, described capping substrate 300 has higher light transmission, is light transmissive material.Two surperficial 300a and 300b of described capping substrate 300 are all smooth, smooth, can not produce scattering, diffuse reflection etc. to incident ray.Particularly, described capping substrate 300 material can for unorganic glass, polymethyl methacrylate or other there is the light transmissive material of certain strength.
In certain embodiments, described supporting construction 320 is by etching formation after depositing support construction material layer on the first surface 300a of described capping substrate 300.Particularly, first the supporting construction material layer (not shown) covering described capping substrate 300 first surface 300a is formed, then carry out graphically to described supporting construction material layer, after removing the described supporting construction material layer of part, form described supporting construction 320.Position on described capping substrate 300 of described supporting construction 320 and the groove structure that described first surface 300a surrounds and described induction region 211 position on described wafer to be wrapped 200 corresponding, thus making after follow-up combined process, described induction region 211 can be positioned at described supporting construction 320 and described groove.In certain embodiments, the material of described supporting construction material layer is wet film or dry film photoresist, by spraying, spin coating or the technique such as to paste and formed, described supporting construction material layer is exposed and development carry out graphical after form described supporting construction 320.In certain embodiments, described supporting construction material layer can also be the insulating dielectric materials such as silica, silicon nitride, silicon oxynitride, and formed by depositing operation, follow-up employing photoetching and etching technics carry out graphically forming described supporting construction 320.
In some other embodiment, described supporting construction 320 can also by etching rear formation to described capping substrate 300.Particularly, patterned photoresist layer can be formed on described capping substrate 300, and then with described patterned photoresist layer for capping substrate 300 described in mask etching, in described capping substrate 300, form described supporting construction 320, described supporting construction 320 is the bossing on described capping substrate 300 first surface 300a.
In the utility model embodiment, described capping substrate 300 has preset thickness, after the follow-up upper cover plate described capping substrate being carried out cutting formation encapsulating structure, described upper cover plate also has described preset thickness, and making can not the induction region 211 of chip unit described in direct irradiation from the light of the sidewall reflects of described upper cover plate.In certain embodiments, described preset thickness can be 50 μm ~ 200 μm, such as, and 100 μm.
In certain embodiments, directly provide the capping substrate 300 with preset thickness, follow-uply on described capping substrate 300, form supporting construction 320 and be combined with described wafer to be wrapped 200.In further embodiments, the capping substrate 300 having and be greater than described preset thickness is provided, after the first surface 300a of described capping substrate 300 forms supporting construction 320, from described second surface 300b, described preset thickness is thinned to described capping substrate 300 again, have and can provide stronger mechanical support in the process forming described supporting construction 320 compared with the capping substrate 300 of heavy thickness, avoid damaging.In further embodiments, the capping substrate 300 having and be greater than described preset thickness is provided, supporting construction 320 is formed at described capping substrate 300, and after described capping substrate 320 is combined with described wafer to be wrapped 200, from the second surface 300b of described capping substrate, described preset thickness is thinned to described capping substrate 300 again, similarly, have and can provide stronger mechanical support for subsequent technique compared with the capping substrate 300 of heavy thickness.Above-mentioned reduction process can adopt the technique such as mask, etching, and the utility model is not construed as limiting this.
Then, with reference to figure 6, combine relative with the first surface 200a of described wafer to be wrapped 200 for the first surface 300a of described capping substrate 300, described supporting construction 320 is between the first surface 300a and the first surface 200a of described wafer to be wrapped 200 of described capping substrate 300, make described supporting construction 320 surround cavity (sign) with the first surface 200a of described wafer to be wrapped 200, described induction region 211 is positioned at described cavity.
In the present embodiment, by adhesive layer (not shown), described capping substrate 300 and described wafer to be wrapped 200 are combined.Such as, can on the top surface of the supporting construction 320 of described capping substrate 300 first surface 300a, and/or on the first surface 200a of described wafer to be wrapped 200, described adhesive layer is formed by spraying, spin coating or the technique pasted, again by the first surface 200a relative pressing of the first surface 300a of described capping substrate 300 with described wafer to be wrapped 200, combined by described adhesive layer.Described adhesive layer both can realize bonding effect, can play again insulation and sealing function.Described adhesive layer can be the polymeric materials such as polymeric adhesion material, such as silica gel, epoxy resin, benzocyclobutene.
In the present embodiment, after relative with the first surface 200a of described wafer to be wrapped 200 for the first surface 300a of described capping substrate 300 combination, described supporting construction 320 surrounds cavity with the first surface 200a of described wafer to be wrapped 200.The position of described cavity is corresponding with the position of described induction region 211, and described cavity area is slightly larger than the area of described induction region 211, and described induction region 211 can be made to be positioned at described cavity.In the present embodiment, after described capping substrate 300 and described wafer to be wrapped 200 being combined, the weld pad 212 on described wafer to be wrapped 200 is covered by the supporting construction 320 on described capping substrate 300.Described capping substrate 300 in subsequent technique, can play the effect protecting described wafer to be wrapped 200.
Then, with reference to figure 7, encapsulation process is carried out to described wafer to be wrapped 200.
Particularly, first, carry out thinning from the second surface 200b of described wafer to be wrapped 200 to described wafer to be wrapped 200, so that the etching of follow-up through hole, can mechanical lapping, chemical mechanical milling tech etc. be adopted to the thinning of described wafer to be wrapped 200; Then, etch from the second surface 200b of described wafer to be wrapped 200 described wafer to be wrapped 200, form through hole (sign), described through hole exposes the weld pad 212 of described wafer to be wrapped 200 first surface 200a side; Then, insulating barrier 213 is formed on the second surface 200b of described wafer to be wrapped 200 and on the sidewall of described through hole, described insulating barrier 213 exposes the weld pad 212 of described via bottoms, described insulating barrier 213 can provide electric insulation for the second surface 200b of described wafer to be wrapped 200, the substrate of the described wafer to be wrapped 200 that can also expose for described through hole provides electric insulation, and the material of described insulating barrier 213 can be silica, silicon nitride, silicon oxynitride or insulating resin; Then, the metal level 214 connecting described weld pad 212 is formed on described insulating barrier 213 surface, described metal level 214 can as wiring layer again, described weld pad 212 is caused on the second surface 200b of described wafer to be wrapped 200, be connected with external circuit again, described metal level 214 through deposit metal films and to the etching of metallic film after formed; Then, the solder mask 215 with perforate (sign) is formed on described metal level 214 surface and described insulating barrier 213 surface, described perforate exposes the surface of the described metal level 214 of part, the material of described solder mask 215 is the insulating dielectric materials such as silica, silicon nitride, for the protection of described metal level 214; Again then, the surface of described solder mask 215 forms external protruding 216, described external protruding 216 fill described perforate, and described external protruding 216 can be the syndeton such as soldered ball, metal column, and material can be the metal materials such as copper, aluminium, gold, tin or lead.
After carrying out encapsulation process to described wafer to be wrapped 200, the chip-packaging structure that follow-up cutting can be made to obtain is connected with external circuit by described external protruding 216.The induction region 211 of described chip unit is after being converted to the signal of telecommunication by light signal, and the described signal of telecommunication can pass through described weld pad 212, metal level 214 and external protruding 216 successively, transfers to external circuit and processes.
Then, with reference to figure 8 and Fig. 9, along described Cutting Road region 220 (simultaneously with reference to figure 4), described wafer to be wrapped 200 and described capping substrate 300 are cut, form multiple encapsulating structure as shown in Figure 2.Described encapsulating structure comprises chip unit 210; And be positioned on described chip unit 210 by the upper cover plate 330 that formed of the described capping substrate 300 of cutting, described upper cover plate 330 has preset thickness, makes the light that reflects from the sidewall 330s of described upper cover plate 330 can not induction region described in direct irradiation.
In the present embodiment, the first cutting technique and the second cutting technique are comprised to the cutting of described wafer to be wrapped 200 and described capping substrate 300.Particularly, with reference to figure 8, first, perform the first cutting technique, described first cutting technique cuts from the second surface 200b of described wafer to be wrapped 200 along Cutting Road region 220 as shown in Figure 4, until the first surface 200a arriving described wafer to be wrapped 200 forms the first cutting groove 410.Described first cutting technique can adopt slicer to cut or laser cutting, and described slicer cutting can adopt steel edge or resin cutter.
Then, with reference to figure 9, perform the second cutting technique, described second cutting technique along the region corresponding with the Cutting Road region 220 described in Fig. 4 from the second surface 300b of described capping substrate 300, described capping substrate 300 is cut, until arrive the first surface 200a of described wafer to be wrapped 200, forms the second cutting groove 420 of through described first cutting groove 410, form multiple encapsulating structure simultaneously, thus complete cutting technique.Described second cutting technique also can adopt slicer to cut or laser cutting.
In some other embodiment, described second cutting technique also can continue the described capping substrate 300 of cutting along described first cutting groove 410 from the first surface 300a of described capping substrate 300, form the second cutting groove 420 running through described capping substrate 300, complete cutting.
It should be noted that, in some other embodiment, described first cutting technique can perform after described second cutting technique; In some other embodiment, can also complete cutting to described wafer to be wrapped 200 and described capping substrate 300 by means of only a cutting technique, the utility model is not construed as limiting this.
The specific descriptions of the encapsulating structure formed about the method for packing of the utility model embodiment with reference to the description for the encapsulating structure shown in Fig. 2, can not repeat them here.
Although the utility model discloses as above, the utility model is not defined in this.Any those skilled in the art, not departing from spirit and scope of the present utility model, all can make various changes or modifications, and therefore protection range of the present utility model should be as the criterion with claim limited range.
Claims (6)
1. an encapsulating structure, is characterized in that, comprising:
Chip unit, the first surface of described chip unit comprises induction region;
Upper cover plate, the first surface of described upper cover plate has supporting construction, described upper cover plate covers the first surface of described chip unit, described supporting construction between described upper cover plate and described chip unit, and within the cavity that surrounds of the first surface that described induction region is positioned at described supporting construction and described chip unit;
Wherein, described upper cover plate has preset thickness, and making can not induction region described in direct irradiation from the light of the sidewall reflects of described upper cover plate.
2. encapsulating structure as claimed in claim 1, it is characterized in that, described preset thickness is 50 μm ~ 200 μm.
3. encapsulating structure as claimed in claim 2, it is characterized in that, described preset thickness is 100 μm.
4. encapsulating structure as claimed in claim 1, it is characterized in that, described preset thickness is based on the width of described induction region, the width of described supporting construction and highly determine.
5. encapsulating structure as claimed in claim 1, is characterized in that, also comprise: the adhesive layer between described chip unit first surface and described upper cover plate first surface.
6. encapsulating structure as claimed in claim 1, it is characterized in that, described chip unit also comprises:
Be positioned at the weld pad outside described induction region;
Run through the through hole of described chip unit from the second surface relative with first surface of described chip unit, described through hole exposes described weld pad;
Cover the insulating barrier on described chip unit second surface and described through-hole side wall surface;
Be positioned at described surface of insulating layer and the metal level be connected with described weld pad electricity;
Be positioned at the solder mask of described metal level and described surface of insulating layer, described solder mask has the perforate exposing the described metal level of part;
Fill described perforate, and be exposed to the external projection outside described solder mask surface.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520673688.XU CN204991710U (en) | 2015-09-02 | 2015-09-02 | Packaging structure |
| TW105128221A TWI612651B (en) | 2015-09-02 | 2016-09-01 | Packaging structure and packaging method |
| US15/752,887 US20180240827A1 (en) | 2015-09-02 | 2016-09-01 | Package structure and packaging method |
| KR1020187008247A KR102069657B1 (en) | 2015-09-02 | 2016-09-01 | Package structure and packaging method |
| JP2018511033A JP6557776B2 (en) | 2015-09-02 | 2016-09-01 | Package structure and packaging method |
| PCT/CN2016/097797 WO2017036410A1 (en) | 2015-09-02 | 2016-09-01 | Package structure and packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520673688.XU CN204991710U (en) | 2015-09-02 | 2015-09-02 | Packaging structure |
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| CN204991710U true CN204991710U (en) | 2016-01-20 |
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| CN201520673688.XU Active CN204991710U (en) | 2015-09-02 | 2015-09-02 | Packaging structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105118843A (en) * | 2015-09-02 | 2015-12-02 | 苏州晶方半导体科技股份有限公司 | Packaging structure and packaging method |
| WO2017036410A1 (en) * | 2015-09-02 | 2017-03-09 | 苏州晶方半导体科技股份有限公司 | Package structure and packaging method |
-
2015
- 2015-09-02 CN CN201520673688.XU patent/CN204991710U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105118843A (en) * | 2015-09-02 | 2015-12-02 | 苏州晶方半导体科技股份有限公司 | Packaging structure and packaging method |
| WO2017036410A1 (en) * | 2015-09-02 | 2017-03-09 | 苏州晶方半导体科技股份有限公司 | Package structure and packaging method |
| CN105118843B (en) * | 2015-09-02 | 2018-09-28 | 苏州晶方半导体科技股份有限公司 | Encapsulating structure and packaging method |
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