CN111900181A - Wafer level packaging method for image sensing chip - Google Patents
Wafer level packaging method for image sensing chip Download PDFInfo
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- CN111900181A CN111900181A CN202010810216.XA CN202010810216A CN111900181A CN 111900181 A CN111900181 A CN 111900181A CN 202010810216 A CN202010810216 A CN 202010810216A CN 111900181 A CN111900181 A CN 111900181A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14687—Wafer level processing
Abstract
The invention provides a wafer-level packaging method of image sensing chips, which comprises the steps of pressing a wafer-level transparent substrate and a supporting dam arranged on the wafer-level transparent substrate on the wafer, then cutting and etching the transparent substrate and the supporting dam, and simultaneously sealing and protecting all the image sensing chips on the wafer at the initial stage of a packaging process, thereby avoiding the operation of attaching the supporting dam and covering a transparent cover plate to the image sensing chips one by one, reducing the requirement on the environmental cleanliness in the subsequent process flow, effectively improving the production yield and reducing the cost.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a wafer level packaging method for an image sensing chip.
Background
With the development of light and shadow technologies such as photographing and shooting, the image sensing chip can be used in a camera of an electronic product as a functional image sensing chip capable of converting a received optical signal into an electrical signal, and has huge market demands.
Meanwhile, as electronic products are further developed to be multifunctional and miniaturized, a wafer level packaging technology is also adopted for a packaging technology of a photosensitive image sensing chip, and the wafer level packaging technology is a technology for obtaining a single finished image sensing chip by packaging and testing a whole wafer and then cutting the whole wafer. The size of a single finished product image sensing chip packaged by the packaging technology is similar to that of a single crystal grain, and the requirements of the market on increasingly lightening, small, short, thinning and low price of microelectronic products are met.
However, in the prior art, the process flow of attaching the transparent cover plate to the wafer is to attach the transparent cover plate and the supporting dam to the image sensing chip one by one, the time that the image sensing chip is exposed in the environment is long, and because the wafer level package is to process the whole wafer, there is a larger product process area, so impurity particles in the production environment are more likely to cause pollution to the image sensing chip, and the photosensitive area of the image sensing chip has a higher requirement on cleanliness compared with the common image sensing chip, thereby causing the low yield and high cost of the image sensing chip manufactured by the wafer level package technology.
Disclosure of Invention
The invention aims to provide a wafer level packaging method for an image sensing chip.
The invention provides a wafer level packaging method of an image sensing chip, which comprises the following steps:
providing a wafer, and forming a plurality of regularly arranged image sensing chips on the wafer;
providing a wafer-level transparent substrate, and manufacturing a supporting dam on the transparent substrate corresponding to the region between the photosensitive regions of the adjacent image sensing chips on the wafer;
pressing one surface of the transparent substrate on which the supporting dam is formed with the wafer;
removing the covering on the wafer cutting channel and exposing the first welding pad positioned at the outer side of the photosensitive area;
dividing the wafer-level transparent substrate into a plurality of transparent cover plates, covering the transparent cover plates above the photosensitive area, and dividing the support dam into a single frame structure surrounding the periphery of the photosensitive area;
and cutting the wafer along the cutting path to form a single image sensing chip.
As a further improvement of the present invention, "manufacturing the supporting dam" specifically includes:
and manufacturing a plurality of supporting dams which are arranged in parallel corresponding to the areas between every two adjacent photosensitive areas on the wafer on the transparent substrate, and exposing the first welding pads between the adjacent supporting dams.
As a further improvement of the present invention, the "removing the covering on the wafer scribe line" specifically includes:
and cutting the transparent substrate which is arranged between the adjacent photosensitive areas and covers the cutting channels and the first welding pads.
As a further improvement of the present invention, the "removing the cover on the wafer dicing lane" further includes:
cutting a portion of the support dam located below the transparent cover plate.
As a further improvement of the present invention, the "manufacturing of the supporting dam" specifically includes:
and manufacturing a supporting dam on the transparent substrate corresponding to the region between each adjacent photosensitive area on the wafer, so that the supporting dam covers the first welding pad.
As a further improvement of the present invention, the "removing the covering on the wafer scribe line" specifically includes:
cutting a part of the transparent substrate covering the cutting channel and the first welding pad between the adjacent image sensing chips and a part of the supporting dam positioned below the transparent substrate;
and etching the rest part of the supporting dam after cutting to expose the first welding pad.
As a further improvement of the present invention, it is characterized in that the "performing press-fitting" specifically includes:
and arranging an adhesive layer on the supporting dam, and aligning and pressing the transparent substrate and the wafer.
As a further development of the invention, it is characterized in that,
the transparent substrate is made of inorganic glass or organic glass.
As a further improvement of the present invention, after the wafer is diced to form individual image sensing chips, the method further includes the steps of:
providing a substrate, arranging the image sensing chip on the first surface of the substrate, and electrically connecting the image sensing chip with the substrate;
filling a plastic packaging material to carry out plastic packaging on the image sensing chip and the substrate;
arranging a welding bulge on a second surface of the substrate opposite to the first surface of the substrate;
and cutting the substrate to form a single packaging structure.
As a further improvement of the present invention, "disposing the image sensing chip on the first surface of the substrate and electrically connecting the image sensing chip with the first surface" specifically includes:
attaching the back surface of the image sensing chip to the first surface of the substrate;
the lead welding wire is electrically connected with the first welding pad and the second welding pad positioned on the first surface of the substrate. The invention has the beneficial effects that: the wafer-level transparent substrate and the supporting dam arranged on the wafer-level transparent substrate are attached to the wafer, and then the processes of cutting, etching the transparent substrate and the supporting dam are carried out, so that all the image sensing chips on the wafer can be simultaneously sealed and protected at the initial stage of the packaging process, the operations of attaching the supporting dam to the image sensing chips and covering the transparent cover plate one by one are avoided, the requirement on the environment cleanliness in the subsequent process flow is lowered, the production yield can be effectively improved, and the cost is reduced.
Drawings
Fig. 1 is a schematic flow chart illustrating the packaging of an image sensor chip, a transparent substrate and a supporting dam in a wafer level packaging method for an image sensor chip according to an embodiment of the present invention.
Fig. 2 is a schematic view of a wafer according to an embodiment of the invention.
Fig. 3 is an enlarged schematic view of a cross-sectional view at a-a in fig. 2.
Fig. 4 is a schematic view of a transparent substrate and a supporting dam according to a first embodiment of the present invention.
Fig. 5 is an enlarged schematic view of a cross-sectional view at B-B in fig. 4.
Fig. 6 is a schematic diagram of the transparent substrate and the supporting dam of fig. 4 after being aligned and pressed on the image sensor chip.
Fig. 7 is a schematic view of the transparent substrate and the supporting dam in the second embodiment of the present invention.
Fig. 8 is a cross-sectional view at C-C in fig. 7.
Fig. 9 is a schematic view of the transparent substrate and the supporting dam of fig. 7 after being aligned and pressed on the image sensor chip.
Fig. 10 and 11 are schematic views of the encapsulation structure of fig. 6 and 9 with portions of the support dam and the transparent substrate removed, respectively.
Fig. 12 and 13 are schematic views of the package structure of fig. 10 and 11 after cutting.
Fig. 14 is a schematic flow chart illustrating the packaging of the image sensor chip and the substrate in the wafer level packaging method for the image sensor chip according to an embodiment of the invention.
Fig. 15 and 16 are schematic diagrams illustrating the package structure in fig. 12 and 13 attached to a substrate, respectively.
Fig. 17 and 18 are schematic diagrams of the package structure of fig. 15 and 16 after lead wires are electrically connected and a molding compound is filled.
Fig. 19 and 20 are schematic views of the package structure in fig. 17 and 18 after solder bumps are disposed on the second surface of the substrate.
Fig. 21 and 22 are schematic views of a single wafer-level package structure of the image sensor chip formed by cutting the package structure shown in fig. 19 and 20, respectively.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more clear, the technical solutions of the present application will be clearly and completely described below with reference to the detailed description of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
For convenience in explanation, the description herein uses terms indicating relative spatial positions, such as "upper," "lower," "rear," "front," and the like, to describe one element or feature's relationship to another element or feature as illustrated in the figures. The term spatially relative position may encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "above" other elements or features would then be oriented "below" or "above" the other elements or features. Thus, the exemplary term "below" can encompass both a spatial orientation of below and above.
As shown in fig. 1, the present invention provides a wafer level packaging method for an image sensor chip, comprising the steps of:
s1: as shown in fig. 2 and fig. 3, a wafer 1 is provided, a plurality of regularly arranged image sensing chips 11 are formed on the wafer 1, and dicing channels 12 are formed between adjacent image sensing chips 11. After the wafer 1 is packaged, the wafer is cut along the cutting streets 12, so as to form a plurality of image sensor chip 11 package structures.
It should be noted that the cutting channel 12 is only a margin area reserved between the two image sensor chips 11 for cutting, and there is no actual boundary line between the cutting channel and the image sensor chips 11 on both sides.
Further, the image sensor chip 11 has a functional surface 111 and a back surface 112 opposite to each other, a photosensitive region 1111 and a first bonding pad 1112 located outside the photosensitive region 1111 and spaced apart from the photosensitive region 1111 are disposed on the functional surface 111, and the first bonding pad 1112 is electrically coupled to the photosensitive region 1111.
The photosensitive region 1111 may include a plurality of photodiode array arrangements for converting optical signals irradiated to the photosensitive region 1111 into electrical signals. The first bonding pads 1112 serve as input and output terminals for devices in the photosensitive region 1111 to connect to external circuitry. In other embodiments of the present invention, other electronic components may be disposed on the image sensor chip 11, which is not limited in the present invention.
S2: as shown in fig. 4 and 5, a wafer-level transparent substrate 2 is provided, and a support dam 3 is formed on the transparent substrate 2 corresponding to an area between the photosensitive areas 1111 of the adjacent image chips 11 on the wafer 1.
The material of the transparent substrate 2 can be inorganic glass, organic glass or other light-transmitting materials with specific strength, and the light-transmitting materials can protect and transmit light to the light-sensing region 1111. The upper and lower surfaces of the transparent substrate 2 are smooth surfaces to prevent scattering, diffuse reflection and other effects on incident light, thereby affecting the sensing accuracy of the image sensing chip 11.
In some embodiments of the present invention, the supporting dam 3 is made of a photosensitive resist, a photosensitive resist coating is formed on the transparent substrate 2 by a spraying or spin coating process, and then the photosensitive resist coating is patterned by an exposure and development process to form the supporting dams 3 arranged in an array in a predetermined area. In other embodiments of the present invention, the material of the supporting dam 3 may also be an insulating dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, etc., and the supporting dam 3 is formed by a deposition process, and then patterned by a photolithography process and an etching process in an array arrangement in a specified region.
S3: as shown in fig. 6, the transparent substrate 2 is formed with the supporting dam 3 and is bonded to the wafer 1.
In some embodiments of the present invention, the support dam 3 and the wafer 1 may be pressed into alignment by an adhesive layer. Forming the bonding layer on the upper surface of the support dam 3 or the limited area on the wafer 1 by screen printing or spin coating, aligning and pressing the support dam 3 and the wafer 1, and bonding by the bonding layer. The adhesive layer can realize the adhesion function on one hand and can play the insulating and sealing functions on the other hand. The adhesive layer may be a polymer adhesive material, such as a polymer material, e.g., silicone, epoxy, benzocyclobutene, etc.
Specifically, in the present invention, there are various structures for implementing the supporting dam 3 on the transparent substrate 2, and two embodiments will be specifically described below.
As shown in fig. 4 to 6, in one embodiment, a plurality of supporting dams 3 are fabricated on the transparent substrate 2 in parallel corresponding to the regions between the adjacent photosensitive areas 1111 of the wafer 1, and the first bonding pads 1112 are exposed between the adjacent supporting dams 3. The region of the supporting dam 3 corresponding to the position on the wafer 1 is spaced from the photosensitive region 1111 and the bonding pad by a certain distance, so as to prevent the bonding layer from contaminating the region and affecting the quality of the package and the image sensor chip 11. The first bonding pads 1112 are exposed, so that in a subsequent cutting process, only the transparent cover plate 21 covering the first bonding pads 1112 needs to be cut off, and the subsequent process flow is simplified.
Illustratively, one supporting dam 3 is respectively disposed between two adjacent first pads 1112 and between the first pads 1112 and the adjacent photosensitive area 1111.
As shown in fig. 7 to 9, in the second embodiment, a supporting dam 3 is formed on the transparent substrate 2 corresponding to the region between the adjacent photosensitive areas 1111 of the wafer 1, and the supporting dam 3 covers the first bonding pad 1112. The area of the supporting dam 3 is spaced from the two adjacent sensing regions by a certain distance corresponding to the position of the wafer 1, so as to prevent the adhesive layer from contaminating the photosensitive region 1111. The supporting dam 3 of this structure is simple in structure and convenient to manufacture.
S4: as shown in fig. 10, the covering on the scribe line 12 of the wafer 1 is removed, and the first bonding pad 1112 located outside the photosensitive zone 1111 is exposed, so as to divide the wafer-level transparent substrate 2 into a plurality of transparent cover plates 21, where the transparent cover plates 21 cover the photosensitive zone 1111, and divide the supporting dam 33 into a single frame structure surrounding the photosensitive zone 1111.
The single transparent cover plate 21 on the photosensitive region 1111 and the supporting dam 33 surrounding the photosensitive region 1111 surround to form a sealed cavity.
Specifically, in the present invention, the implementation method of this step is different according to the structure of the supporting dam 3, and the following description is made in detail with reference to the structure of the supporting dam 3 described in the first and second embodiments.
As shown in fig. 10, in the first embodiment, a portion of the transparent substrate 2 between adjacent photosensitive regions 1111, which covers the scribe line 12 and the first bonding pad 1112, is cut by a cutter or a laser.
Further, in other embodiments of the first embodiment, after the transparent substrate 2 is cut to expose the first bonding pads 1112, a portion of the supporting dam 3 under the transparent cover plate 21 is cut, and at least a portion of the supporting dam 3 is remained without cutting, so as to ensure that the functional surface 111 of the image sensing chip 11 is not scratched by the cutting step, thereby reducing the yield.
Furthermore, cutting off the transparent cover 21 and the supporting dam 3 near the first pad 1112 area in the horizontal direction can ensure that the first pad 1112 is completely exposed without affecting the subsequent wire bonding process.
The supporting dam 3 formed by the above cutting step is formed in a step structure on one side of the photosensitive region 1111, and a block-shaped notch 31 is formed on the upper end of one side of the first pad 1112, the lower surface and the rear surface of the block-shaped notch 31 are parallel and perpendicular to the functional surface 111, and the side wall surface of the transparent cover plate 21 is flush with the rear surface of the block-shaped notch 31.
As shown in fig. 11, in the second embodiment, a portion of the transparent substrate 2 between adjacent image sensor chips 11 and covering the scribe line 12 and the first pad 1112 and the supporting dam 3 located below the transparent substrate are cut by a cutter or a laser, and the cutting leaves a certain processing margin to avoid scratching the functional surface 111 of the image sensor chip 11. Then, the remaining support dam 3 is removed by an etching process to expose the covered functional surface 111 and the first pad 1112.
The supporting dam 3 formed by the above-mentioned cutting step forms a rectangular parallelepiped structure on one side of the photosensitive region 1111, and the side wall surface of the transparent cover plate 21 is flush with the side wall surface of the supporting dam 3.
Here, through the steps S3 and S4, the transparent substrate 2 and the supporting dam 3 disposed thereon are bonded to the wafer 1, and all the image sensing chips 11 on the wafer 1 can be simultaneously sealed and protected at the initial stage of the packaging process, so that the operations of individually bonding the supporting dam 3 and the covering transparent cover plate 21 to the image sensing chips 11 one by one are avoided, and the requirement for environmental cleanliness in the subsequent process flow is reduced, thereby effectively improving the production yield and reducing the cost.
S5: and cutting the wafer 1 along the cutting path 12 to form a plurality of image sensing chips 11 provided with the supporting dam 3 and the transparent cover plate 21.
As shown in fig. 12 and 13, the image sensor chip 11 obtained by cutting the wafer 1 in the first embodiment and the second embodiment is shown.
Fig. 14 is a schematic flow chart illustrating the mounting of the image sensor chip and the substrate in the wafer level packaging method for the image sensor chip according to the present invention.
S6: a substrate 4 is provided, and the back surface 112 of the image sensing chip 11 is bonded to the first surface 41 of the substrate 4.
The image sensing chip 11 and the substrate 4 may be fixed by an adhesive layer.
As shown in fig. 15 and 16, the intermediate package structure of the first embodiment and the second embodiment is formed by attaching the image sensor chip 11 to the substrate 4.
S7: the bonding wires are electrically connected to the first bonding pads 1112 and the second bonding pads 411, and are filled with a molding compound 5 to perform plastic molding on the image sensor chip 11 and the substrate 4.
The image sensing chip 11 and the substrate 4 are electrically connected through a metal bonding wire 6.
As shown in fig. 17 and 18, the intermediate package structure after the image sensor chip 11 is molded in the first embodiment and the second embodiment is shown.
In other embodiments of the present invention, an electrical connector such as a solder ball may be disposed on the back surface 112 of the image sensor chip 11, a conductive structure such as a through silicon via is formed inside the image sensor chip 11 to electrically connect the photosensitive region 1111 and the electrical connector, and the image sensor chip 11 and the substrate 4 are electrically connected by flip-chip.
The plastic package material is filled to form a plastic package layer 5, the plastic package material can be polymer composite materials such as epoxy resin, polyimide, dry film and the like, and the plastic package layer 5 provides physical support for the packaging structure and plays a role in sealing and protecting the image sensing chip 11, the substrate 4 and the bonding wires.
And after the plastic package material is filled, thinning the upper surface of the plastic package material in modes of mechanical grinding and the like, so that the upper surface of the plastic package material is flush with the upper surface of the transparent cover plate 21.
S8: a solder bump 421 is disposed on the second surface 42 of the substrate 4 opposite to the first surface 41, and the solder bump 421 is electrically connected to the second pad 411 through an interconnection circuit located in the substrate 4.
As shown in fig. 19 and 20, the intermediate package structure is obtained after the substrate 4 is provided with the solder bumps 421 in the first and second embodiments, respectively.
S9: and cutting the substrate 4 to form a single packaging structure.
As shown in fig. 21 and 22, the package structure of the single image sensor chip 11 in the first embodiment and the second embodiment is shown.
In summary, according to the invention, the wafer-level transparent substrate and the supporting dam arranged thereon are firstly attached to the wafer, and then the processes of cutting and etching the transparent substrate and the supporting dam are performed, so that all the image sensing chips on the wafer can be simultaneously sealed and protected at the initial stage of the packaging process, thereby avoiding the operations of attaching the supporting dam and covering the transparent cover plate to the image sensing chips one by one, reducing the requirement on environmental cleanliness in the subsequent process flow, and further effectively improving the production yield and reducing the cost.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention and is not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention are included in the scope of the present invention.
Claims (10)
1. A wafer level packaging method for an image sensing chip is characterized by comprising the following steps:
providing a wafer, and forming a plurality of regularly arranged image sensing chips on the wafer;
providing a wafer-level transparent substrate, and manufacturing a supporting dam on the transparent substrate corresponding to the region between the photosensitive regions of the adjacent image sensing chips on the wafer;
pressing one surface of the transparent substrate on which the supporting dam is formed with the wafer;
removing the covering on the wafer cutting path, exposing the first welding pad positioned at the outer side of the photosensitive area, dividing the wafer-level transparent substrate into a plurality of transparent cover plates, covering the transparent cover plates above the photosensitive area, and dividing the supporting dam into a single frame structure surrounding the periphery of the photosensitive area;
and cutting the wafer along the cutting path to form a single image sensing chip.
2. The wafer level packaging method of claim 1, wherein the step of forming the dam comprises:
and manufacturing a plurality of supporting dams on the transparent substrate corresponding to the regions between the adjacent photosensitive areas on the wafer, and exposing the first welding pads between the adjacent supporting dams.
3. The wafer-level packaging method of claim 2, wherein removing the covering on the dicing streets comprises:
and cutting the transparent substrate which is arranged between the adjacent photosensitive areas and covers the cutting channels and the first welding pads.
4. The wafer level packaging method of claim 3, wherein removing the cover on the dicing streets further comprises:
cutting a portion of the support dam located below the transparent cover plate.
5. The wafer level packaging method of claim 1, wherein the step of forming the dam comprises:
and manufacturing a supporting dam on the transparent substrate corresponding to the region between each adjacent photosensitive area on the wafer, so that the supporting dam covers the first welding pad.
6. The wafer-level packaging method of claim 5, wherein removing the covering on the dicing streets comprises:
cutting a part of the transparent substrate covering the cutting channel and the first welding pad between the adjacent image sensing chips and a part of the supporting dam positioned below the transparent substrate;
and etching the rest part of the supporting dam after cutting to expose the first welding pad.
7. The wafer level packaging method of claim 1, wherein the step of bonding comprises:
and arranging an adhesive layer on the supporting dam, and aligning and pressing the transparent substrate and the wafer.
8. The wafer level packaging method of claim 1, wherein,
the transparent substrate is made of inorganic glass or organic glass.
9. The wafer level packaging method of claim 1, wherein after the wafer is diced to form individual image sensing chips, the method further comprises:
providing a substrate, arranging the image sensing chip on the first surface of the substrate, and electrically connecting the image sensing chip with the substrate;
filling a plastic packaging material to carry out plastic packaging on the image sensing chip and the substrate;
arranging a welding bulge on a second surface of the substrate opposite to the first surface of the substrate;
and cutting the substrate to form a single packaging structure.
10. The wafer level packaging method of claim 9, wherein disposing the image sensor chip on the first surface of the substrate and electrically connecting the image sensor chip to the first surface of the substrate comprises:
attaching the back surface of the image sensing chip to the first surface of the substrate;
the lead welding wire is electrically connected with the first welding pad and the second welding pad positioned on the first surface of the substrate.
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| CN202010810216.XA CN111900181A (en) | 2020-08-13 | 2020-08-13 | Wafer level packaging method for image sensing chip |
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| CN202010810216.XA CN111900181A (en) | 2020-08-13 | 2020-08-13 | Wafer level packaging method for image sensing chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115472640A (en) * | 2022-10-14 | 2022-12-13 | 苏州科阳半导体有限公司 | Packaging structure and method of image sensor |
| WO2024051423A1 (en) * | 2022-09-05 | 2024-03-14 | 广东越海集成技术有限公司 | Chip and packaging method for die |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050059188A1 (en) * | 2003-09-17 | 2005-03-17 | Bolken Todd O. | Image sensor packages and methods of fabrication |
| CN103367382A (en) * | 2013-07-23 | 2013-10-23 | 格科微电子（上海）有限公司 | Wafer level packaging method for image sensor chip |
| CN103489885A (en) * | 2013-09-30 | 2014-01-01 | 格科微电子（上海）有限公司 | Wafer-level packaging method of image sensor chips |
| CN106449546A (en) * | 2016-09-26 | 2017-02-22 | 苏州晶方半导体科技股份有限公司 | Image sensor chip packaging structure and packaging method thereof |
| CN109103208A (en) * | 2018-08-17 | 2018-12-28 | 苏州晶方半导体科技股份有限公司 | A kind of encapsulating method and structure of image sensing chip |
| KR101967261B1 (en) * | 2018-05-28 | 2019-08-13 | 테라셈 주식회사 | Image sensor package and manufacturing method thereof |
-
2020
- 2020-08-13 CN CN202010810216.XA patent/CN111900181A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050059188A1 (en) * | 2003-09-17 | 2005-03-17 | Bolken Todd O. | Image sensor packages and methods of fabrication |
| CN103367382A (en) * | 2013-07-23 | 2013-10-23 | 格科微电子（上海）有限公司 | Wafer level packaging method for image sensor chip |
| CN103489885A (en) * | 2013-09-30 | 2014-01-01 | 格科微电子（上海）有限公司 | Wafer-level packaging method of image sensor chips |
| CN106449546A (en) * | 2016-09-26 | 2017-02-22 | 苏州晶方半导体科技股份有限公司 | Image sensor chip packaging structure and packaging method thereof |
| KR101967261B1 (en) * | 2018-05-28 | 2019-08-13 | 테라셈 주식회사 | Image sensor package and manufacturing method thereof |
| CN109103208A (en) * | 2018-08-17 | 2018-12-28 | 苏州晶方半导体科技股份有限公司 | A kind of encapsulating method and structure of image sensing chip |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024051423A1 (en) * | 2022-09-05 | 2024-03-14 | 广东越海集成技术有限公司 | Chip and packaging method for die |
| CN115472640A (en) * | 2022-10-14 | 2022-12-13 | 苏州科阳半导体有限公司 | Packaging structure and method of image sensor |
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