WO2024051423A1

WO2024051423A1 - Chip and packaging method for die

Info

Publication number: WO2024051423A1
Application number: PCT/CN2023/111479
Authority: WO
Inventors: 赖芳奇; 王晔晔; 房玉亮; 赵飞龙; 翟鑫月; 宋亮; 李媛媛; 任鹏
Original assignee: 广东越海集成技术有限公司
Priority date: 2022-09-05
Filing date: 2023-08-07
Publication date: 2024-03-14

Abstract

A chip (300) and a packaging method for a die (11). The die (11) comprises a photosensitive functional region (111). The packaging method comprises: forming, on the die (11), a support structure (12) surrounding the photosensitive functional region (111) (S101); providing a substrate (13), and fixing the die (11) on the substrate (13) (S102); forming a transparent cover plate (14) on the side of the support structure (12) distant from the substrate (13) (S103); forming a protection frame (15) on the substrate (13) (S104); performing plastic packaging on the side of the substrate (13) close to the die (11) by using a plastic packaging material (16) (S105); and removing the plastic packaging material (16) on the side of a first protection branch portion (151) distant from the substrate (13), and removing a first sub-branch portion (1511) of the protection frame (15), so as to form a light through hole (1510) (S106).

Description

Chip and bare chip packaging methods

This application claims priority to Chinese patent applications with application numbers 202211080415.5 and 202222356847.6 submitted to the China Patent Office on September 5, 2022. The entire contents of the above applications are incorporated into this application by reference.

Technical field

The present application relates to the field of chip packaging technology, for example, to a packaging method for chips and bare chips.

Background technique

The preparation process of the chip includes the preparation and packaging of the bare chip (die), as well as chip testing and other stages. The protection of the bare chip is achieved by packaging the bare chip.

Commonly used packaging methods in related technologies include plastic packaging, which uses plastic packaging material to wrap the bare chip and heat and harden it to form a shell of the bare chip to protect the bare chip from pollution from the external environment.

However, for chips with photosensitive functions such as image sensors, the plastic casing needs to be ground to expose the glass cover covering the bare chip so that the photosensitive functional area of the bare chip can receive external light. Research has found that during the grinding process, the glass cover is easily subject to mechanical stress and cracks occur, which affects the imaging of the photosensitive area and thus affects the performance reliability of the chip. In addition, for plastic-sealed devices, water vapor can penetrate into the chip through the plastic packaging layer body and the gap between the plastic packaging layer body and other structures, which is one of the important reasons for the airtightness failure of the device.

Contents of the invention

This application provides a packaging method for chips and bare chips to improve the performance reliability of the chip and extend the life of the chip.

This application provides a packaging method for a bare chip. The bare chip includes a photosensitive functional area. The packaging method includes:

Form a support structure surrounding the photosensitive functional area on the bare chip;

Provide a substrate and fix the bare chip on the substrate; the support structure is located on the side of the bare chip away from the substrate;

A transparent cover is formed on the side of the support structure away from the substrate; the transparent cover covers the photosensitive functional area;

A protection frame is formed on the substrate; the protection frame includes a first protection part and a second protection part connected to each other, and the front projection of the first protection part on the substrate covers the front projection of the bare chip on the substrate, and the first protection part The plane where the first protective part is located intersects with the plane where the second protective part is located, and the second protective part is far away from the first protective part. One end of the protective sub-part is fixed on the base plate; the first protective sub-part includes a first sub-part and a second sub-part, the second sub-part surrounds the first sub-part, and the first sub-part is on the front side of the base plate. The projection is located in the orthographic projection of the transparent cover on the substrate, there is a gap between the first sub-section and the transparent cover, and an end of the second sub-section close to the first sub-section overlaps with the edge of the transparent cover;

Use plastic sealant to seal the side of the substrate close to the bare chip; the plastic sealant is filled in the accommodation space between the protective frame and the substrate, and covers the outer surface of the protective frame;

Remove the plastic compound on the side of the first protective part away from the substrate, and remove the first sub-part to form a light hole.

This application also provides a chip, which is obtained by packaging a bare chip using the packaging method described in any embodiment of this application. The chip includes:

substrate;

The bare chip is fixed on the substrate; the bare chip includes a photosensitive functional area;

The support structure is located on the side of the bare chip away from the substrate and is arranged around the photosensitive functional area;

The transparent cover is located on the side of the support structure away from the bare chip and covers the photosensitive functional area;

Protection frame; the protection frame includes a first protection subdivision and a second protection subdivision connected to each other. The plane of the first protection subdivision intersects with the plane of the second protection subdivision. The second protection subdivision is far away from the first protection subdivision. One end is fixed on the substrate. The first protection subsection includes a light hole and a second sub-section. The second sub-section surrounds the light hole. The orthographic projection of the light hole on the substrate is located on the orthogonal surface of the transparent cover on the substrate. In the projection, one end of the second sub-section close to the light hole overlaps the edge of the transparent cover;

The plastic sealant is filled in the accommodation space between the protection frame and the substrate, and covers the surface of the second protection part away from the bare chip.

Description of the drawings

The following will introduce the drawings needed to describe the embodiments.

Figure 1 is a schematic flow chart of a bare chip packaging method provided by an embodiment of the present application;

Figure 2 is a packaging flow chart corresponding to the packaging method shown in Figure 1;

Figure 3 is a schematic flow chart of another bare chip packaging method provided by an embodiment of the present application;

Figures 4 to 15 are packaging flow charts corresponding to the packaging method shown in Figure 3;

Figure 16 is a schematic structural diagram of a chip provided by an embodiment of the present application;

Figure 17 is one of the structural schematic diagrams of the protection frame in the chip provided by the embodiment of the present application;

Figure 18 is the second structural schematic diagram of the protection frame in the chip provided by the embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

Figure 1 is a schematic flow chart of a bare chip packaging method provided by an embodiment of the present application. Figure 2 is a packaging flow chart corresponding to the packaging method shown in Figure 1. This packaging method is suitable for packaging bare chips with photosensitive functional areas. After packaging, a chip with photosensitive function such as an image sensor can be obtained. As shown in Figure 1 and Figure 2, the packaging method includes the following steps:

S101. Form a support structure surrounding the photosensitive functional area on the bare chip.

As shown in (a) of FIG. 2 , the bare chip 11 includes a photosensitive functional area 111 . The photosensitive functional area 111 is usually provided with photoelectric conversion devices arranged in an array. When external light irradiates the photosensitive functional area 111, each photoelectric conversion device can convert the optical signal it receives into an electrical signal. Based on the electrical signal and the software algorithm, Functions such as imaging and ranging can be realized. The embodiment of the present application does not limit the specific structure and use of the bare chip 11. Any bare chip 11 including the photosensitive functional area 111 can be packaged using the technical solution of the embodiment of the present application.

Continuing to refer to (a) in Figure 2, a support structure 12 is formed around the photosensitive functional area 111. The support structure 12 is set to form a space surrounding the photosensitive functional area 111 to subsequently support the transparent cover and block the plastic sealing material and photosensitive function. Contact District 111 to prepare.

For example, the material of the support structure 12 may be dry film. The structure of the dry film is thin, and using the dry film to form the support structure 12 can reduce the thickness of the packaging structure, which is conducive to the thin design of the chip; in addition, the thermal expansion coefficient of the dry film is low, and it can maintain stability when forming the support structure 12 structure to avoid contamination of the photosensitive functional area 111.

The shape of the support structure 12 is a ring shape consistent with the shape of the photosensitive functional area 111 . For example, when the top view shape of the photosensitive functional area 111 is circular, the top view shape of the support structure 12 is an annular shape.

S102. Provide a substrate and fix the bare chip on the substrate.

As shown in (b) of FIG. 2 , the bare chip 11 is fixed on the substrate 13 , and the support structure 12 is located on the side of the bare chip 11 away from the substrate 13 .

On the one hand, the substrate 13 is configured to support the bare chip 11. On the other hand, the substrate 13 includes bonding pads (not shown in (b) of FIG. 2), and the bonding pads of the substrate 13 are configured to form electrical connections with the bonding pads of the bare chip 11. , and subsequently by forming external pins on the substrate 13, the electrical connection between the bare chip 11 and other circuit devices on the printed circuit board can be achieved, which will be explained later.

S103. Form a transparent cover on the side of the support structure away from the substrate.

As shown in (c) of Figure 2, the transparent cover 14 is located on the side of the support structure 12 away from the substrate 13. Moreover, the transparent cover 14 covers the photosensitive functional area 111 .

The transparent cover 14 is configured to protect the photosensitive functional area 111. The transparent cover 14 and the support structure 12 can form a closed space surrounding the photosensitive functional area 111, and can subsequently block direct contact between the plastic sealing material and the photosensitive functional area 111. For example, the transparent cover 14 can be made of transparent glass to ensure that the photosensitive functional area 111 receives external light.

S104. Form a protective frame on the substrate.

As shown in (d) of FIG. 2 , the protective frame 15 is formed on the substrate 13 . The protection frame 15 includes a first protection part 151 and a second protection part 152 that are connected to each other. The front projection of the first protection part 151 on the substrate 13 covers the front projection of the bare chip 11 on the substrate 13 . The plane where the portion 151 is located intersects the plane where the second protection sub-part 152 is located, and one end of the second protection sub-part 152 away from the first protection sub-part 151 is fixed on the substrate 13; the first protection sub-part 151 includes a first sub-part 1511 and a second sub-section 1512. The second sub-section 1512 surrounds the first sub-section 1511. The orthographic projection of the first sub-section 1511 on the substrate 13 is located within the orthographic projection of the transparent cover 14 on the substrate 13. There is a gap between one sub-section 1511 and the transparent cover 14 , and one end of the second sub-section 1512 close to the first sub-section 1511 overlaps with the edge of the transparent cover 14 .

The function of the protection frame 15 will be described later. It is worth noting that in this embodiment, in order to perform the subsequent plastic packaging process, the second protection part 152 does not completely surround the bare chip 11 .

S105. Use plastic sealing material to plastic seal the side of the substrate close to the bare chip.

As shown in (e) of FIG. 2 , after the plastic sealing process is completed, the plastic sealant 16 is filled in the accommodation space between the protective frame 15 and the substrate 13 and covers the outer surface of the protective frame 15 . The outer surface of the protection frame 15 is the surface on the side of the first protection portion 151 away from the substrate 13 , and the surface on the side of the second protection portion 152 away from the bare chip 11 .

As shown in Figure 2 (e), before plastic sealing, the pads of the bare chip 11 need to be electrically connected to the pads of the substrate 13. For example, metal wires (shown in bold in Figure 2 (e)) can be used. arc) electrically connects the pads of the bare chip 11 and the pads of the substrate 13 . By filling the plastic compound 16 into the accommodation space between the protective frame 15 and the substrate 13 , the plastic compound 16 can be used to protect the circuits on the substrate 13 and improve the reliability of the chip. Controlling the plastic sealant 16 to cover the outer surface of the protective frame 15 during molding can ensure the completion of the molding and avoid areas that are not filled with the plastic sealant 16 in the accommodation space of the protective frame 15 and the substrate 13 .

For example, the plastic sealing material 16 can be made of epoxy resin. After filling the epoxy resin, a high-temperature oxidation treatment can be performed to solidify the plastic sealing material 16 .

S106. Remove the plastic sealing material on the side of the first protection part away from the substrate, and remove the first sub-part to form a light hole.

Comparing (e) and (f) in FIG. 2 , the plastic encapsulation material 16 on the side of the first protection part 151 away from the substrate 13 is removed, and the first sub-part 1511 is removed, forming the light hole 1510 , so , the transparent cover 14 can be exposed to ensure that the photosensitive functional area 111 receives light. It can be understood that the location of the light hole 1510 is the location of the first sub-section 1511 .

For example, the plastic sealing material 16 can be removed by grinding. The first sub-section 1511 can be removed by grinding or other methods, which is not limited in the embodiment of the present application. Comparing (d) and (f) in Figure 2, if the first sub-section 1511 is removed by grinding, the second sub-section 1512 will be thinned accordingly. (f) in Figure 2 indicates the protection frame after removing the first sub-section 1511 with the mark 15'.

In this embodiment, since there is a gap between the first sub-section 1511 and the transparent cover 14 in the first protection sub-section 151, only one end of the second sub-section 1512 close to the first sub-section 1511 is connected to the transparent cover. The edges of 14 overlap, so the contact area between the protective frame 15 and the transparent cover 14 is very small. In this way, during the grinding process, the protective frame 15 can effectively prevent mechanical stress from damaging the transparent cover 14, thereby reducing the sensitivity to light. The imaging influence of the functional area 111 improves the performance reliability of the chip. In addition, only the first sub-section 1511 needs to be removed later to expose the transparent cover 14 to ensure that the photosensitive functional area 111 receives light; similarly, due to The contact area between the protective frame 15 and the transparent cover 14 is very small. Therefore, the protective frame 15 can also prevent damage to the transparent cover 14 during the removal of the first sub-section 1511 . In this embodiment, after the first sub-section 1511 is removed, the remaining second sub-section 1512 and the second protection section 152 in the protection frame 15 can still increase the path for water vapor to enter the inside of the chip, thereby reducing the amount of water vapor entering the package. water vapor, extending the service life of the chip.

For example, the protective frame 15 can be made of metal material, which can effectively protect the transparent cover 14 and effectively reduce the penetration of water vapor in the area where it is located. Of course, the protective frame 15 can also be made of other suitable materials, which is not limited in the embodiments of the present application.

In summary, the technical solution of the embodiment of the present application is to form the following protective frame on the substrate after forming the transparent cover: the protective frame includes a first protective part and a second protective part connected to each other. The first protective part The orthographic projection on the substrate covers the orthographic projection of the bare chip on the substrate. The plane where the first protection part is located intersects the plane where the second protection part is located, and one end of the second protection part away from the first protection part is fixed to the substrate. on the substrate, the first protection sub-section includes a first sub-section and a second sub-section, the second sub-section surrounds the first sub-section, and the orthographic projection of the first sub-section on the substrate is located on the transparent cover on the substrate In the orthographic projection, there is a gap between the first sub-section and the transparent cover. One end of the second sub-section close to the first sub-section overlaps the edge of the transparent cover. After plastic sealing, the first sub-section is removed. Protect the plastic compound on the side of the sub-section away from the substrate, and remove the first sub-section to form a light hole. In this way, due to the gap between the first sub-section and the transparent cover, only the second sub-section is close to the first sub-section. One end of the sub-section overlaps the edge of the transparent cover, so that the protective frame prevents damage to the transparency during removal of the plastic compound and the first sub-section. Damage to the cover reduces the impact on the imaging of the photosensitive functional area of the bare chip, improves the performance reliability of the chip, and does not affect the reception of external light by the photosensitive functional area; in addition, through the remaining second sub-division in the protective frame and the second protection part, which can further increase the path for water vapor to enter the inside of the chip and reduce the water vapor entering the package, thereby extending the service life of the chip.

In one embodiment, Figure 3 is a schematic flow chart of another bare chip packaging method provided by an embodiment of the present application. Figures 4-15 are packaging flow charts corresponding to the packaging method shown in Figure 3. Figure 3 is mentioned above. Based on the description of the core invention of the present application, the embodiment provides a supplementary explanation on the packaging method of the bare chip 11 , and the similarities with the above embodiments will not be repeated here. Referring to Figure 3, the packaging method may include the following steps:

S201. Provide a wafer and form a support layer on the wafer.

Referring to FIG. 4 , a support layer 22 is formed on the wafer 21 .

S202. The patterned support layer forms multiple support structures.

Referring to FIG. 5 , multiple support structures 12 can be obtained by patterning the support layer 22 , and each support structure 12 is arranged around a different photosensitive functional area 111 .

It can be understood that the wafer 21 includes multiple bare chips 11 , and the multiple bare chips 11 can be obtained by cutting the wafer 21 . Rather than forming a support structure 12 on each bare chip 11 after cutting multiple bare chips 11, this embodiment obtains multiple supports by first forming a support layer 22 on the wafer 21 and then patterning the support layer 22. Structure 12 can simplify the process steps, reduce the difficulty of implementation, and enable this step to achieve system-level packaging.

For example, as mentioned above, the support layer 22 can be a dry film, for example, a photosensitive dry film. In this case, the support layer 22 can be patterned through a photolithography process.

S203. Thin the side of the wafer away from the support structure.

Comparing FIG. 5 and FIG. 6 , the side of the wafer 21 away from the support structure 12 is thinned. Figure 6 indicates the thinned wafer with reference numeral 21'. For example, the thickness of the thinned wafer 21' may be about 200 μm. By thinning the wafer 21, the final thickness of the chip can be reduced, which is beneficial to the thin design of the chip.

S204. Form an adhesive layer on the side of the thinned wafer away from the support structure.

Referring to Figure 7, an adhesive layer 23 is formed on the side of the wafer 21' away from the support structure 12. The adhesive layer 23 is configured to subsequently bond the wafer 21 and the substrate. Referring to the above description, by forming the adhesive layer 23 on the wafer 21', compared with forming the adhesive layer 23 on the bare chip 11, the process steps can be simplified, the implementation difficulty can be reduced, and this step can achieve system-level packaging.

For example, the adhesive layer 23 may be die attach film (Die Attach Film, DAF). DAF is a key material commonly used in the chip packaging process. DAF usually includes the first rubber surface, the second rubber surface Surface and middle high thermal conductivity layer, the middle high thermal conductivity layer includes a support body to prevent the chip from tilting. During laser cutting during the chip packaging process, the bare chips 11 can be cut and separated together, so that the cut bare chips 11 can still be adhered to the DAF and will not be scattered and arranged due to cutting. In addition, during the bonding process of the bare chip 11, after the chip is sucked through the suction nozzle, it can be bonded to the substrate through DAF.

S205, cutting wafer.

Referring to Figures 7 and 8, after cutting the wafer 21' along the dotted line in Figure 7, a bare chip 11 formed with a support structure 12 and an adhesive layer 23' can be obtained. Figure 8 identifies the adhesive layer after cutting with the mark 23’.

S206. Provide a substrate and fix the bare chip on the substrate.

Referring to Figure 9, the bare chip 11 is bonded to the substrate 13 through the adhesive layer 23' to achieve fixation.

S207. Form a connection structure to electrically connect the pads of the bare chip and the pads of the substrate.

Referring to FIG. 10 , the connection structure 24 may be a metal wire, through which the bonding pad 112 of the bare chip 11 and the bonding pad 131 of the substrate 13 may be electrically connected. Of course, the bonding pad 112 of the bare chip 11 and the bonding pad 131 of the substrate 13 can also be electrically connected through other methods, which is not limited in the embodiment of the present application. For example, in other embodiments, through-silicon via (TSV) technology can be used to realize vertical electrical interconnection between the pad 112 of the bare chip 11 and the pad 131 of the substrate 13 .

S208. Form a transparent cover on the side of the support structure away from the substrate.

Referring to FIG. 11 , a transparent cover 14 is formed on the side of the support structure 12 away from the substrate 13 .

Optionally, the orthographic projection area of the transparent cover 14 on the substrate 13 is smaller than the orthographic projection area of the bare chip 11 on the substrate 13 . In this way, the transparent cover 14 can be prevented from contacting the metal lines, thereby avoiding affecting the soldering of the bare chip 11 . The stability of the electrical connection between the pad 112 and the pad 131 of the substrate 13.

In addition, when the orthographic projection area of the transparent cover 14 on the substrate 13 is smaller than the orthographic projection area of the bare chip 11 on the substrate 13 , the pad 112 on the bare chip 11 can be exposed. At this time, S207 and S208 can be interchanged. The sequence is that the transparent cover 14 is formed first, and then the bonding pad 112 of the bare chip 11 and the bonding pad 131 of the substrate 13 are electrically connected. The embodiment of the present application only takes as an example that the bonding pad 112 of the bare chip 11 and the bonding pad 131 of the substrate 13 are electrically connected first, and then the transparent cover 14 is formed.

S209. Form a protective frame on the substrate.

Referring to FIG. 12 , a protective frame 15 is formed on the substrate 13 . The specific structure and function of the protection frame 15 will not be described again here.

S210. Use plastic sealing material to plastic seal the side of the substrate close to the bare chip.

Referring to FIG. 13 , after plastic sealing, the plastic sealant 16 is filled in the accommodation space between the protective frame 15 and the substrate 13 , and covers the outer surface of the protective frame 15 .

S211. Use a grinding process to remove the plastic sealing material on the side of the first protection part away from the substrate, and remove the first sub-part to form a light hole.

Referring to FIGS. 13 and 14 , the plastic sealing compound 16 on the side of the first protective subsection 151 away from the substrate 13 (ie, above the protective frame 15 ) is removed. At the same time, the first subsection 1511 is removed to form a light hole 1510 .

The position of the light hole 1510 is the position of the first sub-section 1511. The light hole 1510 can be formed by removing the first sub-section 1511. It can be understood that when the first sub-section 1511 is removed by grinding, the first protection section 151 will be thinned as a whole. Figure 14 indicates the protection frame after the first sub-section 1511 is removed by grinding with mark 15'.

S212. Form external pins on a surface other than the first surface of the substrate; the first surface is the surface of the substrate close to the bare chip.

Referring to FIG. 15 , external pins 25 are formed on the opposite surface of the first surface F1 of the substrate 13 , that is, the surface of the substrate 13 away from the bare chip 11 . At this point, the packaging of the bare chip 11 is completed, and a finished chip is obtained. The chip performance can be tested later.

The external pin 25 is electrically connected to the pad 131 of the substrate 13, so that it can be electrically connected to the pad 112 of the bare chip 11. By soldering the external pin 25 to the printed circuit board, the chip can be realized through the lines on the printed circuit board. Electrical connections to other circuit devices.

For example, referring to FIG. 15 , external pins 25 can be formed on the surface of the substrate 13 away from the bare chip 11 by ball planting. Of course, other technologies may also be used to form the external pins 25 , which is not limited in the embodiments of the present application. For example, in other embodiments, ball grid array package (Ball Grid Array Package, BGA) technology or quad flat no-lead package (Quad Flat No-lead Package, QFN) technology may be used.

An embodiment of the present application also provides a chip, which can be obtained by packaging a bare chip using the packaging method described in any of the above embodiments. Figure 16 is a schematic structural diagram of a chip provided by an embodiment of the present application. As shown in Figure 16, the chip 300 includes a substrate 310, a bare chip 320, a support structure 330, a transparent cover 340, a protective frame 350 and a plastic sealant 360. Among them, the bare chip 320 is fixed on the substrate 310; the bare chip 320 includes a photosensitive functional area 321; the supporting structure 330 is located on the side of the bare chip 320 away from the substrate 310, and is arranged around the photosensitive functional area 321; the transparent cover 340 is located on the supporting structure 330 The side away from the bare chip 320 and covering the photosensitive functional area 321; the protection frame 350 includes a first protection part 351 and a second protection part 352 that are connected to each other. The plane where the first protection part 351 is located is in contact with the second protection part. 352 intersects with the plane, and one end of the second protection part 352 away from the first protection part 351 is fixed on the substrate 310. The first protection part 351 includes a light hole 3511 and a second sub-part 3512. The second sub-part 3512 3512 surrounds the light hole 3511. The orthographic projection of the light hole 3511 on the substrate 310 is located within the orthographic projection of the transparent cover 340 on the substrate 310. The end of the second sub-section 3512 close to the light hole 3511 is in contact with the transparent cover 340. of The edges are overlapped; the plastic compound 360 is filled in the receiving space between the protective frame 350 and the substrate 310 , and covers the surface of the second protective portion 352 on the side away from the bare chip 320 .

Since the chip provided by the embodiment of the present application can be obtained by packaging a bare chip using the packaging method described in any of the above embodiments, it has the same effect as the above packaging method. The transparent cover 340 can be protected through the setting of the protective frame 350 It is not damaged by mechanical stress during the grinding process and prevents the transparent cover 340 from cracking, thereby reducing the imaging impact on the photosensitive functional area 321 and improving the performance reliability of the chip. At the same time, the protective frame 350 can also be used to increase the path for water vapor to enter the inside of the chip. Reduce water vapor entering the package and extend the service life of the chip.

Referring to FIG. 16 , optionally, the orthographic projection of the support structure 330 on the substrate 310 is located within the orthographic projection of the transparent cover 340 on the substrate 310 , so that the support structure 330 can provide strong support to the transparent cover 340 . In addition, optionally, the orthographic projection of the transparent cover 340 on the substrate 310 is located within the orthographic projection of the bare chip 320 on the substrate 310. In this way, the influence of the transparent cover 340 on the metal line (such as the logo 380) due to contact with it can be avoided. The stability of the electrical connection between the pads of the bare chip 320 and the pads of the substrate 310. In addition, when the orthographic projection area of the transparent cover 340 on the substrate 310 is smaller than the orthographic projection area of the bare chip 320 on the substrate 310, the pads on the bare chip 320 can be exposed. At this time, the packaging process can be adjusted more flexibly.

Continuing to refer to Figure 16, the chip 300 also includes an adhesive layer 370, a connection structure 380 and an external pin 390. The adhesive layer 370 is bonded between the bare chip 320 and the substrate 310; the connection structure 380 is electrically connected to the bare chip. 320 and the pad of the substrate 310; the external pin 390 is located on a surface other than the first surface F1 of the substrate 310; the first surface F1 is the surface of the substrate 310 close to the bare chip 320.

The adhesive layer 370 in the chip is cut from the adhesive layer formed on the wafer. As shown in Figure 16, the connection structure 380 may be a metal wire. The external pin 390 may be spherical or in other shapes. FIG. 16 only takes the spherical external pin as an example for illustration.

FIG. 17 is one of the structural schematic diagrams of the protection frame in the chip provided by the embodiment of the present application. As shown in FIG. 16 and FIG. 17 , optionally, the second protection part 352 includes at least two mutually separated third sub-parts. 3521, each third sub-section 3521 is evenly distributed on the transparent cover 340, the support structure 330 and the side of the bare chip 320. With this arrangement, there is a gap between adjacent third sub-parts 3521, so that the gap can be used to fill the plastic compound 360 in the accommodation space formed by the protective frame 350 and the substrate 310. In addition, by setting each third sub-part 3521 Evenly distributed on the transparent cover 340, the support structure 330 and the sides of the bare chip 320 can make the structure of the protective frame 350 more stable.

For example, FIG. 16 and FIG. 17 illustrate that the second protection sub-section 352 includes two third sub-sections 3521, namely the third sub-section 3521-1 and the third sub-section 3521-2. At this time, the two third sub-sections 3521 are arranged oppositely, and the protection frame 350 is in the shape of a right-angle bridge. Of course, in other embodiments, the second protection sub-section 352 may include a greater number of third sub-sections 3521 as long as the filling of the plastic sealant 360 is not affected. Just charge. Exemplarily, Figure 18 is the second structural schematic diagram of the protection framework in the chip provided by the embodiment of the present application. As shown in Figure 18, optionally, the second protection sub-section 352 includes four third sub-sections 3521, namely The third sub-division 3521-1, the third sub-division 3521-2, the third sub-division 3521-3 and the third sub-division 3521-4, the four third sub-divisions 3521 are evenly distributed, and the protection frame 350 It is in the shape of a four-legged table.

Claims

A packaging method for bare chips, the packaging method includes:

forming a support structure on the bare chip surrounding the photosensitive functional area of the bare chip;

Provide a substrate, and fix the bare chip on the substrate; the support structure is located on the side of the bare chip away from the substrate;

A transparent cover is formed on the side of the support structure away from the substrate; the transparent cover covers the photosensitive functional area;

A protective frame is formed on the substrate; the protective frame includes a first protective part and a second protective part connected to each other, and the orthographic projection of the first protective part on the substrate covers the bare chip on the substrate. In the orthographic projection on the substrate, the plane where the first protection part is located intersects with the plane where the second protection part is located, and one end of the second protection part away from the first protection part is fixed on the on the substrate; the first protection subsection includes a first subsection and a second subsection, the second subsection surrounds the first subsection, and the first subsection is on the The orthographic projection on the substrate is located within the orthographic projection of the transparent cover on the substrate, there is a gap between the first sub-section and the transparent cover, and the second sub-section is close to the third sub-section. One end of a sub-section overlaps the edge of the transparent cover;

Use plastic sealing material to plastic seal the side of the substrate close to the bare chip; the plastic sealing material is filled in the accommodation space between the protective frame and the substrate, and covers the outer surface of the protective frame;

Remove the plastic molding material on the side of the first protective portion away from the substrate, and remove the first sub-portion to form a light hole.
The packaging method according to claim 1, wherein forming a support structure surrounding the photosensitive functional area on the bare chip includes:

A wafer is provided and a support layer is formed on the wafer; the wafer includes a plurality of bare chips;

The support layer is patterned to form a plurality of support structures.
The packaging method according to claim 2, before fixing the bare chip on the substrate, further comprising:

Thinning the side of the wafer away from the support structure;

Form an adhesive layer on the side of the thinned wafer away from the support structure;

The wafer is cut.
The packaging method according to claim 1, before forming a protective frame on the substrate, further comprising:

A connection structure is formed to electrically connect the pads of the bare chip and the pads of the substrate.
The packaging method of claim 1, wherein removing the first protective portion away from the The plastic sealing material on one side of the substrate and the removal of the first sub-part include:

A grinding process is used to remove the plastic encapsulation material on the side of the first protective part away from the substrate, and to remove the first sub-part.
The packaging method according to claim 1, further comprising:

External pins are formed on surfaces other than the first surface of the substrate; the first surface is the surface of the substrate close to the bare chip.
A chip obtained by packaging a bare chip using the packaging method described in any one of claims 1 to 6, and the chip includes:

substrate;

A bare chip is fixed on the substrate; the bare chip includes a photosensitive functional area;

A support structure located on the side of the bare chip away from the substrate and arranged around the photosensitive functional area;

A transparent cover plate, located on the side of the support structure away from the bare chip, and covering the photosensitive functional area;

Protection frame; the protection frame includes a first protection subdivision and a second protection subdivision connected to each other. The plane of the first protection subdivision intersects with the plane of the second protection subdivision. The second protection subdivision One end away from the first protection sub-section is fixed on the substrate, the first protection sub-section includes a light hole and a second sub-section, the second sub-section surrounds the light hole, The orthographic projection of the light hole on the substrate is located within the orthographic projection of the transparent cover on the substrate, and one end of the second sub-section close to the light hole is in contact with the transparent cover. The edges overlap;

Plastic encapsulation material is filled in the accommodation space between the protection frame and the substrate, and covers the surface of the second protection part on the side away from the bare chip.
The chip of claim 7, wherein an orthographic projection of the support structure on the substrate is located within an orthographic projection of the transparent cover on the substrate, and an orthographic projection of the transparent cover on the substrate is The orthographic projection is located within the orthographic projection of the die on the substrate.
The chip according to claim 7, wherein the second protection sub-section includes at least two mutually separated third sub-sections, each third sub-section is evenly distributed on the transparent cover plate, the support structure and the sides of the bare chip.
The chip according to claim 7, further comprising:

An adhesive layer, bonded between the bare chip and the substrate;

A connection structure electrically connected between the pads of the bare chip and the pads of the substrate;

The external pins are located on a surface other than the first surface of the substrate; the first surface is the surface of the substrate close to the bare chip.