CN104600058A - Multi-chip semiconductor package structure and manufacturing method - Google Patents
Multi-chip semiconductor package structure and manufacturing method Download PDFInfo
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- CN104600058A CN104600058A CN201510054319.7A CN201510054319A CN104600058A CN 104600058 A CN104600058 A CN 104600058A CN 201510054319 A CN201510054319 A CN 201510054319A CN 104600058 A CN104600058 A CN 104600058A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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Abstract
The invention discloses a multi-chip semiconductor package structure and a manufacturing method. The package structure comprises a semiconductor chip, wherein an opening toward to a first surface and a slot are formed in the second surface of the semiconductor chip, the slot is opposite to an element area of the semiconductor chip, the opening is opposite to a first welding pad of the semiconductor chip and the first welding pad is exposed; a second surface, the inner wall of the slot and the inner wall of the opening are sequentially provided with a first insulating layer, a metal wiring layer and a second insulating layer, at least one functional chip is placed in the slot, and other spare space in the slot is filled with insulating materials, and the metal wiring layer is electrically connected with the first welding pad and a welding pad of the functional chip. According to the package structure, the system package can be realized on the basis of not increasing the package thickness; furthermore, according to the manufacturing method of the package structure, the integral package can be carried out and then a wafer is cut into single chips, therefore the production cost can be reduced.
Description
Technical field
The present invention relates to semiconductor package and technique, specifically relate to a kind of multi-chip semiconductor package structure and manufacture method.
Background technology
Along with various portable information apparatus is to short, little, light, the thin development trend of internal memory property requirements diversification and electronic product day by day, at present, the developing direction of semiconductor chip package is at an intrasystem multi-chip (Multi-Chip Package, MCP) encapsulating structure by several chip package.In order to realize the requirement reaching several functions or multiple performance on a packaging body.Multichip packaging structure is by dissimilar chip, as memory chip, memory chip, flash chip etc. are incorporated in a packaging body.
But integrate multiple chip under limited chip area, the package thickness of material, reliability and Cost Problems all need to solve.
Summary of the invention
In order to solve the problems of the technologies described above, the present invention proposes a kind of multi-chip semiconductor package structure and manufacture method, can realize system in package on the basis not increasing package thickness, cost-saving.
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of multi-chip semiconductor package structure, comprises semiconductor chip, described semiconductor chip have first surface and with its back to second surface; Described first surface has element region and is positioned at several first weld pads of described element region periphery, described second surface is formed with the opening and groove that extend to described first surface, and described groove and described element region back to, described opening and the first weld pad back to and expose described first weld pad; The inwall of described second surface, described groove and the inwall of described opening are formed with the first insulating barrier, metal wiring layer and the second insulating barrier successively, at least one functional chip is placed with in described groove, other clearance spaces in described groove are filled with insulating material, and the weld pad of described metal wiring layer described first weld pad of electrical connection and described functional chip.
As a further improvement on the present invention, in described groove, interval is placed with two described functional chips, the weld pad of two described functional chips is electrically connected with described metal wiring layer respectively, and described functional chip and described insulating material are all between described first insulating barrier and described metal wiring layer.
As a further improvement on the present invention, described second insulating barrier leaves some breach, in described breach, be formed with the external tie point of the described metal wiring layer of electrical connection.
As a further improvement on the present invention, described external tie point is BGA or LGA.
As a further improvement on the present invention, be separately provided with articulamentum, described functional chip to be connected in described groove on the first insulating barrier or described semiconductor chip by described articulamentum.
As a further improvement on the present invention, described functional chip is process chip or memory chip or flash chip or aforesaid combined chip.
As a further improvement on the present invention, described insulating material is epoxy resin or polyimides or benzocyclobutene or polybenzoxazoles or phenolic resins or polyurethane.
As a further improvement on the present invention, described element region is provided with protective layer.
A manufacture method for multi-chip semiconductor package structure, comprises the steps:
A, prepare a wafer with several semiconductor chips, each described semiconductor chip have first surface and with first surface back to second surface; The first surface of described semiconductor chip has element region and some first weld pads being positioned at described element region periphery, described in several, the first weld pad is electrically connected described element region;
B, carry out thinning to the second surface of described wafer;
C, on the second surface of described wafer with the first weld pad of each semiconductor chip back to position carve opening, meanwhile, the second surface of described wafer and the element region of each semiconductor chip back to position carve groove;
The inwall of d, the second surface of wafer formed in step c, the inwall of each opening, each groove covers one deck first insulating barrier, and the first weld pad making each opening corresponding comes out;
At least one functional chip is placed in e, each groove after steps d, and the bottom of the weld pad making functional chip groove dorsad;
Fill insulant in f, each groove after step e, and make insulating material concordant with the first insulating barrier on second surface;
G, to be come out by the weld pad of photoetching process by the functional chip after step f;
On h, the first insulating barrier of being formed in step g, the position of the first weld pad that exposes and the position deposition layer of metal wiring layer of the weld pad of functional chip exposed, form the interconnection between the weld pad of the first weld pad and each functional chip and each functional chip weld pad;
I, metal wiring layer after step h form first insulating layer outward, and leave some breach thereon;
J, step I formed each breach in formed electrical connection metal wiring layer external tie point;
K, cut wafer, discrete is single chips, forms single multi-chip semiconductor package structure.
As a further improvement on the present invention, after steps d is placed on step e, and first apply one deck articulamentum before placing functional chip in step e in groove, then be positioned in groove.
The invention has the beneficial effects as follows: the invention provides a kind of multi-chip semiconductor package structure and manufacture method, by formed on the second surface of semiconductor chip with the first weld pad of first surface back to opening, and metal wiring layer is formed in opening, can by the second surface electrically guiding to semiconductor chip of the first weld pad of semiconductor chip first surface, on metal wiring layer, be provided with some BGA or LGA simultaneously, like this, when being connected with external devices, utilize the Flip Chip Bond Technique of BGA or LGA, replace the wire bonding technique of routing, therefore, the encapsulation volume reducing semiconductor chip can be reached, meet the requirement of semiconductor chip miniaturization.And the groove by being formed on the second surface of semiconductor chip back to element region, the functional chip with some specific function is placed wherein, and be fixed by fill insulant, then, by the technique that reroutes, the weld pad of the weld pad of functional chip and wafer semiconductor-on-insulator chip is electrically connected.Like this, not only can reduce package thickness, can also system in package be realized.This manufacture method utilizes crystal wafer chip dimension encapsulation (WLP) technology, first carries out overall package, then wafer is cut into single chips, reduces holistic cost.
Accompanying drawing explanation
The crystal circle structure schematic diagram of Fig. 1 for providing in the embodiment of the present invention 1 step a;
Fig. 2 is the crystal circle structure schematic diagram after the embodiment of the present invention 1 step b;
Fig. 3 is the crystal circle structure schematic diagram after the embodiment of the present invention 1 step c;
Fig. 4 is the crystal circle structure schematic diagram after laying the first insulating barrier in the embodiment of the present invention 1 steps d;
Fig. 5 is the crystal circle structure schematic diagram after the embodiment of the present invention 1 steps d;
Fig. 6 is the crystal circle structure schematic diagram after the embodiment of the present invention 1 step e;
Fig. 7 is the crystal circle structure schematic diagram after the embodiment of the present invention 1 step f;
Fig. 8 is the crystal circle structure schematic diagram after the embodiment of the present invention 1 step g;
Fig. 9 is the crystal circle structure schematic diagram after the embodiment of the present invention 1 step h;
Figure 10 is the crystal circle structure schematic diagram after the embodiment of the present invention 1 step I;
Figure 11 is the crystal circle structure schematic diagram after the embodiment of the present invention 1 step j;
Figure 12 is the schematic diagram of the multi-chip semiconductor package structure formed after the embodiment of the present invention 1 step k;
Figure 13 is the embodiment of the present invention 2 multi-chip semiconductor package structure schematic diagram.
By reference to the accompanying drawings, make the following instructions:
1---semiconductor chip 101---first weld pad
102---element region 103---first surface
104---second surface 2---opening
3---groove 4---first insulating barrier
5---metal wiring layer 6---second insulating barrier
7---functional chip 701---weld pad of functional chip
8---insulating material 9---are tie point externally
10---breach 11---protective layer
Embodiment
Embodiment 1
As shown in figure 12, a kind of multi-chip semiconductor package structure, comprises semiconductor chip 1, described semiconductor chip have first surface 103 and with its back to second surface 104; Described first surface has element region 102 and is positioned at several first weld pads 101 of described element region periphery, and element region is used for receiving light source or receiving user fingerprints information, and the first weld pad is electrically connected described element region; Described second surface is formed with the opening 2 and groove 3 that extend to described first surface, and described groove and described element region back to, described opening and the first weld pad back to and expose described first weld pad; The inwall of described second surface, described groove and the inwall of described opening are formed with the first insulating barrier 4, metal wiring layer 5 and the second insulating barrier 6 successively; second insulating barrier is covered on metal wiring layer; for the protection of the not oxidized corrosion of layer metal wiring layer; at least one functional chip 7 is placed with in described groove; other clearance spaces in described groove are filled with insulating material 8, and the weld pad 701 of described metal wiring layer described first weld pad of electrical connection and described functional chip.
In said structure, by formed on the second surface of semiconductor chip with the first weld pad of first surface back to opening, and metal wiring layer is formed in opening, can by the second surface electrically guiding to semiconductor chip of the first weld pad of semiconductor chip first surface, on metal wiring layer, be provided with some BGA or LGA simultaneously, like this, when being connected with external devices, utilize the Flip Chip Bond Technique of BGA or LGA, replace the wire bonding technique of routing, therefore, the encapsulation volume reducing semiconductor chip can be reached, meet the requirement of semiconductor chip miniaturization.And the groove by being formed on the second surface of semiconductor chip back to element region, the functional chip with some specific function is placed wherein, and be fixed by fill insulant, then, by the technique that reroutes, the weld pad of the weld pad of functional chip and wafer semiconductor-on-insulator chip is electrically connected.Like this, not only can reduce package thickness, the system in package of chip can also be realized.
Preferably, in described groove, interval is placed with two described functional chips, the weld pad of two described functional chips is electrically connected with described metal wiring layer respectively, and described functional chip and described insulating material are all between described first insulating barrier and described metal wiring layer.Optionally, described functional chip is process chip or memory chip or flash chip or aforesaid combined chip.
Preferably, described second insulating barrier leaves some breach, the external tie point 9 of the described metal wiring layer of electrical connection is formed in described breach, optionally, described external tie point is BGA (abbreviation of Ball Grid Array), also can be LGA (abbreviation of LandGrid Array).
Optionally, be separately provided with articulamentum, described functional chip to be connected in described groove on the first insulating barrier or described semiconductor chip by described articulamentum.
Optionally, described insulating material can be epoxy resin or polyimides or benzocyclobutene or polybenzoxazoles or phenolic resins or polyurethane.
Optionally, the material of described metal wiring layer is the alloy of copper or aluminium or nickel or gold or titanium or aforementioned combinatorial.
As a kind of preferred embodiment, the manufacture method of the present embodiment 1 multi-chip semiconductor package structure, comprises the steps:
A, see Fig. 1, prepare a wafer with several semiconductor chips, each described semiconductor chip have first surface 103 and with first surface back to second surface 104; The first surface of described semiconductor chip has element region 102 and some first weld pads 101 being positioned at described element region periphery, described in several, the first weld pad is electrically connected described element region;
B, see Fig. 2, carry out thinning to the second surface of described wafer, the thinning mode of wafer can realize for mechanical lapping or etching technics;
C, see Fig. 3, on the second surface of described wafer with the first weld pad of each semiconductor chip back to position carve opening 2, meanwhile, the second surface of described wafer and the element region of each semiconductor chip back to position carve groove 3; Concrete, the method forming opening and groove is: first, the second surface 104 of wafer laying one deck photoresist, being exposed by techniques such as exposure, developments by needing the place carving opening and groove; Then, adopt dry etching or wet etching, opening and groove are carved.The opening shape formed can be the straight hole that upper and lower opening is equal, also can be the inclined hole that upper and lower opening does not wait, and open bottom needs the first weld pad to expose; Groove shapes can be the set as required shape such as rectangle, circle.
The inwall of d, the second surface of wafer formed in step c see Fig. 4 and Fig. 5, the inwall of each opening, each groove covers one deck first insulating barrier 4, and the first weld pad making each opening corresponding comes out; The method exposing the first weld pad cuts away part first weld pad by the mode of machine cuts, exposes the sidewall of the first weld pad; Also can be exposed by the surface of etch process by weld pad.
E, see Fig. 6, in each groove after steps d, place at least one functional chip 7, and the bottom of the weld pad making functional chip groove dorsad; Functional chip can be the functional chips such as Processor (process) chip, Memory (memory) chip, and functional chip forms the system in package chip with several functions together with the semiconductor chip encapsulated.
F, see Fig. 7, fill insulant 8 in each groove after step e, and make insulating material concordant with the first insulating barrier on second surface; Namely fully filled by groove with insulating material, insulating material can be epoxy resin, polyimides, benzocyclobutene, polybenzoxazoles or or phenolic resins or polyurethane or other macromolecular materials be applicable to.
G, see Fig. 8, to be come out by the weld pad of photoetching process by the functional chip after step f;
H, see Fig. 9, on the first insulating barrier that step g is formed, the position of the first weld pad that exposes and the position deposition layer of metal wiring layer 5 of the weld pad of functional chip exposed, form the interconnection between the weld pad of the first weld pad and each functional chip and each functional chip weld pad;
I, see Figure 10, the metal wiring layer after step h forms first insulating layer 6 outward, and leaves some breach 10 thereon;
J, see Figure 11, step I formed each breach in formed electrical connection metal wiring layer external tie point 9; External tie point can be BGA, also can be LGA.
K, see Figure 12, cut wafer, discrete is single chips, forms single multi-chip semiconductor package structure.
Optionally, after steps d is placed on step e, and first apply one deck articulamentum before placing functional chip in step e in groove, then be positioned in groove.
Embodiment 2
The present embodiment 2 comprises all technical characteristics in embodiment, and as shown in figure 13, its difference is, described element region is provided with protective layer 11.Protective layer is injury-free for the protection of the induction zone of sensing chip, and optionally, the material of described protective layer is glass or the protective material such as film and glass ceramics, and preferably, the thickness of described protective layer is between 1-400 micron.
To sum up, the present invention proposes a kind of multi-chip semiconductor package structure and manufacture method, and the reduction that the groove had in this encapsulating structure is package thickness provides advantage, utilize groove structure, other functional chips are placed wherein, by rerouting, circuit interconnects by technique, achieves system in package.Therefore, this encapsulating structure can reduce package thickness, meets the requirement of semiconductor chip miniaturization; This manufacture method utilizes crystal wafer chip dimension encapsulation technology, first carries out overall package, then wafer is cut into single chips, reduces production cost.
Above embodiment is with reference to accompanying drawing, to a preferred embodiment of the present invention will be described in detail.The present invention is applicable to the encapsulation of all multi-chip semiconductors.Those skilled in the art by carrying out amendment on various forms or change to above-described embodiment, or is applied to the encapsulating structure of different multi-chip semiconductor, but when not deviating from essence of the present invention, all drops within protection scope of the present invention.
Claims (10)
1. a multi-chip semiconductor package structure, comprises semiconductor chip (1), described semiconductor chip have first surface (103) and with its back to second surface (104); Described first surface has element region (102) and is positioned at several first weld pads (101) of described element region periphery, it is characterized in that: described second surface is formed with the opening (2) and groove (3) that extend to described first surface, and described groove and described element region back to, described opening and the first weld pad back to and expose described first weld pad; The inwall of described second surface, described groove and the inwall of described opening are formed with the first insulating barrier (4), metal wiring layer (5) and the second insulating barrier (6) successively, at least one functional chip (7) is placed with in described groove, other clearance spaces in described groove are filled with insulating material (8), and the weld pad (701) of described metal wiring layer described first weld pad of electrical connection and described functional chip.
2. multi-chip semiconductor package structure according to claim 1, it is characterized in that: in described groove, interval is placed with two described functional chips, the weld pad of two described functional chips is electrically connected with described metal wiring layer respectively, and described functional chip and described insulating material are all between described first insulating barrier and described metal wiring layer.
3. multi-chip semiconductor package structure according to claim 1, is characterized in that: described second insulating barrier leaves some breach, is formed with the external tie point (9) of the described metal wiring layer of electrical connection in described breach.
4. multi-chip semiconductor package structure according to claim 3, is characterized in that: described external tie point is BGA or LGA.
5. multi-chip semiconductor package structure according to claim 1, is characterized in that: be separately provided with articulamentum, and described functional chip to be connected in described groove on the first insulating barrier or described semiconductor chip by described articulamentum.
6. multi-chip semiconductor package structure according to claim 1, is characterized in that: described functional chip is process chip or memory chip or flash chip or aforesaid combined chip.
7. multi-chip semiconductor package structure according to claim 1, is characterized in that: described insulating material is epoxy resin or polyimides or benzocyclobutene or polybenzoxazoles or phenolic resins or polyurethane.
8. multi-chip semiconductor package structure according to claim 1, is characterized in that: described element region is provided with protective layer (11).
9. a manufacture method for multi-chip semiconductor package structure, is characterized in that, comprises the steps:
A, prepare a wafer with several semiconductor chips, each described semiconductor chip have first surface (103) and with first surface back to second surface (104); The first surface of described semiconductor chip has element region (102) and be positioned at some first weld pads (101) of described element region periphery, described in several, the first weld pad is electrically connected described element region;
B, carry out thinning to the second surface of described wafer;
C, on the second surface of described wafer with the first weld pad of each semiconductor chip back to position carve opening (2), meanwhile, the second surface of described wafer and the element region of each semiconductor chip back to position carve groove (3);
The inwall of d, the second surface of wafer formed in step c, the inwall of each opening, each groove covers one deck first insulating barrier (4), and the first weld pad making each opening corresponding comes out;
At least one functional chip (7) is placed in e, each groove after steps d, and the bottom of the weld pad making functional chip groove dorsad;
Fill insulant (8) in f, each groove after step e, and make insulating material concordant with the first insulating barrier on second surface;
G, to be come out by the weld pad of photoetching process by the functional chip after step f;
On h, the first insulating barrier of being formed in step g, the position of the first weld pad that exposes and position deposition layer of metal wiring layer (5) of the weld pad of functional chip exposed, form the interconnection between the weld pad of the first weld pad and each functional chip and each functional chip weld pad;
I, metal wiring layer after step h form first insulating layer (6) outward, and leave some breach (10) thereon;
J, step I formed each breach in formed electrical connection metal wiring layer external tie point (9);
K, cut wafer, discrete is single chips, forms single multi-chip semiconductor package structure.
10. according to the manufacture method of a kind of multi-chip semiconductor package structure shown in claim 9, it is characterized in that, after steps d is placed on step e, and first apply one deck articulamentum before placing functional chip in step e in groove, then be positioned in groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510054319.7A CN104600058B (en) | 2015-02-03 | 2015-02-03 | Multi-chip semiconductor package structure and manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510054319.7A CN104600058B (en) | 2015-02-03 | 2015-02-03 | Multi-chip semiconductor package structure and manufacturing method |
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| Publication Number | Publication Date |
|---|---|
| CN104600058A true CN104600058A (en) | 2015-05-06 |
| CN104600058B CN104600058B (en) | 2017-02-22 |
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| CN201510054319.7A Active CN104600058B (en) | 2015-02-03 | 2015-02-03 | Multi-chip semiconductor package structure and manufacturing method |
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