CN104600058B - Multi-chip semiconductor package structure and manufacturing method - Google Patents

Multi-chip semiconductor package structure and manufacturing method Download PDF

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Publication number
CN104600058B
CN104600058B CN201510054319.7A CN201510054319A CN104600058B CN 104600058 B CN104600058 B CN 104600058B CN 201510054319 A CN201510054319 A CN 201510054319A CN 104600058 B CN104600058 B CN 104600058B
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chip
groove
weld pad
package structure
semiconductor package
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CN104600058A (en
Inventor
王晔晔
万里兮
黄小花
沈建树
钱静娴
翟玲玲
廖建亚
金凯
邹益朝
王珍
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Huatian Technology Kunshan Electronics Co Ltd
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Huatian Technology Kunshan Electronics Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses a multi-chip semiconductor package structure and a manufacturing method. The package structure comprises a semiconductor chip, wherein an opening toward to a first surface and a slot are formed in the second surface of the semiconductor chip, the slot is opposite to an element area of the semiconductor chip, the opening is opposite to a first welding pad of the semiconductor chip and the first welding pad is exposed; a second surface, the inner wall of the slot and the inner wall of the opening are sequentially provided with a first insulating layer, a metal wiring layer and a second insulating layer, at least one functional chip is placed in the slot, and other spare space in the slot is filled with insulating materials, and the metal wiring layer is electrically connected with the first welding pad and a welding pad of the functional chip. According to the package structure, the system package can be realized on the basis of not increasing the package thickness; furthermore, according to the manufacturing method of the package structure, the integral package can be carried out and then a wafer is cut into single chips, therefore the production cost can be reduced.

Description

Multi-chip semiconductor package structure and preparation method
Technical field
The present invention relates to semiconductor package and technique, it is specifically related to a kind of multi-chip semiconductor package structure and system Make method.
Background technology
Short, little, light, thin to the increasingly diversification of internal memory property requirements and electronic product with various portable information apparatus Development trend, at present, the developing direction of semiconductor bare chip chip package is that several chip packages are many in a system Chip (Multi-Chip Package, MCP) encapsulating structure.In order to realize reaching several functions or multiple on a packaging body The requirement of performance.Multichip packaging structure is by different types of chip, such as memory chip, memory chip, flash chip etc. It is incorporated into an encapsulation internal.
However, integrating multiple chips under limited chip area, the package thickness of material, reliability and Cost Problems are all Need to solve.
Content of the invention
In order to solve above-mentioned technical problem, the present invention proposes a kind of multi-chip semiconductor package structure and preparation method, energy Enough systems of realizing on the basis of not increasing package thickness encapsulate, cost-effective.
For achieving the above object, the technical scheme is that and be achieved in that:
A kind of multi-chip semiconductor package structure, including semiconductor bare chip, described semiconductor bare chip has the first table Face and with its back to second surface;Described first surface have element region and be located at described element region periphery several first Weld pad, described second surface forms opening and the groove that oriented described first surface extends, and described groove and described element region Back to, described opening and the first weld pad back to and expose described first weld pad;Described second surface, the inwall of described groove and institute State and the first insulating barrier, metal wiring layer and the second insulating barrier be sequentially formed with the inwall of opening, be placed with described groove to Few One function chip, other clearance spaces in described groove are filled with insulating materials, and the electrical connection of described metal wiring layer Described first weld pad and the weld pad of described functional chip.
As a further improvement on the present invention, two described functional chips it have been spaced apart in described groove, described in two The weld pad of functional chip is electrically connected with described metal wiring layer respectively, and described functional chip and described insulating materials are respectively positioned on institute State between the first insulating barrier and described metal wiring layer.
As a further improvement on the present invention, described second insulating barrier leaves some breach, be formed with described breach Electrically connect the external connection point of described metal wiring layer.
As a further improvement on the present invention, described external connection point is BGA or LGA.
As a further improvement on the present invention, it is additionally provided with articulamentum, described functional chip is connected to by described articulamentum On first insulating barrier or described semiconductor bare chip in described groove.
As a further improvement on the present invention, described functional chip be process chip or memory chip or flash chip or Aforesaid combined chip.
As a further improvement on the present invention, described insulating materials be epoxy resin or polyimides or benzocyclobutene or Polybenzoxazoles or phenolic resin or polyurethane.
As a further improvement on the present invention, described element region is provided with protective layer.
A kind of preparation method of multi-chip semiconductor package structure, comprises the steps:
A, preparation one have the wafer of several semiconductor bare chips, and each described semiconductor bare chip has first surface And with first surface back to second surface;Element region is had on the first surface of described semiconductor bare chip and is located at described unit Some first weld pads of part area periphery, several described first weld pads electrically connect described element region;
B, the second surface to described wafer carry out thinning;
C, on the second surface of described wafer with the first weld pad of each semiconductor bare chip back to position carve out Mouthful, meanwhile, the second surface of described wafer and the element region of each semiconductor bare chip back to position carve groove;
One layer is covered on d, the second surface in the wafer that step c is formed, the inwall of each opening, the inwall of each groove First insulating barrier, and so that corresponding first weld pad of each opening is come out;
E, place at least one functional chip in each groove after step d, and make functional chip weld pad dorsad recessed The bottom of groove;
F, in each groove after step e fill insulant, and make insulating materials exhausted with first on second surface Edge layer is concordant;
G, by photoetching process, the weld pad of the functional chip after step f is come out;
H, on the first insulating barrier that step g is formed, the position of the first weld pad that exposes and the functional chip exposing Weld pad position deposition layer of metal wiring layer, form weld pad and the weldering of each functional chip of the first weld pad and each functional chip Interconnection between pad;
I, outside the metal wiring layer after step h, form first insulating layer, and leave some breach thereon;
J, step i formed each breach in formed electrical connection metal wiring layer external connection point;
K, wafer is cut, discrete for single chip, form single multi-chip semiconductor package structure.
As a further improvement on the present invention, after step d is placed on step e, and in groove, in step e, place function core First coat one layer of articulamentum before piece, then be positioned in groove.
The invention has the beneficial effects as follows:The present invention provides a kind of multi-chip semiconductor package structure and preparation method, passes through The second surface of semiconductor bare chip is formed with the first weld pad of first surface back to opening, and formed in opening Metal wiring layer, can be by second table electrically guiding to semiconductor bare chip of the first weld pad of semiconductor bare chip first surface Face, is provided with some BGA or LGA on metal wiring layer simultaneously, so, when being attached with external devices, using BGA or The Flip Chip Bond Technique of LGA, replaces the wire bonding technique of routing, therefore, it is possible to reach the encapsulation volume reducing semiconductor bare chip, full The requirement of sufficient semiconductor bare chip miniaturization.And by being formed back to element region on the second surface of semiconductor bare chip Groove, the functional chip with some specific functions is placed wherein, and is fixed by fill insulant, then, By rerouting technique, the weld pad of the weld pad of functional chip and wafer semiconductor-on-insulator bare chip is electrically connected with.So, no Only package thickness can be reduced, system encapsulation can also be realized.This preparation method utilizes crystal wafer chip dimension encapsulation (WLP) skill Art, first carries out overall package, then wafer is cut into single chip, reduce holistic cost.
Brief description
Fig. 1 is the crystal circle structure schematic diagram providing in the embodiment of the present invention 1 step a;
Fig. 2 is the crystal circle structure schematic diagram after the embodiment of the present invention 1 step b;
Fig. 3 is the crystal circle structure schematic diagram after the embodiment of the present invention 1 step c;
Fig. 4 is the crystal circle structure schematic diagram after laying the first insulating barrier in the embodiment of the present invention 1 step d;
Fig. 5 is the crystal circle structure schematic diagram after the embodiment of the present invention 1 step d;
Fig. 6 is the crystal circle structure schematic diagram after the embodiment of the present invention 1 step e;
Fig. 7 is the crystal circle structure schematic diagram after the embodiment of the present invention 1 step f;
Fig. 8 is the crystal circle structure schematic diagram after the embodiment of the present invention 1 step g;
Fig. 9 is the crystal circle structure schematic diagram after the embodiment of the present invention 1 step h;
Figure 10 is the crystal circle structure schematic diagram after the embodiment of the present invention 1 step i;
Figure 11 is the crystal circle structure schematic diagram after the embodiment of the present invention 1 step j;
The schematic diagram of the multi-chip semiconductor package structure for being formed after the embodiment of the present invention 1 step k for the Figure 12;
Figure 13 is the embodiment of the present invention 2 multi-chip semiconductor package structure schematic diagram.
In conjunction with accompanying drawing, make the following instructions:
1 semiconductor bare chip 101 first weld pad
102 element region 103 first surface
104 second surface 2 opening
3 groove 4 first insulating barrier
5 metal wiring layer 6 second insulating barrier
The weld pad of 7 functional chip 701 functional chip
8 insulating materials 9 external connection point
10 breach 11 protective layer
Specific embodiment
Embodiment 1
As shown in figure 12, a kind of multi-chip semiconductor package structure, including semiconductor bare chip 1, described semiconductor bare chip Piece have first surface 103 and with its back to second surface 104;Described first surface has element region 102 and is located at described Several first weld pads 101 of element region periphery, element region is used for receiving light source or receive user finger print information, the first weld pad It is electrically connected with described element region;Described second surface forms opening 2 and the groove 3 that oriented described first surface extends, and described Groove and described element region back to, described opening and the first weld pad back to and expose described first weld pad;Described second surface, institute State and be sequentially formed with the first insulating barrier 4, metal wiring layer 5 and the second insulating barrier 6 on the inwall of groove and the inwall of described opening, Second insulating barrier is covered on metal wiring layer, for the not oxidized corrosion of protective layer metal wiring layer, puts in described groove It is equipped with least one functional chip 7, other clearance spaces in described groove are filled with insulating materials 8, and described metal line Layer electrically connects the weld pad 701 of described first weld pad and described functional chip.
In said structure, by the back of the body with the first weld pad of first surface is formed on the second surface of semiconductor bare chip To opening, and in opening formed metal wiring layer, can be electrical by the first weld pad of semiconductor bare chip first surface Guide to the second surface of semiconductor bare chip, some BGA or LGA be provided with metal wiring layer simultaneously, so, with outside When device is attached, using the Flip Chip Bond Technique of BGA or LGA, replaces the wire bonding technique of routing, reduce therefore, it is possible to reach The encapsulation volume of semiconductor bare chip, meets the requirement of semiconductor bare chip miniaturization.And by semiconductor bare chip Second surface on form groove back to element region, the functional chip with some specific functions is placed wherein, and passes through Fill insulant is fixed, then, by rerouting technique by the weld pad of functional chip and wafer semiconductor-on-insulator bare chip Weld pad be electrically connected with.So, package thickness not only can be reduced, the system encapsulation of chip can also be realized.
Preferably, two described functional chips it have been spaced apart in described groove, the weld pad of two described functional chips divides Do not electrically connect with described metal wiring layer, and described functional chip and described insulating materials are respectively positioned on described first insulating barrier and institute State between metal wiring layer.Optionally, described functional chip is process chip or memory chip or flash chip or aforesaid group Close chip.
Preferably, described second insulating barrier leaves some breach, in described breach, be formed with the described hardware cloth of electrical connection The external connection point 9 of line layer, optionally, described external connection point be BGA (abbreviation of Ball Grid Array) or LGA (abbreviation of Land Grid Array).
Optionally, it is additionally provided with articulamentum, it is exhausted that described functional chip is connected in described groove first by described articulamentum In edge layer or described semiconductor bare chip.
Optionally, described insulating materials can for epoxy resin or polyimides or benzocyclobutene or polybenzoxazoles or Phenolic resin or polyurethane.
Optionally, the material of described metal wiring layer is copper or the alloy of aluminium or nickel or gold or titanium or aforementioned combinatorial.
As a kind of preferred embodiment, the preparation method of the present embodiment 1 multi-chip semiconductor package structure, walk including following Suddenly:
A, referring to Fig. 1, prepare a wafer with several semiconductor bare chips, each described semiconductor bare chip has First surface 103 and with first surface back to second surface 104;On the first surface of described semiconductor bare chip, there is element Area 102 and some first weld pads 101 being located at described element region periphery, several described first weld pads electrically connect described element Area;
B, referring to Fig. 2, the second surface of described wafer is carried out thinning, the thinning mode of wafer can for mechanical lapping or Person's etching technics is realized;
C, referring to Fig. 3, on the second surface of described wafer with the first weld pad of each semiconductor bare chip back to position Put and carve opening 2, meanwhile, the second surface of described wafer and the element region of each semiconductor bare chip back to position carve Groove 3;Specifically, form opening and the method for groove is:First, the second surface 104 of wafer lays one layer of photoresist, By techniques such as exposure, developments, the place needing to carve opening and groove is exposed;Then, using dry etching or wet Method etches, and opening is carved with groove.The opening shape being formed can be opened for the equal straight hole of upper and lower opening or up and down Mouth not wait inclined hole, and open bottom need by first weld pad expose;Groove shapes can for rectangle, circle etc. as needed Set shape.
D, referring to Fig. 4 and Fig. 5 in the second surface of the wafer that step c is formed, the inwall of each opening, each groove Cover one layer of first insulating barrier 4 on wall, and so that corresponding first weld pad of each opening is come out;The method exposing the first weld pad Part first weld pad can be cut away by way of machine cuts, expose the side wall of the first weld pad;Can also be incited somebody to action by etch process The surface of weld pad is exposed.
E, referring to Fig. 6, place at least one functional chip 7 in each groove after step d, and make the weldering of functional chip The bottom acted as a cushion to groove;Functional chip can be Processor (process) chip, the function core such as Memory (memory) chip Piece, functional chip constitutes the system encapsulation chip with several functions together with encapsulating the semiconductor bare chip completing.
F, referring to Fig. 7, fill insulant 8 in each groove after step e, and make on insulating materials and second surface The first insulating barrier concordant;With insulating materials, groove is sufficient filling with, insulating materials can for epoxy resin, polyimides, Benzocyclobutene, polybenzoxazoles or or phenolic resin or polyurethane or other suitable macromolecular materials.
G, referring to Fig. 8, by photoetching process, the weld pad of the functional chip after step f is come out;
H, referring to Fig. 9, on the first insulating barrier that step g is formed, the position of the first weld pad that exposes and exposing The position deposition layer of metal wiring layer 5 of the weld pad of functional chip, forms the weld pad of the first weld pad and each functional chip and each Interconnection between functional chip weld pad;
I, referring to Figure 10, outside the metal wiring layer after step h formed first insulating layer 6, and if leaving thereon Dry breach 10;
J, in each breach that step i is formed, referring to Figure 11, form the external connection point 9 of electrical connection metal wiring layer; External connection point can be BGA or LGA.
K, referring to Figure 12, wafer is cut, discrete for single chip, form single multi-chip semiconductor encapsulation knot Structure.
Optionally, after step d is placed on step e, and first coat one layer of company before placement functional chip in groove in step e Connect layer, then be positioned in groove.
Embodiment 2
The present embodiment 2 comprises all technical characteristics in embodiment, and as shown in figure 13, its difference is, on described element region It is provided with protective layer 11.The protective layer used induction zone in protection sensing chip is injury-free, and optionally, the material of described protective layer is The protection materials such as glass or film and glass ceramics, preferably, the thickness of described protective layer is between 1-400 micron.
To sum up, have in a kind of present invention multi-chip semiconductor package structure of proposition and preparation method, and this encapsulating structure Groove be that the reduction of package thickness provides advantage, using groove structure, other functions chip is placed wherein, passes through Reroute technique to be interconnected circuit it is achieved that system encapsulates.Therefore, this encapsulating structure can reduce package thickness, meets The requirement of semiconductor bare chip miniaturization;This preparation method utilizes crystal wafer chip dimension encapsulation technology, first carries out entirety Encapsulation, then wafer is cut into single chip, reduce production cost.
Above example is referring to the drawings, to a preferred embodiment of the present invention will be described in detail.The present invention is applied to institute There is the encapsulation of multi-chip semiconductor.Those skilled in the art by carrying out the modification on various forms or change to above-described embodiment More, or applied to the encapsulating structure of different multi-chip semiconductors, in the case of but without departing substantially from the essence of the present invention, all fall Within protection scope of the present invention.

Claims (10)

1. a kind of multi-chip semiconductor package structure, including semiconductor bare chip (1), described semiconductor bare chip has the first table Face (103) and with its back to second surface (104);Described first surface has element region (102) and is located at described element region Several first weld pads (101) of periphery it is characterised in that:Described second surface forms opening of oriented described first surface extension Mouthful (2) and groove (3), and described groove and described element region back to, described opening and the first weld pad back to and expose described the One weld pad;Be sequentially formed with the inwall of described second surface, the inwall of described groove and described opening the first insulating barrier (4), Metal wiring layer (5) and the second insulating barrier (6), are placed with least one functional chip (7), in described groove in described groove Other clearance spaces are filled with insulating materials (8), and described metal wiring layer electrically connects described first weld pad and described function core The weld pad (701) of piece.
2. multi-chip semiconductor package structure according to claim 1 it is characterised in that:It has been spaced apart in described groove Two described functional chips, the weld pad of two described functional chips is electrically connected with described metal wiring layer respectively, and described function Chip and described insulating materials are respectively positioned between described first insulating barrier and described metal wiring layer.
3. multi-chip semiconductor package structure according to claim 1 it is characterised in that:Leave on described second insulating barrier Some breach, are formed with external connection point (9) electrically connecting described metal wiring layer in described breach.
4. multi-chip semiconductor package structure according to claim 3 it is characterised in that:Described external connection point is BGA Or LGA.
5. multi-chip semiconductor package structure according to claim 1 it is characterised in that:It is additionally provided with articulamentum, described work( Can chip be connected in described groove on the first insulating barrier or described semiconductor bare chip by described articulamentum.
6. multi-chip semiconductor package structure according to claim 1 it is characterised in that:Described functional chip is to process core Piece or memory chip or flash chip or aforesaid combined chip.
7. multi-chip semiconductor package structure according to claim 1 it is characterised in that:Described insulating materials is asphalt mixtures modified by epoxy resin Fat or polyimides or benzocyclobutene or polybenzoxazoles or phenolic resin or polyurethane.
8. multi-chip semiconductor package structure according to claim 1 it is characterised in that:Described element region is provided with protection Layer (11).
9. a kind of preparation method of multi-chip semiconductor package structure is it is characterised in that comprise the steps:
A, preparation one have the wafer of several semiconductor bare chips, and each described semiconductor bare chip has first surface (103) and with first surface back to second surface (104);On the first surface of described semiconductor bare chip, there is element region (102) some first weld pads (101) with positioned at described element region periphery, several described first weld pads electrically connect described elements Area;
B, the second surface to described wafer carry out thinning;
C, on the second surface of described wafer with the first weld pad of each semiconductor bare chip back to position carve opening (2), meanwhile, the second surface of described wafer and the element region of each semiconductor bare chip back to position carve groove (3);
One layer first is covered on d, the second surface in the wafer that step c is formed, the inwall of each opening, the inwall of each groove Insulating barrier (4), and so that corresponding first weld pad of each opening is come out;
E, place at least one functional chip (7) in each groove after step d, and make the weld pad dorsad groove of functional chip Bottom;
F, in each groove after step e fill insulant (8), and make the first insulation on insulating materials and second surface Layer is concordant;
G, by photoetching process, the weld pad of the functional chip after step f is come out;
H, on the first insulating barrier that step g is formed, the position of the first weld pad that exposes and the weldering of the functional chip exposing Position deposition layer of metal wiring layer (5) of pad, is formed the first weld pad and is welded with the weld pad of each functional chip and each functional chip Interconnection between pad;
I, form first insulating layer (6) outside the metal wiring layer after step h, and leave some breach (10) thereon;
J, step i formed each breach in formed electrical connection metal wiring layer external connection point (9);
K, wafer is cut, discrete for single chip, form single multi-chip semiconductor package structure.
10. a kind of preparation method of multi-chip semiconductor package structure according to claim 9 is it is characterised in that step d After being placed on step e, and first coat one layer of articulamentum before placement functional chip in groove in step e, then be positioned in groove.
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105023900A (en) * 2015-08-11 2015-11-04 华天科技(昆山)电子有限公司 Embedded silicon substrate fan-out type packaging structure and manufacturing method thereof
CN107768317A (en) * 2016-08-18 2018-03-06 苏州迈瑞微电子有限公司 A kind of low section multichip packaging structure and its manufacture method
JP6412179B2 (en) * 2017-02-03 2018-10-24 ファナック株式会社 Processing system in which mobile robot carries goods in and out from processing machine, and machine control device
CN107342234A (en) * 2017-07-07 2017-11-10 苏州晶方半导体科技股份有限公司 The method for packing and structure of fingerprint recognition chip and driving chip
CN108346639B (en) * 2017-09-30 2020-04-03 中芯集成电路(宁波)有限公司 Wafer level system packaging method and packaging structure
US10861821B2 (en) 2018-05-03 2020-12-08 Ningbo Semiconductor International Corporation Packaging method and package structure of wafer-level system-in-package
WO2020093391A1 (en) * 2018-11-09 2020-05-14 华为技术有限公司 Chip integrated with at least two dies

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102779800A (en) * 2011-05-09 2012-11-14 精材科技股份有限公司 Chip package and method for forming the same
CN102774805A (en) * 2011-05-13 2012-11-14 精材科技股份有限公司 Wafer packaging body and formation method thereof
CN102810549A (en) * 2012-08-29 2012-12-05 格科微电子(上海)有限公司 Method for manufacturing wafer-level packages of image sensors
CN103208471A (en) * 2013-04-23 2013-07-17 山东华芯半导体有限公司 Multi-chip package body
CN104051364A (en) * 2013-03-15 2014-09-17 英特尔移动通信有限责任公司 Chip arrangements, chip packages, and a method for manufacturing a chip arrangement
CN204424254U (en) * 2015-03-17 2015-06-24 扬州艾笛森光电有限公司 Directly accept the LED packaging element of alternating current

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100338129B1 (en) * 2000-03-25 2002-05-24 이성민 Multichip module in semiconductor and packaging method thereof
CN204424251U (en) * 2015-02-03 2015-06-24 华天科技(昆山)电子有限公司 Multi-chip semiconductor package structure

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102779800A (en) * 2011-05-09 2012-11-14 精材科技股份有限公司 Chip package and method for forming the same
CN102774805A (en) * 2011-05-13 2012-11-14 精材科技股份有限公司 Wafer packaging body and formation method thereof
CN102810549A (en) * 2012-08-29 2012-12-05 格科微电子(上海)有限公司 Method for manufacturing wafer-level packages of image sensors
CN104051364A (en) * 2013-03-15 2014-09-17 英特尔移动通信有限责任公司 Chip arrangements, chip packages, and a method for manufacturing a chip arrangement
CN103208471A (en) * 2013-04-23 2013-07-17 山东华芯半导体有限公司 Multi-chip package body
CN204424254U (en) * 2015-03-17 2015-06-24 扬州艾笛森光电有限公司 Directly accept the LED packaging element of alternating current

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