CN204508799U - Surface sensing chip encapsulating structure - Google Patents
Surface sensing chip encapsulating structure Download PDFInfo
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- CN204508799U CN204508799U CN201420858896.2U CN201420858896U CN204508799U CN 204508799 U CN204508799 U CN 204508799U CN 201420858896 U CN201420858896 U CN 201420858896U CN 204508799 U CN204508799 U CN 204508799U
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Abstract
The utility model discloses a kind of surperficial sensing chip encapsulating structure, this encapsulating structure comprises surperficial sensing chip and functional chip, surface sensing chip first surface have several weld pads and induction zone, second surface is formed with the first opening of corresponding weld pad, insulating barrier and metal wiring layer is equipped with in first opening, weld pad on first surface electrically guides on second surface by metallic circuit layer, arranges plastic packaging layer in the periphery of sensing chip; The second surface of induction chip can add functional chip, the metal wiring layer on functional chip electrical connection second surface.The utility model adopts silicon through hole TSV technology, by the second surface electrically guiding to chip of chip first surface weld pad, reduces encapsulation volume; Plastic packaging is carried out to the periphery of chip, adds the reliability of chip.
Description
Technical field
The utility model relates to surperficial sensing chip encapsulating structure and technique, specifically relates to a kind of surperficial sensing chip encapsulating structure.
Background technology
Surface sensing chip or surface induction chip, if fingerprint recognition surface sensing chip, touch-type surface sensing chip etc. are because it is easy, practicality, application is constantly expanded.The intelligent terminal that function is powerful gradually, also starts to carry increasing surperficial sensing chip, but present equipment frivolously has higher requirement for packaging is short and small, and the encapsulation volume of this type of surperficial sensing chip of lift-launch also will be pursued and minimize.
But traditional surperficial sensing chip adopts wire bonding technique to be connected with substrate by surperficial sensing chip usually, and concrete structure is: surperficial sensing chip has first surface and the second surface relative with first surface; The first surface of surface sensing chip has induction zone and several weld pads, is electrically connected between weld pad and induction zone; Substrate has second weld pad corresponding with surperficial sensing chip, when surperficial sensing chip is connected with substrate, the second weld pad that the weld pad of surperficial sensing chip first surface is corresponding with on substrate is electrically connected by bonding wire.The surperficial sensing chip encapsulating structure of this form, the routing of surperficial sensing chip and substrate is easy to be squeezed and rupture, and can not place other dielectric layers again above routing, have impact on the encapsulation yield of product, also reduces the reliability of product.Due to the restriction of bonding wire craft, the surperficial sensing chip package thickness that this technique completes is comparatively large, cannot meet encapsulation volume and pursue minimized requirement.
Summary of the invention
In order to solve the problems of the technologies described above, the utility model proposes a kind of surperficial sensing chip encapsulating structure, this encapsulating structure can reduce package thickness, meets the requirement of surperficial sensing chip miniaturization; Be arranged with plastic packaging layer outside sensing chip in this encapsulating structure, the reliability of sensing chip can be improved; This encapsulating structure is convenient in conjunction with other functional chips or substrate, strengthens the using function of chip.This preparation method utilizes crystal wafer chip dimension encapsulation technology, first carries out overall package, then wafer is cut into single chips, reduces production cost.
The technical solution of the utility model is achieved in that
A kind of surperficial sensing chip encapsulating structure, comprise the surperficial sensing chip with relative first surface and second surface, described first surface has induction zone and is positioned at several weld pads of described induction zone periphery, and weld pad described in several and described induction zone are electrically connected; Described first surface is formed with the first plastic packaging layer exposing described induction zone; Position relative with each described weld pad on described second surface is formed with the first opening, the inwall of described second surface and described first opening is formed with the insulating barrier exposing described weld pad, described insulating barrier is formed with the metal wiring layer being electrically connected described weld pad expose portion; Described metal wiring layer forms matcoveredn outward.
As further improvement of the utility model, described first plastic packaging layer covers in described induction zone, and the first plastic packaging layer covering in described induction zone has setting thickness.
As further improvement of the utility model, the described induction zone exposed is provided with over cap.
As further improvement of the utility model, described protective layer is the second plastic packaging layer or insulating protective layer.
As further improvement of the utility model, be separately provided with one or more functional chip, described functional chip is electrically connected with the metal wiring layer on described second surface.
As further improvement of the utility model; when described protective layer is described second plastic packaging layer; described functional chip is fixedly arranged between insulating barrier on described second surface and the second plastic packaging layer, and described functional chip is electrically connected with the metal wiring layer on described second surface by the mode of wire bonding.
As further improvement of the utility model, described functional chip is electrically connected with the metal wiring layer on described second surface by the mode of flip chip bonding.
As further improvement of the utility model, the described protective layer of described second surface is provided with the solder bump that some and described metal wiring layer is connected, and described solder bump is for being electrically connected external devices.
As further improvement of the utility model, the material of described metal wiring layer is copper or aluminium or nickel or gold or titanium or alloy.
As further improvement of the utility model, described first opening is combination or the straight hole in groove or groove and hole.
The beneficial effects of the utility model are: the utility model provides a kind of surperficial sensing chip encapsulating structure, by forming first opening relative with the weld pad of first surface on the second surface of surperficial sensing chip, and insulating barrier and metal wiring layer is formed in second surface and the first opening, can by the second surface electrically guiding to surperficial sensing chip of the weld pad of surperficial sensing chip first surface, like this, when connecting external devices (substrate or functional chip), can by the Flip Chip Bond Technique of solder bump and pad, replace the wire bonding technique of routing, therefore, the encapsulation volume reducing surperficial sensing chip can be reached, meet the object of the requirement of surperficial sensing chip miniaturization.The periphery of this encapsulating structure effects on surface sensing chip is carried out plastic packaging or arranges insulating protective layer, further increases the reliability of chip.
Accompanying drawing explanation
Fig. 1 is the crystal circle structure schematic diagram described in the utility model embodiment 1 step a;
Fig. 2 is the crystal circle structure schematic diagram after the utility model embodiment 1 step b;
The crystal circle structure schematic diagram of Fig. 3 a to be the first opening formed after the utility model embodiment 1 steps d be groove;
Fig. 3 b be in Fig. 3 a A-A' to cross-sectional view;
Fig. 4 is the crystal circle structure schematic diagram after forming insulating barrier in the utility model embodiment 1 step e;
Fig. 5 is the crystal circle structure schematic diagram after exposing weld pad in the utility model embodiment 1 step e;
Fig. 6 is the crystal circle structure schematic diagram after the utility model embodiment 1 step f;
Fig. 7 is the crystal circle structure schematic diagram after the utility model embodiment 1 step g;
Fig. 8 is that after the utility model embodiment 1 step h, also flip chip bonding connects the crystal circle structure schematic diagram of a functional chip;
Fig. 9 a is the first opening formed after the utility model embodiment 1 steps d is the crystal circle structure schematic diagram that groove and hole are combined;
Fig. 9 b be in Fig. 9 a B-B' to cross-sectional view;
The crystal circle structure schematic diagram of Figure 10 a to be the first opening formed after the utility model embodiment 1 steps d be straight hole;
Figure 10 b be in Figure 10 a C-C' to cross-sectional view;
Figure 11 is the utility model embodiment 1 surperficial sensing chip encapsulating structure schematic diagram;
Figure 12 is the utility model embodiment 2 surperficial sensing chip encapsulating structure schematic diagram;
Figure 13 is the utility model embodiment 3 surperficial sensing chip encapsulating structure schematic diagram;
Figure 14 is the utility model embodiment 4 surperficial sensing chip encapsulating structure schematic diagram.
By reference to the accompanying drawings, make the following instructions:
1---surperficial sensing chip; 101---first surface;
102---second surface; 103---induction zone;
104---weld pad; 2---the first plastic packaging layer;
3---the first opening; 4---insulating barrier;
5---metal wiring layer; 6---over cap;
7---the second plastic packaging layer; 8---insulating protective layer;
9---functional chip; 10---solder bump;
11---the second opening.
Detailed description of the invention
Embodiment 1
As shown in figure 11, a kind of surperficial sensing chip encapsulating structure, comprise and there is relative first surface 101 and the surperficial sensing chip of second surface 102, described first surface 101 has induction zone 103 and is positioned at several weld pads 104 of described induction zone 103 periphery, and weld pad 104 described in several is electrically connected with described induction zone 103; Described first surface 101 is formed with the first plastic packaging layer 2 exposing described induction zone 103, the described induction zone 103 exposed is provided with over cap 6; Position relative with each described weld pad 104 on described second surface 102 is formed with the first opening 3, the inwall of described second surface 102 and described first opening 3 is formed with the insulating barrier 4 exposing described weld pad 104, described insulating barrier 4 is formed with the metal wiring layer 5 being electrically connected described weld pad 104 expose portion; Form matcoveredn outside described metal wiring layer 5, and described protective layer is one deck second plastic packaging layer 7; Metal wiring layer 5 on described second surface 102 is formed and passes described second plastic packaging layer 7 for connecting the solder bump 10 of external devices, in order to connect external circuit.
In said structure, by forming first opening 3 relative with the weld pad 104 of the first surface 101 of induction zone 103 on the second surface 102 of surperficial sensing chip, and in second surface 102 and the first opening 3, form insulating barrier 4 and metal wiring layer 5 successively, can by the second surface 102 electrically guiding to surperficial sensing chip of the weld pad 104 of surperficial sensing chip first surface 101, like this, when being connected with external devices, the second weld pad on such as substrate, can by connecting some solder bumps of metal wiring layer and the Flip Chip Bond Technique of the second weld pad described in second surface, replace the wire bonding technique of routing, therefore, the encapsulation volume reducing surperficial sensing chip can be reached, meet the object of the requirement of surperficial sensing chip miniaturization.In addition, carry out plastic packaging by the first surface 101 at surperficial sensing chip with a kind of capsulation material of second surface 102, form the first plastic packaging layer 2 and the second plastic packaging layer 7, can be used for the damage preventing outer bound pair chip, improve the reliability of surperficial sensing chip.In order to improve the sensitivity of induction zone 103, the present embodiment is selected to cover with one deck over cap 6 on induction zone 103.Preferred, the material of this over cap 6 can be the protective materials such as glass, film and glass ceramics, and the thickness of over cap 6 is between 1 micron-400 microns.
Preferably, the material of described metal wiring layer 5 is copper or aluminium or nickel or gold or titanium or alloy.
Preferably, described first opening 3 is groove, the combination in groove and hole or straight hole, and the structure of groove is see Fig. 3 a and Fig. 3 b, and wherein Fig. 3 a is the first hatch frame schematic diagram that second surface is overlooked, Fig. 3 b be Fig. 3 a AA ' to profile; The combining structure in groove and hole is see Fig. 9 a and Fig. 9 b, and wherein Fig. 9 a is the first hatch frame schematic diagram that second surface is overlooked, and Fig. 9 b is the profile of Fig. 9 a at BB ' place; The structure of straight hole is see Figure 10 a and 10b, and wherein Figure 10 a is the first hatch frame schematic diagram that second surface is overlooked, and Figure 10 b is the profile of Figure 10 a at CC ' place.
As a kind of preferred embodiment, the preparation method of the surperficial sensing chip encapsulating structure of the present embodiment 1, comprises the steps:
A, see Fig. 1, prepare a wafer with several surperficial sensing chip unit, each described surperficial sensing chip unit has first surface 101 and the second surface 102 relative with first surface 101; The first surface 101 of described surperficial sensing chip unit has induction zone 103 and the some weld pads 104 being positioned at described induction zone 103 periphery, weld pad 104 described in several is electrically connected with described induction zone 103;
B, see Fig. 2, the described first surface 101 of described wafer is formed and covers the over cap 6 of described induction zone 103, and form one deck first plastic packaging layer 2 on the periphery of over cap 6 and the described first surface 101 of periphery;
C, carry out thinning to the described second surface 102 of described wafer;
D, see Fig. 3 b, position relative with the weld pad 104 of each surperficial sensing chip unit on the second surface 102 of described wafer carves the first opening 3, exposes the weld pad 104 of its correspondence;
E, see Fig. 4 and Fig. 5, the second surface 102 of described wafer formed in steps d and the inwall of each described first opening 3 cover a layer insulating 4, and the weld pad 104 of described first opening 3 correspondence is come out; During concrete enforcement, first opening 3 is formed by etching and machine cuts, first slot opening is formed by photoetching process at wafer second surface 102, then the wafer of etched recesses aperture position, insulating barrier 4 is laid in the face comprising etched recesses surface and wafer second surface 102, finally, to carrying out the sidewall that machine cuts exposes weld pad 104 at the bottom of etched recesses.
F, see Fig. 6, on the described insulating barrier 4 that step e is formed and the position of described weld pad 104 exposed lay layer of metal wiring layer 5, namely weld pad 104 is electrically guided on the second surface 102 of surperficial sensing chip by metal wiring layer 5.
G, see Fig. 7, the metal wiring layer 5 formed in step f is outer forms one deck second plastic packaging layer 7, and the second opening 11 that reserved metal wiring layer 5 is connected with external devices on the second plastic packaging layer 7 of second surface 102.
H, see Fig. 8, step g formed the second opening 11 place plant solder bump 10;
I, to step H-shaped become wafer cut, form single surperficial sensing chip encapsulating structure.
Embodiment 2
The present embodiment 2 comprises all technical characteristics in embodiment 1, as shown in figure 12, its difference is, separately be provided with a functional chip 9, described functional chip 9 is electrically connected with the metal wiring layer 5 on described second surface 102, and functional chip 9 is fixedly arranged between insulating barrier 4 on second surface 102 and the second plastic packaging layer 7, and described functional chip 9 is electrically connected with the metal wiring layer 5 on described second surface 102 by the mode of wire bonding.
The preparation method of the surperficial sensing chip encapsulating structure of the present embodiment 2, comprises the steps:
A, see Fig. 1, prepare a wafer with several surperficial sensing chip unit, each described surperficial sensing chip unit has first surface 101 and the second surface 102 relative with first surface 101; The first surface 101 of described surperficial sensing chip unit has induction zone 103 and the some weld pads 104 being positioned at described induction zone 103 periphery, described in several, weld pad 104 and described induction zone 103 are electrically connected;
B, see Fig. 2, the described first surface 101 of described wafer is formed and covers the over cap 6 of described induction zone 103, and form one deck first plastic packaging layer 2 on the periphery of over cap 6 and the described first surface 101 of periphery;
C, carry out thinning to the described second surface 102 of described wafer;
D, see Fig. 3 b, position relative with the weld pad 104 of each surperficial sensing chip unit on the second surface 102 of described wafer carves the first opening 3, exposes the weld pad 104 of its correspondence;
E, see Fig. 4 and Fig. 5, the second surface 102 of described wafer formed in steps d and the inwall of each described first opening 3 cover a layer insulating 4, and the weld pad 104 of each described first opening 3 correspondence is come out;
F, see Fig. 6, on the described insulating barrier 4 that step e is formed and the position of described weld pad 104 exposed lay layer of metal wiring layer 5, and expose the insulating barrier 4 pre-fixing functional chip 9 position, wherein, metal wiring layer 5 forms several terminal pads for linkage function chip 9;
G, provide a functional chip 9, the insulating barrier 4 that step f exposes fixes this functional chip 9, and by the mode of wire bonding, functional chip 9 is electrically connected with the metal wiring layer 5 on described second surface 102; During concrete enforcement, functional chip 9 can be fixed on the insulating barrier 4 on wafer second surface 102 by viscose, then is connected with the metal wiring layer 5 on second surface 102 in modes such as bonding wires.
H, the metal wiring layer 5 formed in step g is outer and functional chip 9 is outer forms one deck second plastic packaging layer 7, and the second opening 11 that reserved metal wiring layer 5 is connected with external devices on the second plastic packaging layer 7 of second surface 102.
I, step H-shaped become the second opening 11 place plant solder bump 10;
J, to step I formed wafer cut, form single surperficial sensing chip encapsulating structure.
Embodiment 3
The present embodiment 3 comprises all technical characteristics in embodiment 1, as shown in figure 13, its difference is, 1, a functional chip 9 is separately provided with, described functional chip 9 is electrically connected with the metal wiring layer 5 on described second surface 102, and functional chip 9 is electrically connected with the metal wiring layer 5 on described second surface 102 by the mode of flip chip bonding.2, first surface 101 is formed the over cap 6 covering described induction zone 103 to be replaced by one deck first plastic packaging layer 2; first plastic packaging layer 2 covers in described induction zone 103; the the first plastic packaging layer 2 covering in described induction zone 103 has setting thickness, and this first plastic packaging layer material can have relatively large Mohs' hardness.
The preparation method of the surperficial sensing chip encapsulating structure of the present embodiment 3, comprises the steps:
A, see Fig. 1, prepare a wafer with several surperficial sensing chip unit, each described surperficial sensing chip unit has first surface 101 and the second surface 102 relative with first surface 101; The first surface 101 of described surperficial sensing chip unit has induction zone 103 and the some weld pads 104 being positioned at described induction zone 103 periphery, described in several, weld pad 104 and described induction zone 103 are electrically connected;
B, on the described first surface 101 of described wafer, form the first plastic packaging layer 2; And described first plastic packaging layer 2 covers in described induction zone 103, the first plastic packaging layer 2 covering in described induction zone 103 has setting thickness;
C, carry out thinning to the described second surface 102 of described wafer;
D, position relative with the weld pad 104 of each surperficial sensing chip unit on the second surface 102 of described wafer carve the first opening 3, first opening 3 and remove base material above corresponding weld pad 104;
E, the second surface 102 of described wafer formed in steps d and the inwall of each described first opening 3 cover a layer insulating 4, and the weld pad 104 of described first opening 3 correspondence is come out;
Layer of metal wiring layer 5 is laid on f, the described insulating barrier 4 that formed in step e and the position of described weld pad 104 exposed;
G, separately provide a functional chip 9, described functional chip 9 is electrically connected with the metal wiring layer 5 on described second surface 102 by the mode of flip chip bonding.
H, the metal wiring layer 5 outer formation one deck second plastic packaging layer 7 formed in step g, and the second opening 11 that reserved metal wiring layer 5 is connected with external devices on the second plastic packaging layer 7 of second surface 102.
I, step H-shaped become the second opening 11 place plant solder bump 10;
J, to step I formed wafer cut, form single surperficial sensing chip encapsulating structure.
Embodiment 4
The present embodiment 4 comprises all technical characteristics in embodiment 1, and as shown in figure 14, its difference is, forms matcoveredn outside described metal wiring layer 5, and described protective layer is one deck insulating protective layer 8.Insulating protective layer 8, for preventing metal wiring layer 5 oxidized, can be photoresist, is convenient to exposure second opening 11.
The preparation method of the surperficial sensing chip encapsulating structure of the present embodiment 4, comprises the steps:
A, see Fig. 1, prepare a wafer with several surperficial sensing chip unit, each described surperficial sensing chip unit has first surface 101 and the second surface 102 relative with first surface 101; The first surface 101 of described surperficial sensing chip unit has induction zone 103 and the some weld pads 104 being positioned at described induction zone 103 periphery, described in several, weld pad 104 and described induction zone 103 are electrically connected;
B, see Fig. 2, the described first surface 101 of described wafer is formed and covers the over cap 6 of described induction zone 103, and form one deck first plastic packaging layer 2 on the periphery of over cap 6 and the described first surface 101 of periphery;
C, carry out thinning to the described second surface 102 of described wafer;
D, see Fig. 3 b, position relative with the weld pad 104 of each surperficial sensing chip unit on the second surface 102 of described wafer carves the base material above weld pad 104 that the first opening 3, first opening 3 removes its correspondence;
E, see Fig. 4 and Fig. 5, the second surface 102 of described wafer formed in steps d and the inwall of each described first opening 3 cover a layer insulating 4, and the weld pad 104 of each described first opening 3 correspondence is come out;
F, see Fig. 6, on the described insulating barrier 4 that step e is formed and the position of described weld pad 104 exposed lay layer of metal wiring layer 5;
G, see Fig. 7, the metal wiring layer 5 formed in step f is outer forms one deck insulating protective layer 8, and the second opening 11 that reserved metal wiring layer 5 is connected with external devices on the insulating protective layer 8 of second surface 102.
H, see Fig. 8, step g formed the second opening 11 place plant solder bump 10;
I, to step H-shaped become wafer cut, form single surperficial sensing chip encapsulating structure.
To sum up, the utility model proposes a kind of surperficial sensing chip encapsulating structure, this encapsulating structure can reduce package thickness, meets the requirement of surperficial sensing chip miniaturization; Be arranged with plastic packaging layer outside sensing chip in this encapsulating structure, the reliability of sensing chip can be improved; This encapsulating structure is convenient in conjunction with other functional chips or substrate, strengthens the using function of chip.This preparation method utilizes crystal wafer chip dimension encapsulation technology, first carries out overall package, then wafer is cut into single chips, reduces production cost.
Above embodiment is with reference to accompanying drawing, is described in detail to preferred embodiment of the present utility model.Those skilled in the art by carrying out amendment on various forms or change to above-described embodiment, but when not deviating from essence of the present utility model, drops within protection domain of the present utility model.
Claims (10)
1. a surperficial sensing chip encapsulating structure, it is characterized in that: comprise and there is relative first surface (101) and the surperficial sensing chip (1) of second surface (102), described first surface has induction zone (103) and is positioned at several weld pads (104) of described induction zone periphery, and weld pad described in several and described induction zone are electrically connected; Described first surface is formed with the first plastic packaging layer (2) exposing described induction zone; Position relative with each described weld pad on described second surface is formed with the first opening (3), the inwall of described second surface and described first opening is formed with the insulating barrier (4) exposing described weld pad, described insulating barrier is formed with the metal wiring layer (5) being electrically connected described weld pad expose portion; Described metal wiring layer forms matcoveredn outward.
2. surperficial sensing chip encapsulating structure according to claim 1, is characterized in that: described first plastic packaging layer (2) covers in described induction zone, and the first plastic packaging layer covering in described induction zone has setting thickness.
3. surperficial sensing chip encapsulating structure according to claim 1, is characterized in that: the described induction zone exposed is provided with over cap (6).
4. surperficial sensing chip encapsulating structure according to claim 1, is characterized in that: described protective layer is the second plastic packaging layer (7) or insulating protective layer (8).
5. surperficial sensing chip encapsulating structure according to claim 4, is characterized in that: be separately provided with one or more functional chip (9), described functional chip is electrically connected with the metal wiring layer on described second surface.
6. surperficial sensing chip encapsulating structure according to claim 5; it is characterized in that: when described protective layer is described second plastic packaging layer; described functional chip is fixedly arranged between insulating barrier on described second surface and the second plastic packaging layer, and described functional chip (102) is electrically connected with the metal wiring layer on described second surface by the mode of wire bonding.
7. surperficial sensing chip encapsulating structure according to claim 5, is characterized in that: described functional chip (9) is electrically connected with the metal wiring layer on described second surface by the mode of flip chip bonding.
8. surperficial sensing chip encapsulating structure according to claim 1; it is characterized in that: the described protective layer of described second surface (102) is provided with the solder bump (10) that some and described metal wiring layer is connected, and described solder bump (10) is for being electrically connected external devices.
9. surperficial sensing chip encapsulating structure according to claim 1, is characterized in that: the material of described metal wiring layer (5) is copper or aluminium or nickel or gold or titanium or alloy.
10. surperficial sensing chip encapsulating structure according to claim 1, is characterized in that: the combination that described first opening (3) is groove or groove and hole or straight hole.
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| CN201420858896.2U CN204508799U (en) | 2014-12-30 | 2014-12-30 | Surface sensing chip encapsulating structure |
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| CN201420858896.2U CN204508799U (en) | 2014-12-30 | 2014-12-30 | Surface sensing chip encapsulating structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104495741A (en) * | 2014-12-30 | 2015-04-08 | 华天科技（昆山）电子有限公司 | Packaging structure for surface-sensing chip and fabrication method |
| CN106876289A (en) * | 2017-03-09 | 2017-06-20 | 华进半导体封装先导技术研发中心有限公司 | A kind of chip and its method for packing |
| CN107248505A (en) * | 2017-06-30 | 2017-10-13 | 苏州科阳光电科技有限公司 | A kind of encapsulating structure and method for packing of bio-identification chip |
-
2014
- 2014-12-30 CN CN201420858896.2U patent/CN204508799U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104495741A (en) * | 2014-12-30 | 2015-04-08 | 华天科技（昆山）电子有限公司 | Packaging structure for surface-sensing chip and fabrication method |
| CN106876289A (en) * | 2017-03-09 | 2017-06-20 | 华进半导体封装先导技术研发中心有限公司 | A kind of chip and its method for packing |
| CN106876289B (en) * | 2017-03-09 | 2019-05-21 | 华进半导体封装先导技术研发中心有限公司 | A kind of packaging method of chip |
| CN107248505A (en) * | 2017-06-30 | 2017-10-13 | 苏州科阳光电科技有限公司 | A kind of encapsulating structure and method for packing of bio-identification chip |
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Effective date of registration: 20190108 Address after: 710018 123 Fengcheng No. 5 Road, Xi'an Economic and Technological Development Zone, Shaanxi Province Patentee after: Alex Hua Tian Hui Chuang Technology (Xi'an) Co., Ltd. Address before: 215300 No. 112, Longteng Road, Kunshan Development Zone, Suzhou, Jiangsu Patentee before: Alex Hua Tian Technology (Kunshan) Electronics Co., Ltd. |
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| TR01 | Transfer of patent right |