CN204029810U - A kind of encapsulating structure - Google Patents
A kind of encapsulating structure Download PDFInfo
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- CN204029810U CN204029810U CN201420347904.7U CN201420347904U CN204029810U CN 204029810 U CN204029810 U CN 204029810U CN 201420347904 U CN201420347904 U CN 201420347904U CN 204029810 U CN204029810 U CN 204029810U
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- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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Abstract
A kind of encapsulating structure, comprise: image sensor chip, described image sensor chip has first surface and relative with described first surface second, image sensor chip first surface has photo-sensitive cell and the first pad around described photo-sensitive cell, in image sensor chip, there is metal column, and one end of metal column is electrically connected with the first pad, the other end relative with described one end flushes with image sensor chip second face; Signal processing chip, signal processing chip have the 3rd and with described 3rd relative fourth face, signal processing chip the 3rd mask has the second pad, and described signal processing chip the 3rd and image sensor chip second fixed engagement, described second pad is electrically connected with metal column; Run through the through hole of described signal processing chip fourth face, and described through hole exposes the second bond pad surface.The utility model, by being provided separately image sensor chip and signal processing chip, improves encapsulation performance.
Description
Technical field
The utility model relates to semiconductor packaging, particularly a kind of encapsulating structure.
Background technology
Image sensing chip a kind ofly can experience extraneous light and convert thereof into the chip of the signal of telecommunication.After image sensing chip manufacturing completes, then by carrying out a series of packaging technology to image sensing chip, thus form packaged image sensor, for the various electronic equipments of such as digital camera, Digital Video etc.
In prior art, image sensing chip is by image sensing (CIS, Contact Image Sensor) unit and signal transacting (DSP, Digital Signal Processor) unit is dimerous, same chip arranges image sensing cell and signal processing unit simultaneously, wherein, image sensing cell is used for receiving optical signals and is converted into the signal of telecommunication, and the signal of telecommunication that signal processing unit is used for light signal transforms processes.
But, in prior art, when image sensing cell and signal processing unit are set on one chip, chip design difficulty and formed encapsulating structure performance have much room for improvement.
Utility model content
The problem that the utility model solves is to provide a kind of encapsulating structure, and image sensor chip and signal processing chip are what be provided separately, improves encapsulation performance.
For solving the problem, the utility model provides a kind of encapsulating structure, comprise: image sensor chip, described image sensor chip has first surface and relative with described first surface second, described image sensor chip first surface has photo-sensitive cell and the first pad around described photo-sensitive cell, have metal column in described image sensor chip, and one end of described metal column is electrically connected with the first pad, the other end relative with described one end flushes with image sensor chip second face; Signal processing chip, described signal processing chip have the 3rd and with described 3rd relative fourth face, described signal processing chip the 3rd mask has the second pad, and described signal processing chip the 3rd and image sensor chip second fixed engagement, described second pad is electrically connected with metal column; Run through the through hole of described signal processing chip fourth face, and described through hole exposes the second bond pad surface.
Optionally, adhesion layer is formed with between described image sensor chip and signal processing chip.
Optionally, also comprise: the opening being positioned at described second pad and adhesion layer, open bottom exposes metal column surface, and described opening and through hole run through mutually.
Optionally, also comprise: the conductive layer of filling full described opening, and described conductive layer contacts with metal column and the second pad.
Optionally, also comprise: the insulating barrier being positioned at through-hole side wall and signal processing chip fourth face; Be positioned at the metal redistribution layer of surface of insulating layer, and described metal redistribution layer is also positioned at conductive layer surface; Be positioned at the solder-bump on the metal redistribution layer surface of described signal processing chip fourth face.
Optionally, also comprise: the solder-bump of filling full described through hole, described solder-bump contacts with conductive layer, and described solder-bump top is higher than signal processing chip fourth face.
Optionally, between described solder-bump and through-hole side wall, be formed with insulating barrier, described insulating barrier is also covered in signal processing chip fourth face.
Optionally, described signal processing chip the 3rd directly contacts with image sensor chip second, and described second bond pad surface contacts with metal column surface.
Optionally, also comprise: the insulating barrier being positioned at described through-hole side wall and signal processing chip fourth face; Be positioned at the metal redistribution layer of described via bottoms and surface of insulating layer; Be positioned at the solder-bump on the metal redistribution layer surface of described signal processing chip fourth face.
Optionally, fill the solder-bump of full described through hole, described solder-bump contacts with the second pad, and described solder-bump top is higher than signal processing chip fourth face.
Optionally, also comprise: the substrate being positioned at image sensor chip first surface.
Optionally, also adhesive-layer is formed with between described substrate and image sensor chip first surface.
Compared with prior art, the technical solution of the utility model has the following advantages:
The utility model embodiment provides the encapsulating structure that a kind of structural behaviour is superior, image sensor chip first surface has photo-sensitive cell and the first pad around described photo-sensitive cell, in described image sensor chip, there is metal column, and described metal column one end is electrically connected with the first pad, the other end relative with described one end flushes with image sensor chip second face; Signal processing chip the 3rd and image sensor chip second fixed engagement, signal processing chip the 3rd mask has the second pad, and described second pad is electrically connected with metal column, thus the image sensor chip in encapsulating structure is electrically connected with signal processing chip; Run through the through hole of described signal processing chip fourth face, and described through hole exposes the second bond pad surface, described in the second bond pad surface of exposing for being electrically connected with external circuit, thus encapsulating structure is electrically connected with external circuit.In the utility model encapsulating structure, image sensor chip and signal processing chip are oppositely arranged, the restriction being subject to the other side between image sensor chip and signal processing chip is little, and therefore image sensor chip and signal processing chip all can obtain the performance of the best, improve encapsulation performance.
Meanwhile, because image sensor chip and signal processing chip are not arranged on the same chip, hinge structure, the area of the image sensor chip of the utility model embodiment is less, therefore, the design cost of image sensor chip reduces, thus makes the cost of encapsulating structure low.Further, because image sensor chip and signal processing chip are provided separately, image sensor chip and signal processing chip can combination in any, make encapsulating structure have higher flexibility.
Further, have opening in the utility model embodiment in the second pad and adhesion layer, open bottom exposes metal column surface, and described opening and through hole run through mutually; Fill the conductive layer of full gate mouth, and described conductive layer contacts with metal column and the second pad, by described conductive layer, the second pad and metal column are electrically connected, thus realize the object that signal processing chip is electrically connected with image sensor chip.Described adhesion layer improves the adhesiveness between image sensor chip and signal processing chip, thus improves the reliability of encapsulating structure.
Further, the utility model embodiment is provided with substrate at image sensor chip first surface, described substrate plays the effect supporting signal processing chip and image sensor chip, improve the mechanical strength of signal processing chip and image sensor chip, thus improve the reliability of encapsulating structure further.
Accompanying drawing explanation
Fig. 1 to Figure 13 is the cross-sectional view of the utility model one embodiment encapsulation process;
Figure 14 to Figure 17 is the cross-sectional view of another embodiment encapsulation process of the utility model.
Embodiment
From background technology, the existing performance comprising the encapsulating structure of image sensing cell and signal processing unit has much room for improvement.
Find after deliberation, in prior art, usually image sensing cell and signal processing unit are encapsulated on the same chip.General, chip obtains after cutting crystal wafer, therefore image sensor chip and signal processing chip are produced in same wafer by prior art, and described wafer can be described as image sensing wafer, and signal processing chip is produced in image sensing wafer by prior art.
In prior art, image sensor chip should be formed form signal processing chip again in image sensing wafer, need to consider the arrangement between image sensor chip and signal processing chip and interconnection, this increases causing the difficulty of chip manufacturing process and packaging technology; Simultaneously, because the cost of image sensing wafer is high, signal processing chip is arranged on after in image sensing wafer, in order to consider the interconnection between signal processing chip, the area of image sensing wafer will certainly be increased, cause chip manufacturing cost and packaging technology cost greatly to increase; And, during owing to forming signal processing chip and image sensor chip on same wafer, in order to consider arrangement between the two and interconnection, signal processing chip and image sensor chip are restricted mutually, make signal processing chip and image sensor chip be difficult to reach best performance, therefore cause the poor-performing of encapsulating structure.
The above analysis is known, if image sensing cell and signal processing unit are peeled away, form two independent wafer (image sensing wafer and signal transacting wafers, wherein, image sensing wafer is for the formation of image sensor chip, and signal transacting wafer is for the formation of signal processing chip), and then by two independent wafer level packagings in same encapsulating structure, so then can solve the problem that encapsulation difficulty is large and encapsulation performance is poor
Meanwhile, if peeled away by two parts, form two independent wafers, so image sensor chip and signal processing chip can combination in any, and relatively traditional encapsulating structure, flexibility can improve a lot.And when making image sensing wafer, do not need for signal processing chip reserves arrangement space, therefore image sensing wafer can do smaller, thus save packaging technology cost.
For this reason, the utility model provides a kind of encapsulating structure, comprise: image sensor chip, described image sensor chip has first surface and relative with described first surface second, described image sensor chip first surface has photo-sensitive cell and the first pad around described photo-sensitive cell, have metal column in described image sensor chip, and one end of described metal column is electrically connected with the first pad, the other end relative with described one end flushes with image sensor chip second face; Signal processing chip, described signal processing chip have the 3rd and with described 3rd relative fourth face, described signal processing chip the 3rd mask has the second pad, and described signal processing chip the 3rd and image sensor chip second fixed engagement, described second pad is electrically connected with metal column; Run through the through hole of described signal processing chip fourth face, and described through hole exposes the second bond pad surface.The utility model reduces the difficulty of interconnection of arranging between image sensor chip and signal processing chip, thus reduces packaging technology difficulty; And be provided separately image sensor chip and signal processing chip, make image sensor chip and signal processing chip all have best performance, thus improve encapsulation performance.
For enabling above-mentioned purpose of the present utility model, feature and advantage more become apparent, and are described in detail specific embodiment of the utility model below in conjunction with accompanying drawing.
Fig. 1 to Figure 13 is the structural representation of the utility model one embodiment encapsulation process.
Please refer to Fig. 1, image sensing wafer 100 is provided.
It is the chip area of matrix arrangement and the Cutting Road center line 110 between chip area that described image sensing wafer 100 comprises some, have an image sensor chip in each chip area, each image sensor chip correspondence forms an encapsulating structure.Follow-up when cutting image sensing wafer 100, along described Cutting Road center line 110, image sensing wafer 100 is cut into several image sensor chips.
In the present embodiment, owing to not being formed with signal processing unit (or signal processing chip) in image sensing wafer 100, without the need to considering the arrangement interconnection problems between signal processing unit, the image sensor chip therefore in image sensing wafer 100 has best performance; Further, image sensing wafer 100 does not need for signal processing chip reserves arrangement space, and therefore, compared with prior art, the area of the image sensor chip in image sensing wafer 100 is little many.Compared with prior art, for the image sensor chip providing equal number, in the present embodiment, the area of image sensing wafer 100 is little many, thus reduces process costs.
Described image sensing wafer 100 has first surface and relative with described first surface second, described first surface is image sensing wafer 100 surface with photo-sensitive cell 101 and the first pad 102, and described second is pending thinning and surface that is follow-up and signal transacting wafer fixed engagement.
The first surface of described image sensing wafer 100 chip area has some photo-sensitive cells 101 and the first pad 102 around described photo-sensitive cell 101.The associated circuit being formed with image sensor unit in described photo-sensitive cell 101 and being connected with image sensor unit, utilize described image sensor unit by extraneous light receiver and convert electrical signal to, by described associated circuit, electrical signal is passed to the first pad 102, the metal redistribution layer, the solder-bump that recycle the first pad 102 and follow-up formation send electrical signal to other circuit.General, described photo-sensitive cell 101 top is higher than the first pad 102 top.
In the present embodiment, for the ease of wiring, photo-sensitive cell 101 is positioned at the centre position of chip area, first pad 102 is positioned at the marginal position of chip area, the follow-up position in described first pad 102 correspondence forms the through hole running through described image sensing wafer 100 thickness, utilizes through hole to be connected with the follow-up signal transacting wafer electricity provided by the first pad 102 being positioned at image sensing wafer 100 first surface.
It should be noted that, in other embodiments, the position of the first pad and photo-sensitive cell can adjust flexibly according to the requirement of actual process.
In the present embodiment, the first pad 102 of different chip area is independent setting; In other embodiments, the first pad be connected can be formed at adjacent chip area, namely the first pad formed crosses over Cutting Road region, this is because: Cutting Road region can be cut after packaging is accomplished and hold, first pad in described leap Cutting Road region is cut to be opened, and can not affect the electric property of encapsulating structure.
After formation first pad 102 and photo-sensitive cell 101, also comprise step: form at the first surface of described image sensing wafer 100 chip area the metal interconnect structure be connected with photo-sensitive cell 101 electricity by described first pad 102.
In described image sensing wafer 100, there is metal column 103, described metal column 103 one end is electrically connected with the first pad 102, the other end relative with described one end is positioned at image sensing wafer 100, and between described metal column 103 other end and image sensing wafer 100 second, there is certain distance, described metal column 103 is the medium between follow-up connection image sensing wafer 100 and signal processing chip.
Please refer to Fig. 2, form substrate 105 at described image sensing wafer 100 first surface.
In the present embodiment, the size of described substrate 105 and the measure-alike of image sensing wafer 100.
Described substrate 105 provides a supporting role for image sensing wafer 100, improves the mechanical strength of image sensing wafer 100, prevents image sensing wafer 100 from the potting process such as follow-up thinning etching, splintering problem occurring; Described substrate 105 is also for the follow-up signal transacting wafer provided provides a supporting role.
The material of described substrate 105 is unorganic glass, polymethyl methacrylate, silicon, IR glass or AR glass.If follow-up, after formation encapsulating structure, photo-sensitive cell 101 needs to receive extraneous light, substrate 105 described in extraneous light therethrough, and make photo-sensitive cell 101 receive extraneous light smoothly, then substrate 105 has the performance of printing opacity
In the present embodiment, the material of described substrate 105 is the unorganic glass of solid-state shape.In order to improve the adhesiveness between substrate 105 and image sensing wafer 100, preventing substrate 105 in follow-up encapsulation process from coming off from image sensing wafer 100, between substrate 105 and image sensing wafer 100, forming adhesive-layer 104.Concrete, form adhesive-layer 104 on substrate 105 surface, image sensing wafer 100 first surface and the substrate 105 with adhesive-layer 104 are carried out pressing.Described adhesive-layer 104 improves the adhesiveness between substrate 104 and image sensing wafer 100.
As a specific embodiment, adopt coating process at substrate 105 surface coating liquid state glue, by described substrate 105 and the pressing of image sensing wafer 100 first surface with liquid glue, when being converted into the adhesive-layer 104 between image sensing wafer 100 and substrate 105 after liquid glue solidification.
Please refer to Fig. 3, reduction processing is carried out to described image sensing wafer 100 second face, until expose metal column 103 surface, metal column 103 surface is flushed with image sensing wafer 100 second face.
After reduction processing is carried out to image sensing wafer 100, be beneficial to the encapsulating structure of follow-up formation thinner thickness; Further, after reduction processing, is come out in metal column 103 surface, the follow-up signal transacting wafer provided is electrically connected with metal column 103, thus realizes the electrical connection between signal transacting wafer and image sensing wafer 100.
The technique of described reduction processing can be mechanical lapping or cmp etc.
After reduction processing, metal column 103 one end is electrically connected with the first pad 102, and the other end relative with described one end flushes with image sensing wafer 100 second face.
Please refer to Fig. 4, signal transacting wafer 107 be provided, described signal transacting wafer 107 have the 3rd and with described 3rd relative fourth face, and signal transacting wafer 107 the 3rd mask has the second pad 108.
Have multiple signal processing chip in described signal transacting wafer 107, quantity and the position of described second pad 108 can need to determine according to actual process.
In the present embodiment, the size of described signal transacting wafer 107 and the consistent size of image sensing wafer 100, and, accordingly, described signal transacting wafer 107 has the first chip area (sign) and the first Cutting Road center line (sign) between the first chip area.
Owing to only having signal processing chip in signal transacting wafer 107, without the need to considering the location problem between signal processing chip and image sensor chip, the signal processing chip formed is made to have higher performance.
Please refer to Fig. 5, by described image sensing wafer 100 second and signal transacting wafer 107 the 3rd fixed engagement, make the second pad 108 corresponding with the position of metal column 103.
Described second pad 108 is corresponding with the position of metal column 103, and that is, the second pad 108 is positioned at immediately below metal column 103, and follow-up when etching second pad 108 forms opening, the bottom of the opening of formation can expose the surface of metal column 103.
In the present embodiment, in order to improve the adhesiveness between image sensing wafer 100 and signal transacting wafer 107, adhesion layer 106 is become at described image sensing wafer 100 second or signal transacting wafer 107 third surface shape, by described adhesion layer 106 by image sensing wafer 100 second and signal transacting wafer 107 the 3rd fixed engagement, and making the position of the second pad 108 correspond to the position of metal column 103, the first Cutting Road center line of signal transacting wafer 107 overlaps with the Cutting Road center line 110 of image sensing wafer 100.
The method of some glue, plastic roll or print glue is adopted to form described adhesion layer 106.
Please refer to Fig. 6, etching processing is carried out to described signal transacting wafer 107 fourth face, form the through hole 109 running through described signal transacting wafer 107 fourth face, and described through hole 109 exposes the second pad 108 surface.
The technique of described etching processing is dry etching.As a specific embodiment, the processing step forming through hole 109 comprises: form photoresist film at described signal transacting wafer 107 fourth face; Described photoresist film is exposed, development treatment, form patterned photoresist layer; With described patterned photoresist layer for mask, etch described signal transacting wafer 107 and form through hole 109, until expose the second pad 108 surface.
In the present embodiment, using plasma etching technics etches described signal transacting wafer 107, and the technological parameter of described plasma etching industrial is: etching gas comprises SF
6and C
4f
8, wherein, SF
6gas flow is 100sccm to 2000sccm, C
4f
8gas flow is 200sccm to 1000sccm, and etching source radio-frequency power is 1000 watts to 5000 watts, and etching bias voltage radio-frequency power is 0 watt to 500 watts, and etching cavity pressure is 10 millitorr to 200 millitorrs.
It should be noted that, in the present embodiment, described through hole 109 bottom-exposed goes out the second pad 108 part surface, namely, described through hole 109 bottom area is less than described second pad 108 surface area, its benefit is: until when exposing the first pad 102 surface bottom follow-up continuation etching through hole 109, described etching technics can etch the second pad 108 removed and come out, if is all come out in second pad 108 surface bottom through hole 109, then the second pad 108 is easily all etched removal, causes package failure; And in the present embodiment, the second pad 108 part surface is only exposed bottom through hole 109, after the second pad 108 bottom subsequent etching through hole 109, still remain with the second pad 108 of area in signal transacting wafer 107, realize the electrical connection between signal transacting wafer 107 and image sensing wafer 100 by remaining second pad 108.
In other embodiments of the utility model, via bottoms also can expose the second pad all surfaces, during follow-up the second pad bottom etching through hole, should be noted that and whole second bond-pad etch should not removed.
Please refer to Fig. 7, bottom described signal transacting wafer 107 fourth face, through hole 109 and sidewall formed insulating barrier 111.
Described insulating barrier 111 provides electric isolution for signal transacting wafer 107, and can play the effect of guard signal process wafer 107 fourth face.
Chemical vapour deposition (CVD), physical vapour deposition (PVD) or atom layer deposition process is adopted to form described insulating barrier 111; The material of described insulating barrier 111 is the insulating material such as silica, silicon nitride, silicon oxynitride or insulating resin.
In the present embodiment, the material of described insulating barrier 111 is silica.
Please refer to Fig. 8, etching removes the insulating barrier 111 be positioned at bottom through hole 109, and continuation etches the second pad 108 and adhesion layer 106 that are positioned at bottom through hole 109, until expose metal column 103 surface, in the second pad 108 and adhesion layer 106, forms opening 112.
In the present embodiment, described opening 112 bottom-exposed goes out metal column 103 surface, and go out the second pad 108 part surface due to through hole 109 bottom-exposed, therefore after formation opening 112, metal column 103 surface and the second pad 108 sidewall surfaces are exposed, and described opening 112 and through hole 109 run through mutually.
The object forming described opening 112 is: due to after opening 112 is formed, metal column 103 surface and the second pad 108 sidewall surfaces are exposed, follow-up after forming the conductive layer of filling full gate mouth 112, conductive layer not only contacts with metal column 103 but also contacts with the second pad 108, therefore by described conductive layer, metal column 103 and the second pad 108 are electrically connected, thus realize the object of electrical connection between signal transacting wafer 107 and image sensing wafer 100.
Radium art or etching technics is adopted to form described opening 112.
As a specific embodiment, the processing step adopting etching technics to form opening 112 comprises: form patterned photoresist layer on described insulating barrier 111 surface, described patterned photoresist layer exposes the insulating barrier 111 being positioned at through hole 109 lower surface; With described patterned photoresist layer for mask, etching removes the insulating barrier 111 be positioned at bottom through hole 109, continuation etches the second pad 108 and adhesion layer 106 that are positioned at bottom through hole 109, in the second pad 108 and adhesion layer 106, form opening 112, until expose metal column 103 surface.
In the present embodiment, Radium art is adopted to form described opening 112, the technological parameter of described Radium art is: frequency is 10kHZ to 200kHZ, power is 0.5watts to 5watts, spot size is 50 μm to 150 μm, hot spot translational speed is 100mm/sec to 300mm/sec, and number of repetition is 1 to 10 time.
Please refer to Fig. 9, form the conductive layer 116 of filling full gate mouth 112 (please refer to Fig. 8), form metal redistribution layer 113 on described insulating barrier 111 surface simultaneously, and described metal redistribution layer 113 is also positioned at conductive layer 116 surface, the second pad 108 and metal column 103 is electrically connected by conductive layer 116.
The material of described metal redistribution layer 113 comprises Cu, Al or W.In the present embodiment, metal redistribution layer 113 is identical with the material of conductive layer 116, and is formed in processing step.
As an embodiment, the forming step of described metal redistribution layer 113 and conductive layer 116 comprises: form the conductive layer 116 of filling full gate mouth 112, is covered in the metal film on described insulating barrier 111 surface, simultaneously in described formation simultaneously; Patterned photoresist layer is formed in described metallic film surface; With described patterned photoresist layer for metal film described in mask etching, form metal redistribution layer 113.
Please refer to Figure 10, form solder-bump 115 on metal redistribution layer 113 surface of described signal transacting wafer 107 fourth face.
In the present embodiment, described solder-bump 115 is electrically connected with conductive layer 116, concrete, by described metal redistribution layer 113, realizes the electrical connection between solder-bump 115 and conductive layer 116.Described solder-bump 115, for being electrically connected with external circuit, therefore can make metal column 103, second pad 108 be electrically connected with external circuit by described solder-bump 115.
The material of described solder-bump 115 is Sn, Au or Sn-Au alloy.Adopt screen printing and reflux technique or plant ball technique and form described solder-bump 115.
In the present embodiment, before formation solder-bump 115, form welding resisting layer 114 on metal redistribution layer 113, conductive layer 116 and insulating barrier 111 surface.The material of described welding resisting layer 114 is insulating material, plays the effect that protection metal redistribution layer 113 is not oxidized.
After formation welding resisting layer 114, etch described welding resisting layer 114 to form the groove exposing part metals redistributing layer 113 surface, in described groove, fill full solder-bump 115, described solder-bump 115 is electrically connected with metal redistribution layer 113.
In the present embodiment, by forming metal redistribution layer 113, solder-bump 115 is electrically connected with conductive layer 116.
In other embodiments of the utility model, as shown in figure 11, in order to reduce packaging technology step, improve packaging efficiency, the processing step forming conductive layer 116 and solder-bump 115 comprises: form the conductive layer 116 of filling full described opening 112 (please refer to Fig. 8); Form the solder-bump 115 of filling full described through hole 109 (please refer to Fig. 8), and described solder-bump 115 top is higher than signal transacting wafer 107 fourth face.And there is unnecessary electrical connection in order to avoid solder-bump 115 and signal transacting wafer 107, before formation solder-bump 115, form insulating barrier 111 at through hole 109 sidewall, described insulating barrier 111 is also positioned at signal transacting wafer 107 fourth face.
Concrete, in one embodiment, conductive layer 116 is formed in processing step with solder-bump 115, and the material of conductive layer 116 is identical with the material of solder-bump 115.In another embodiment, also can first form conductive layer 116, then form solder-bump 115, and conductive layer 116 is different from the material of solder-bump 115.
Please refer to Figure 12, cut described image sensing wafer 100 (please refer to Figure 10) and signal transacting wafer 107 (please refer to Figure 10) along described Cutting Road center line 110 (please refer to Figure 10), form some single encapsulating structures.
The technique of cutting described image sensing wafer 100 and signal transacting wafer 107 is slicer cutting or laser cutting.Because laser cutting has less kerf width, improve the accuracy of cutting technique, in the present embodiment, adopt laser to cut image sensing wafer 100 and signal transacting wafer 107.
Cut described image sensing wafer 100 and form some image sensor chips 200, cut described signal transacting wafer 107 and form some signal processing chips 207.
Because image sensing wafer 100 and signal transacting wafer 107 are separately formed, reduce the formation process difficulty of image sensing wafer 100 and signal transacting wafer 107, and avoid considering image sensor chip 200 and the arrangement interconnection problems of signal processing chip 207 in same wafer, image sensor chip 200 and signal processing chip 207 can not be subject to restriction each other, therefore the image sensor chip 200 in image sensing wafer 100 has optimum performance, same, signal processing chip 207 in signal transacting wafer 107 also has optimum performance, therefore the performance of the encapsulating structure of the present embodiment formation is high.
In another embodiment of the utility model, when solder-bump 115 fills full through hole, then after Cutting Road center line 110 (please refer to Figure 11) cutting image sensing wafer 100 (please refer to Figure 11) and signal transacting wafer 107 (please refer to Figure 11), the encapsulating structure formed as shown in figure 13, solder-bump 115 fills full through hole, conductive layer 116 fills full gate mouth, solder-bump 115 contacts with conductive layer 116, by conductive layer 116, second pad 108 and metal column 103 are electrically connected, and solder-bump 115 top is higher than signal processing chip 207 surface.
Accordingly, the utility model embodiment also provides a kind of encapsulating structure, please refer to Figure 12, and described encapsulating structure comprises:
Image sensor chip 200, described image sensor chip 200 has first surface and relative with described first surface second, described image sensor chip 200 first surface has photo-sensitive cell 101 and the first pad 102 around described photo-sensitive cell 101, in described image sensor chip 200, there is metal column 103, and one end of described metal column 103 is electrically connected with the first pad 102, the other end relative with described one end flushes with image sensor chip 200 second face;
Signal processing chip 207, described signal processing chip 207 have the 3rd and with described 3rd relative fourth face, described signal processing chip 207 the 3rd mask has the second pad 108, and described signal processing chip 207 the 3rd and image sensor chip 200 second fixed engagement, described second pad 108 is electrically connected with metal column 103;
Run through the through hole of described signal processing chip 207 fourth face, and described via bottoms exposes the second pad 108 surface.
In the present embodiment, adhesion layer 106 is formed between described image sensor chip 200 and signal processing chip 207, improve the adhesiveness between image sensor chip 200 and signal processing chip 207, prevent from being separated between image sensor chip 200 with signal processing chip 207.
In the present embodiment, described via bottoms exposes the second pad 108 part surface, described encapsulating structure also comprises: the opening being positioned at the second pad 108 and adhesion layer 106, and open bottom exposes metal column 103 surface, and described opening and through hole run through mutually.
Described encapsulating structure also comprises: the conductive layer 116 of filling full described opening, and described conductive layer 116 contacts with metal column 103 and the second pad 108, by described conductive layer 116, second pad 108 and metal column 103 is electrically connected.
In the present embodiment, described encapsulating structure also comprises: the insulating barrier 111 being positioned at through-hole side wall and signal processing chip 207 fourth face; Be positioned at the metal redistribution layer 113 on insulating barrier 111 surface, and described metal redistribution layer 113 is also positioned at conductive layer 116 surface; Be positioned at the solder-bump 115 on metal redistribution layer 113 surface of described signal processing chip 207 fourth face.
In order to improve the reliability of encapsulating structure, also comprise: the welding resisting layer 114 being positioned at described metal redistribution layer 113 and conductive layer 112 surface; Be positioned at the groove of the welding resisting layer 114 of described signal processing chip 207 fourth face, and described bottom portion of groove exposes metal redistribution layer 113 surface, described solder-bump 115 fills full described groove.
Described metal redistribution layer 113 contacts with conductive layer 116 surface, described conductive layer 116 contacts with the second pad 108 sidewall surfaces and metal column 103 surface, therefore described conductive layer 116 is as intermediary, make the second pad 108, metal column 103 is electrically connected with metal redistribution layer 113, and solder-bump 115 is electrically connected with metal redistribution layer 113, therefore make to be electrically connected between solder-bump 115, signal processing chip 207 and image sensor chip 200 by metal redistribution layer 113.
Described solder-bump 115 is for being electrically connected signal processing chip 207, image sensor chip 200 and external circuit.
Described encapsulating structure also comprises: the substrate 105 being positioned at image sensor chip 200 first surface.In the present embodiment, in order to improve the adhesiveness between substrate 105 and image sensor chip 200 first surface, between described substrate 105 and image sensor chip 200, be also formed with adhesion layer 104; In other embodiments, substrate directly contacts with image sensor chip first surface.
Described substrate 105 provides a supporting role for image sensor chip 200 and signal processing chip 207, improve the mechanical strength of image sensor chip 200 and signal processing chip 207, prevent image sensor chip 200 or signal processing chip 207 from splintering problem occurring, improve the reliability of encapsulating structure.And substrate 105 described in external light therethrough, arrive the region at photo-sensitive cell 101 place, receive extraneous light to make image sensor chip 200.
Image sensor chip 200 and signal processing chip 207 are separated setting by the utility model embodiment, concrete, in image sensor chip 200 second signalization process chip 207, avoid arrangement and the interconnection problems considering in same chip, arrange image sensor chip 200 and signal processing chip 207, reduce design difficulty; Further, because the impact being subject to the other side's arrangement and area between image sensor chip 200 and signal processing chip 207 is little, therefore image sensor chip 200 and signal processing chip 207 all can obtain best performance, improve the encapsulation performance of encapsulating structure; Meanwhile, because image sensor chip 200 and signal processing chip 207 are not arranged on the same chip, hinge structure, the area of the image sensor chip 200 of the utility model embodiment is less, and therefore, the design cost of image sensor chip 200 reduces.
In another embodiment of the utility model, as shown in figure 13, described encapsulating structure comprises: the solder-bump 115 of filling full through hole, described solder-bump 115 contacts with conductive layer 116, and described solder-bump 115 top is higher than signal processing chip 207 fourth face.Described solder-bump 115 and conductive layer 116 directly contact to be electrically connected, conductive layer 116 is electrically connected with the second pad 108 and metal column 103, therefore makes to be electrically connected between signal processing chip 207, image sensor chip 200 and external circuit by described solder-bump 115.In order to prevent solder-bump 115 and signal processing chip 207 from unnecessary electrical connection occurring, between solder-bump 115 and through-hole side wall, be formed with insulating barrier 111, described insulating barrier 111 is also covered in signal processing chip 207 fourth face.
Another embodiment of the utility model also provides a kind of method for packing, Figure 14 to Figure 17 is the cross-sectional view of another embodiment encapsulation process of the utility model, it should be noted that, in the present embodiment, the parameter of structure same with the above-mentioned embodiment and effect etc. limit and repeat no more in the present embodiment, specifically please refer to above-described embodiment.
Please refer to Figure 14, provide image sensing wafer 300, described image sensing wafer 300 has some chip areas and the Cutting Road center line 310 between chip area.
Described image sensing wafer 300 has first surface and second of being oppositely arranged with described first surface, described image sensing wafer 300 first surface has some photo-sensitive cells 301 and the first pad 302 around described photo-sensitive cell 301, there is in image sensing wafer 300 metal column 303, metal column 303 one end is electrically connected with the first pad 302, and the other end relative with described one end flushes with image sensing wafer 300 second face.
In the present embodiment, form substrate 305 at image sensing wafer 300 first surface.Such as, if there is stronger adhesiveness between substrate 305 and image sensing wafer 300 first surface, when the material of substrate 305 is liquid glass, directly substrate 305 is covered image sensing wafer 300 first surface.As a specific embodiment, adopt spin coating process (spin-on-coating) at image sensing wafer 100 first surface coating liquid glass, form substrate 305 at image sensing wafer 300 first surface.
Please continue to refer to Figure 14, provide signal transacting wafer 307, described signal transacting wafer 307 have the 3rd and with described 3rd relative fourth face, and described signal transacting wafer 307 the 3rd mask has the second pad 308; By Direct Bonding technique, by image sensing wafer 300 second and signal transacting wafer 307 the 3rd fixed engagement, described second pad 308 directly contacts with metal column 303 surface, is electrically connected by the second pad 308 with metal column 303.
Please refer to Figure 15, etching processing is carried out to described signal transacting wafer 307 fourth face, form the through hole 309 running through described signal transacting wafer 307 fourth face, and described through hole 309 exposes the second pad 308 surface.
In the present embodiment, described through hole 309 bottom-exposed goes out the second pad 308 lower surface (face flushed with signal transacting wafer 307 the 3rd face in the second pad 308 is called upper surface, and the another side relative with described upper surface is called lower surface).In other embodiments, via bottoms exposes the second land side wall surface.
Please refer to Figure 16, form insulating barrier 311 at described signal transacting wafer 307 fourth face, through hole 309 (please refer to Figure 15) sidewall; Form metal redistribution layer 313 on described insulating barrier 311 surface, described metal redistribution layer 313 is also positioned at bottom through hole 309; Solder-bump 315 is formed on metal redistribution layer 313 surface of described signal transacting wafer 307 fourth face.
Because the second pad 308 is electrically connected with metal column 303, metal redistribution layer 313 is positioned at the second pad 308 surface, and so described metal redistribution layer 313 is all electrically connected with the second pad 308 and metal column 303.By the solder-bump 315 be electrically connected with metal redistribution layer 313, signal transacting wafer 307 and image sensing wafer 300 are electrically connected with external circuit.
In the present embodiment, in order to improve the reliability of encapsulating structure, before formation solder-bump 315, form welding resisting layer 314 on metal redistribution layer 313 surface and the second pad 308 surface; Form groove at the welding resisting layer 314 being positioned at signal transacting wafer 307 fourth face, described groove exposes part metals redistributing layer 313 surface; Form the solder-bump 315 of filling full described groove.
In other embodiments of the utility model, in order to reduce processing step, improving packaging efficiency, form the solder-bump of filling full described through hole, and described solder-bump top is higher than signal transacting wafer fourth face; And prevent future solder-bump and signal transacting wafer fourth face from unnecessary electrical connection occurring, between solder-bump and through-hole side wall, form insulating barrier, and described insulating barrier is also positioned at signal transacting wafer fourth face.
Please refer to Figure 17, cut described image sensing wafer 300 (please refer to Figure 16) and signal transacting wafer 307 (please refer to Figure 16) along described Cutting Road center line 310 (please refer to Figure 16), form some single encapsulating structures.
Described cutting technique with reference to the explanation of previous embodiment, can not repeat them here.Cutting image sensing wafer 300 forms image sensor chip 400, and cutoff signal process wafer 307 forms signal processing chip 407.
Because image sensing wafer 300 and signal transacting wafer 307 are separately formed, reduce the formation process difficulty of image sensing wafer 300 and signal transacting wafer 307, and avoid considering image sensor chip 400 and the arrangement interconnection problems of signal processing chip 407 in same wafer, image sensor chip 400 and signal processing chip 407 can not be subject to restriction each other, therefore the image sensor chip 400 in image sensing wafer 400 has optimum performance, same, signal processing chip 407 in signal transacting wafer 307 also has optimum performance, therefore the performance of the encapsulating structure of the present embodiment formation is high.
Accordingly, the present embodiment improves a kind of encapsulating structure, please refer to Figure 17, and described encapsulating structure comprises:
Image sensor chip 400, described image sensor chip 400 has first surface and relative with described first surface second, described image sensor chip 400 first surface has photo-sensitive cell 301 and the first pad 302 around described photo-sensitive cell 301, in described image sensor chip 400, there is metal column 303, and one end of described metal column 303 is electrically connected with the first pad 302, the other end relative with described one end flushes with image sensor chip 400 second face;
Signal processing chip 407, described signal processing chip 407 have the 3rd and with described 3rd relative fourth face, described signal processing chip 407 the 3rd mask has the second pad 308, and described signal processing chip 407 the 3rd and image sensor chip 400 second fixed engagement, described second pad 308 is electrically connected with metal column 303;
Run through the through hole of described signal processing chip 407 fourth face, and described via bottoms exposes the second pad 308 surface.
In the present embodiment, described signal processing chip 407 the 3rd directly contacts with image sensor chip 400 second, and described second pad 308 surface contacts with metal column 303 surface, and the mode that the second pad 308 and metal column 303 pass through directly to contact is to be electrically connected.
In the present embodiment, described through hole exposes the second pad 308 lower surface (face flushed with signal transacting wafer 307 the 3rd face in the second pad 308 is called upper surface, and the another side relative with described upper surface is called lower surface); In other embodiments, through hole exposes the second land side wall surface.
In order to make signal processing chip 407 and image sensor chip 400 be electrically connected with external circuit, described encapsulating structure also comprises: the insulating barrier 311 being positioned at described through-hole side wall and signal processing chip 407 fourth face; Be positioned at the metal redistribution layer 313 on described via bottoms and insulating barrier 311 surface; Be positioned at the solder-bump 315 on metal redistribution layer 313 surface of described signal processing chip 407 fourth face.
In order to improve the reliability of encapsulating structure, also comprise: the welding resisting layer 314 being positioned at described metal redistribution layer 313 surface; Be positioned at the groove of the welding resisting layer 314 of described signal processing chip 407 fourth face, and described bottom portion of groove exposes metal redistribution layer 313 surface, described solder-bump 315 fills full described groove.
In other embodiments of the utility model, be electrically connected with external circuit to make signal processing chip and image sensor chip, described encapsulating structure also comprises: the solder-bump of filling full described through hole, described solder-bump contacts with the second pad, and described solder-bump top is higher than signal processing chip fourth face.Prevent future solder-bump and signal processing chip from unnecessary electrical connection occurring, between solder-bump and through-hole side wall, be formed with insulating barrier, and described insulating barrier is also positioned at signal processing chip fourth face.
In the present embodiment, described encapsulating structure also comprises: the substrate 305 being positioned at image sensor chip 400 first surface, and described substrate 305 directly contacts with image sensor chip 400 first surface; In other embodiments, adhesive-layer can also be formed with between image sensor chip and substrate.
Image sensor chip 400 and signal processing chip 407 are separated setting by the utility model embodiment, concrete, in image sensor chip 400 second signalization process chip 407, avoid arrangement and the interconnection problems considering in same chip, arrange image sensor chip 400 and signal processing chip 407, reduce design difficulty; Further, because the impact being subject to the other side's arrangement and area between image sensor chip 400 and signal processing chip 407 is little, therefore image sensor chip 400 and signal processing chip 407 all can obtain best performance, improve the performance of encapsulating structure; Simultaneously, because image sensor chip 400 and signal processing chip 407 are not arranged on the same chip, hinge structure, the area of the image sensor chip 400 of the utility model embodiment is less, therefore, the design cost of image sensor chip 400 reduces, and makes the cost of encapsulating structure low.
Although the utility model discloses as above, the utility model is not defined in this.Any those skilled in the art, not departing from spirit and scope of the present utility model, all can make various changes or modifications, and therefore protection range of the present utility model should be as the criterion with claim limited range.
Claims (12)
1. an encapsulating structure, is characterized in that, comprising:
Image sensor chip, described image sensor chip has first surface and relative with described first surface second, described image sensor chip first surface has photo-sensitive cell and the first pad around described photo-sensitive cell, in described image sensor chip, there is metal column, and one end of described metal column is electrically connected with the first pad, the other end relative with described one end flushes with image sensor chip second face;
Signal processing chip, described signal processing chip have the 3rd and with described 3rd relative fourth face, described signal processing chip the 3rd mask has the second pad, and described signal processing chip the 3rd and image sensor chip second fixed engagement, described second pad is electrically connected with metal column;
Run through the through hole of described signal processing chip fourth face, and described through hole exposes the second bond pad surface.
2. encapsulating structure as claimed in claim 1, is characterized in that, be formed with adhesion layer between described image sensor chip and signal processing chip.
3. encapsulating structure as claimed in claim 2, it is characterized in that, also comprise: the opening being positioned at described second pad and adhesion layer, open bottom exposes metal column surface, and described opening and through hole run through mutually.
4. encapsulating structure as claimed in claim 3, is characterized in that, also comprise: the conductive layer of filling full described opening, and described conductive layer contacts with metal column and the second pad.
5. encapsulating structure as claimed in claim 4, is characterized in that, also comprise: the insulating barrier being positioned at through-hole side wall and signal processing chip fourth face; Be positioned at the metal redistribution layer of surface of insulating layer, and described metal redistribution layer is also positioned at conductive layer surface; Be positioned at the solder-bump on the metal redistribution layer surface of described signal processing chip fourth face.
6. encapsulating structure as claimed in claim 4, is characterized in that, also comprise: the solder-bump of filling full described through hole, described solder-bump contacts with conductive layer, and described solder-bump top is higher than signal processing chip fourth face.
7. encapsulating structure as claimed in claim 6, it is characterized in that, between described solder-bump and through-hole side wall, be formed with insulating barrier, described insulating barrier is also covered in signal processing chip fourth face.
8. encapsulating structure as claimed in claim 1, it is characterized in that, described signal processing chip the 3rd directly contacts with image sensor chip second, and described second bond pad surface contacts with metal column surface.
9. encapsulating structure as claimed in claim 8, is characterized in that, also comprise: the insulating barrier being positioned at described through-hole side wall and signal processing chip fourth face; Be positioned at the metal redistribution layer of described via bottoms and surface of insulating layer; Be positioned at the solder-bump on the metal redistribution layer surface of described signal processing chip fourth face.
10. encapsulating structure as claimed in claim 8, is characterized in that, fill the solder-bump of full described through hole, described solder-bump contacts with the second pad, and described solder-bump top is higher than signal processing chip fourth face.
11. encapsulating structures as claimed in claim 1, is characterized in that, also comprise: the substrate being positioned at image sensor chip first surface.
12. encapsulating structures as claimed in claim 11, is characterized in that, be also formed with adhesive-layer between described substrate and image sensor chip first surface.
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| CN201420347904.7U CN204029810U (en) | 2014-06-25 | 2014-06-25 | A kind of encapsulating structure |
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| CN201420347904.7U CN204029810U (en) | 2014-06-25 | 2014-06-25 | A kind of encapsulating structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104037146A (en) * | 2014-06-25 | 2014-09-10 | 苏州晶方半导体科技股份有限公司 | Packaging structure and packaging method |
| CN106449549A (en) * | 2016-11-08 | 2017-02-22 | 华天科技（昆山）电子有限公司 | Surface sensing wafer packaging structure and manufacturing method thereof |
-
2014
- 2014-06-25 CN CN201420347904.7U patent/CN204029810U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104037146A (en) * | 2014-06-25 | 2014-09-10 | 苏州晶方半导体科技股份有限公司 | Packaging structure and packaging method |
| CN104037146B (en) * | 2014-06-25 | 2016-09-28 | 苏州晶方半导体科技股份有限公司 | Encapsulating structure and method for packing |
| CN106449549A (en) * | 2016-11-08 | 2017-02-22 | 华天科技（昆山）电子有限公司 | Surface sensing wafer packaging structure and manufacturing method thereof |
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