CN112310135B - Sensor structure and method for forming sensor structure - Google Patents

Sensor structure and method for forming sensor structure Download PDF

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Publication number
CN112310135B
CN112310135B CN202011119399.7A CN202011119399A CN112310135B CN 112310135 B CN112310135 B CN 112310135B CN 202011119399 A CN202011119399 A CN 202011119399A CN 112310135 B CN112310135 B CN 112310135B
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chip
silicon
sensor
structures
electrically connected
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CN112310135A (en
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罗文哲
王林
黄金德
胡万景
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Rockchip Electronics Co Ltd
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Rockchip Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/1469—Assemblies, i.e. hybrid integration

Abstract

A sensor structure and a method for forming the sensor structure, the structure includes: the chip structures are arranged in a two-dimensional array; the chip structure comprises a first chip and a second chip which are bonded with each other, wherein the first chip is internally provided with a sensor array, and the second chip is internally provided with a circuit structure electrically connected with the sensor array. The sensor structure can meet the sensor requirement of any area.

Description

Sensor structure and method for forming sensor structure
Technical Field
The present disclosure relates to sensors, and particularly to a sensor structure and a method for forming the sensor structure.
Background
An image sensor is a semiconductor device that converts an optical signal into an electrical signal.
Image sensors are classified into CMOS (complementary metal oxide semiconductor, complementary Metal Oxide Semiconductor, abbreviated as CMOS) image sensors and CCD (charge coupled device, charge coupled device, abbreviated as CCD) image sensors. The CMOS image sensor has the advantages of simple process, easy integration of other devices, small volume, light weight, low power consumption, low cost and the like. Therefore, with the development of image sensing technology, CMOS image sensors are increasingly being used in various electronic products instead of CCD image sensors. Currently, CMOS image sensors have been widely used in still digital cameras, digital video cameras, medical imaging devices, vehicle imaging devices, and the like.
However, with the development of society, the market has greatly increased for large area array image sensors. However, the large area array image sensor chip is difficult to manufacture due to the limitations of process, yield and the like.
Disclosure of Invention
The invention solves the technical problem of providing a sensor structure and a forming method of the sensor structure so as to realize a chip structure with an ultra-large area.
In order to solve the above technical problems, the present invention provides a sensor structure, including: the chip structures are arranged in a two-dimensional array; the chip structure comprises a first chip and a second chip which are bonded with each other, wherein the first chip is internally provided with a sensor array, and the second chip is internally provided with a circuit structure electrically connected with the sensor array.
Optionally, the method further comprises: a substrate; the chip structures are located on the substrate, and the chip structures are connected with the substrate.
Optionally, the substrate comprises an integrated circuit board.
Optionally, the method further comprises: and the bonding layers are positioned between the chip structures and the substrate.
Optionally, the material of the adhesive layer includes an insulating material; the insulating material comprises a thermoset glue.
Optionally, the sensor array comprises an image sensor array.
Optionally, the first chip includes a first surface and a second surface opposite to each other, the sensor array is located on the first surface, the sensor array includes a plurality of sensor units, and any one of the sensor units is electrically connected with a corresponding circuit structure; the second chip comprises a third surface and a fourth surface which are opposite, the third surface of the second chip is provided with a circuit layer, and the circuit structure is positioned in the circuit layer; the second face of the first chip is bonded to the third face of the second chip.
Optionally, the chip structure further includes: a plurality of first through silicon via structures extending from the second surface of the first chip to the first surface, any one of the first through silicon via structures being electrically connected to one of the sensor units, and the plurality of first through silicon via structures being electrically connected to the circuit structure; and the second through silicon via structures extend from the fourth surface of the second chip to the third surface, and are electrically connected with the circuit structures.
Optionally, the first through silicon via structure includes a first conductive layer and a first insulating layer located between the first conductive layer and the first chip; the second through silicon via structure includes a second conductive layer and a second insulating layer between the second conductive layer and the second chip.
Optionally, the material of the first conductive layer includes a metal including one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum nitride, ruthenium nitride, and aluminum; the material of the first conductive layer includes a metal including one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum nitride, ruthenium nitride, and aluminum.
Optionally, the material of the first insulating layer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide, and silicon oxycarbide; the material of the second insulating layer comprises one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide and silicon oxycarbonitride.
Optionally, the chip structure further includes: a rewiring structure on a fourth side of the second chip; the rewiring structure comprises a passivation layer and a conductive structure located in the passivation layer, wherein the conductive structure is electrically connected with the second through silicon via structure.
Optionally, the chip structure further includes: and a plurality of metal pins positioned on the rewiring structure, wherein the metal pins are electrically connected with the conductive structure.
Optionally, the metal pins include solder balls or copper pillars.
Optionally, the sensor array has a first interval from the edge of the first chip, a second interval is arranged between adjacent chip structures, and the sensor unit has a third width; the first spacing is smaller than the third width, and the second spacing plus 2 times the first spacing is 1-3 times the third width.
Optionally, the first interval ranges from 10 micrometers to 50 micrometers; the second interval ranges from 10 micrometers to 100 micrometers; the third width ranges from 10 microns to 100 microns.
Correspondingly, the technical scheme of the invention also provides a method for forming the sensor structure, which comprises the following steps: providing a plurality of chip structures, and arranging the chip structures in a two-dimensional array; the chip structure comprises a first chip and a second chip which are bonded with each other, wherein the first chip is internally provided with a sensor array, and the second chip is internally provided with a circuit structure electrically connected with the sensor array.
Optionally, the method further comprises: providing a substrate; and arranging a plurality of chip structures on the substrate in a two-dimensional array, wherein the chip structures are connected with the substrate.
Optionally, the substrate comprises an integrated circuit board.
Optionally, the method further comprises: an adhesive layer is formed between a plurality of the chip structures and the substrate.
Optionally, the material of the adhesive layer includes an insulating material; the insulating material comprises a thermoset glue.
Optionally, the sensor array comprises an image sensor array.
Optionally, the first chip includes a first surface and a second surface opposite to each other, the sensor array is located on the first surface, the sensor array includes a plurality of sensor units, and any one of the sensor units is electrically connected with a corresponding circuit structure; the second chip comprises a third surface and a fourth surface which are opposite, the third surface of the second chip is provided with a circuit layer, and the circuit structure is positioned in the circuit layer; the second face of the first chip is bonded to the third face of the second chip.
Optionally, the chip structure further includes: a plurality of first through silicon via structures extending from the second surface of the first chip to the first surface, any one of the first through silicon via structures being electrically connected to one of the sensor units, and the plurality of first through silicon via structures being electrically connected to the circuit structure; and the second through silicon via structures extend from the fourth surface of the second chip to the third surface, and are electrically connected with the circuit structures.
Optionally, the first through silicon via structure includes a first conductive layer and a first insulating layer located between the first conductive layer and the first chip; the second through silicon via structure includes a second conductive layer and a second insulating layer between the second conductive layer and the second chip.
Optionally, the material of the first conductive layer includes a metal including one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum nitride, ruthenium nitride, and aluminum; the material of the first conductive layer includes a metal including one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum nitride, ruthenium nitride, and aluminum.
Optionally, the material of the first insulating layer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide, and silicon oxycarbide; the material of the second insulating layer comprises one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide and silicon oxycarbonitride.
Optionally, the chip structure further includes: a rewiring structure on a fourth side of the second chip; the rewiring structure comprises a passivation layer and a conductive structure located in the passivation layer, wherein the conductive structure is electrically connected with the second through silicon via structure.
Optionally, the chip structure further includes: and a plurality of metal pins positioned on the rewiring structure, wherein the metal pins are electrically connected with the conductive structure.
Optionally, the metal pins include solder balls, copper pillars, gold pins, or pads.
Optionally, the method for forming the chip structure includes: providing a first wafer, wherein the first wafer comprises a plurality of chip areas and a first cutting area, and the first wafer comprises a first surface and a second surface which are opposite; forming a sensor array in a first surface chip area of a first wafer; forming a plurality of first through-silicon-via structures in a first wafer, wherein the first through-silicon-via structures are exposed from a second surface of the first wafer; providing a second wafer comprising a plurality of logic regions and a second dicing region, the second wafer comprising opposed third and fourth faces; forming a circuit layer in a third surface logic region of the second wafer, wherein the circuit layer is internally provided with a circuit structure; forming a plurality of second through-silicon-via structures in the second wafer, wherein the second through-silicon-via structures extend from the fourth surface to the third surface of the second wafer, and the second through-silicon-via structures are electrically connected with the circuit structure; bonding the second surface of the first wafer with the third surface of the second wafer, wherein a plurality of chip areas correspond to a plurality of logic areas one by one, a first cutting area corresponds to the second cutting area, and a plurality of first through silicon via structures are electrically connected with a plurality of circuit structures to form an initial chip structure; and cutting the initial chip structure along the first cutting area and the second cutting area to form a plurality of chip structures.
Optionally, the sensor array has a first interval from the edge of the first chip, a second interval is arranged between adjacent chip structures, and the sensor unit has a third width; the first spacing is smaller than the third width, and the second spacing plus 2 times the first spacing is 1-3 times the third width.
Optionally, the first interval ranges from 10 micrometers to 50 micrometers; the second interval ranges from 10 micrometers to 100 micrometers; the third width ranges from 10 microns to 100 microns.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
the sensor structure in the technical scheme of the invention comprises a first chip and a second chip which are bonded with each other, wherein the first chip is internally provided with a sensor array, and the second chip is internally provided with a circuit structure electrically connected with the sensor array. Therefore, the chip structure can realize two-dimensional array arrangement with four edges capable of being spliced, and meanwhile, the chip structure in two-dimensional array arrangement is not discontinuous in imaging or uneven in signal receiving, so that the requirement of a sensor with any area can be met.
Further, the first distance is generally smaller than the third width, and the second distance is added by 2 times the first distance to be 1-3 times the third width, so that the distances between adjacent sensor units in a plurality of chip structures arranged in a two-dimensional array are relatively uniform, the arrangement distances of the sensor units in a plurality of chip structures arranged in the two-dimensional array are uniform, and continuity of sensor imaging is facilitated.
According to the method for forming the sensor structure in the technical scheme, the chip structure comprises a first chip and a second chip which are bonded with each other, a sensor array is arranged in the first chip, and a circuit structure electrically connected with the sensor array is arranged in the second chip. Therefore, the chip structure can realize two-dimensional array arrangement with four edges capable of being spliced, and meanwhile, the chip structure in two-dimensional array arrangement is not discontinuous in imaging or uneven in signal receiving, so that the requirement of a sensor with any area can be met.
Drawings
FIGS. 1 and 2 are schematic structural views of a sensor structure in one embodiment;
fig. 3 to 9 are schematic structural views of a sensor structure forming process in an embodiment of the present invention.
Detailed Description
As described in the background, the existing large area array chip is difficult to manufacture. Specifically, the physical layout of a conventional 2d cmos image sensor chip is: the middle of the chip is a pixel array of the image sensor, and processing circuits, reading circuits, SRAM (static random Access memory) and the like are arranged around the chip, and surround the pixel array, and occupy a large part of chip area; however, under the influence of photolithography, an image sensor chip with a large area array cannot be formed at a time.
In order to solve the problem of the area array limitation of the CMOS image sensor, a method of splicing the chips is proposed to meet the requirement of a large area array image sensor.
The following two common splicing methods: (a) 1D splicing and (b) 1.5D splicing to meet the requirements of a large area array image sensor.
Fig. 1 and 2 are schematic structural diagrams of an image sensor in an embodiment.
Referring to fig. 1, the method includes: a plurality of chips arranged along a first direction X, the chips comprising: a pixel region 100; logic circuit regions 101 located at both sides of the pixel region 100 in the second direction Y.
In the image sensor, the chips can only be spliced in the first direction X, but cannot be spliced in the second direction Y, and the area of the finally obtained spliced chip is limited in the second direction Y, so that the requirement of any large-area array image sensor cannot be met.
Referring to fig. 2, the method includes: the chips are distributed along the first direction X, and in the second direction Y, the two chips are adjacent; the chip comprises: a pixel region 200; the logic circuit region 201 located at one side of the pixel region 200 along the second direction Y in which the pixel regions 200 of adjacent chips are adjacent.
In the image sensor, the chips can be spliced in any number in the first direction X, only two chips can be spliced in the second direction Y, the area of the finally obtained spliced chip is limited in the second direction Y, and the requirement of any large-area array image sensor cannot be met.
In order to solve the above problems, the present invention provides a sensor structure and a method for forming the sensor structure, where the formed chip structure includes a first chip and a second chip bonded to each other, the first chip has a sensor array therein, and the second chip has a circuit structure electrically connected to the sensor array therein. Therefore, the chip structure can realize two-dimensional array arrangement with four edges capable of being spliced, and meanwhile, the chip structure in two-dimensional array arrangement is not discontinuous in imaging or uneven in signal receiving, so that the requirement of a sensor with any area can be met.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 9 are schematic structural views of a sensor structure forming process in an embodiment of the present invention.
Providing a plurality of chip structures, and arranging the plurality of chip structures in a two-dimensional array.
The chip structure comprises a first chip and a second chip which are bonded with each other, wherein the first chip is internally provided with a sensor array, and the second chip is internally provided with a circuit structure electrically connected with the sensor array. The process of forming the chip structure is shown in fig. 3 to 8.
Referring to fig. 3, a first wafer 300 is provided, the first wafer 300 includes a plurality of chip regions 301 and a first dicing region 302, and the first wafer 300 includes a first surface and a second surface opposite to each other.
The chip area 301 is an area where a sensor array is formed; the first dicing area 302 is a dicing channel for subsequently dicing the first wafer 300.
In this embodiment, the material of the first wafer 300 is silicon.
In other embodiments, the material of the first wafer comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Wherein the iii-v element comprising multi-component semiconductor material comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.
With continued reference to fig. 3, a sensor array is formed within a first die area 301 of a first wafer 300, the sensor array including a plurality of sensor units 303.
The sensor array includes an image sensor array.
In this embodiment, the sensor array comprises an image sensor array; the sensor unit 303 includes a pixel unit.
Referring to fig. 4, a plurality of first through-silicon via structures 304 are formed in the first wafer 300, and the first through-silicon via structures 304 are exposed on the second surface of the first wafer 300.
The first through silicon via structures 304 extend from the second surface of the first wafer 300 towards the first surface, and any one of the first through silicon via structures 304 is electrically connected to one of the sensor units 303.
The first through silicon via structure 304 is used to electrically connect the sensor array with a circuit structure subsequently formed on a second wafer to control the sensor array.
The first through silicon via structure 304 includes a first conductive layer (not shown) and a first insulating layer (not shown) between the first conductive layer and the first wafer 300.
The material of the first conductive layer includes a metal including one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum nitride, ruthenium nitride, and aluminum.
The material of the first insulating layer comprises one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide and silicon oxycarbonitride.
Referring to fig. 5, a second wafer 400 is provided, the second wafer 400 includes a plurality of logic areas 401 and a second dicing area 402, and the second wafer 400 includes a third surface and a fourth surface opposite to each other.
The logic region 401 is a region where a circuit structure is formed; the second dicing area 402 is a dicing channel for subsequently dicing the second wafer 400.
In this embodiment, the material of the second wafer 400 is silicon.
In other embodiments, the material of the second wafer comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Wherein the iii-v element comprising multi-component semiconductor material comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.
With continued reference to fig. 5, a circuit layer having a circuit structure 403 is formed in the third logic region 401 of the second wafer 400.
The circuit layer further comprises a dielectric layer (not shown), within which the circuit structure 403 is located.
The circuit structure 403 is electrically connected to the sensor array through the first through silicon via structure 304, so as to control the working state of the sensor array.
Referring to fig. 6, a plurality of second through-silicon via structures 404 are formed in the second wafer 400, the second through-silicon via structures 404 extend from the fourth surface of the second wafer 400 to the third surface, and the second through-silicon via structures 404 are electrically connected to the circuit structures 403.
The second through silicon via structure 404 is used to external the circuit structure 403 to a power source or other circuit.
The second through silicon via structure 404 includes a second conductive layer (not shown) and a second insulating layer (not shown) between the second conductive layer and the second chip.
The material of the second conductive layer comprises a metal comprising one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum nitride, ruthenium nitride, and aluminum. The material of the second insulating layer comprises one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide and silicon oxycarbonitride.
With continued reference to fig. 6, the method further includes: forming a rewiring structure 405 on a fourth surface of the second wafer 400; the rewiring structure 405 includes a passivation layer (not shown) and a conductive structure (not shown) located within the passivation layer, the conductive structure being electrically connected with the second through-silicon via structure 404; a number of metal pins 406 are formed on the rewiring structure 405, the metal pins 406 being electrically connected with the conductive structure.
The metal pins comprise solder balls, copper columns, gold pins or bonding pads.
Referring to fig. 7 and 8, fig. 8 is a perspective view of fig. 7, fig. 7 is a schematic view of a cross-sectional structure of fig. 8 along a section line AA1, bonding a second surface of the first wafer 300 to a third surface of the second wafer 400, wherein a plurality of the chip regions 301 and a plurality of the logic regions 401 are in one-to-one correspondence, the first dicing region 302 corresponds to the second dicing region 402, and a plurality of the first through silicon via structures 304 are electrically connected to a plurality of the circuit structures 403 to form an initial chip structure (not shown); the initial chip structure is diced along the first dicing area 302 and the second dicing area 402 to form a plurality of chip structures.
The first wafer 300 is cut to form a first chip 310; the second wafer 400 is diced to form second chips 410.
In this embodiment, the first chip 310 and the second chip 410 have the same area; the first chip 310 and the second chip 410 may have any area.
The chip structure includes a first chip 310 and a second chip 410 bonded to each other, the first chip 310 having a sensor array therein, and the second chip 410 having a circuit structure 403 electrically connected to the sensor array therein.
The first chip 310 includes a first surface and a second surface opposite to each other, the sensor array is located on the first surface, the sensor array includes a plurality of sensor units, and any one of the sensor units is electrically connected to a corresponding circuit structure 403; the second chip 410 includes a third surface and a fourth surface opposite to each other, the third surface of the second chip 410 has a circuit layer thereon, and the circuit structure 403 is located in the circuit layer; the second side of the first chip 310 is bonded to the third side of the second chip 410.
The chip structure further comprises: a plurality of first through silicon via structures 304, the first through silicon via structures 304 extending from the second surface of the first chip 310 to the first surface, any one of the first through silicon via structures 304 being electrically connected to one of the sensor units, and the plurality of first through silicon via structures 304 being electrically connected to the circuit structure 403; a plurality of second through silicon via structures 404, the second through silicon via structures 404 extending from the fourth surface of the second chip 410 to the third surface, the second through silicon via structures 404 being electrically connected to the circuit structures 403.
In this embodiment, any one of the sensor units is electrically connected to the corresponding circuit structure 403 through the first through-silicon via structure 304.
The chip structure further comprises: a rewiring structure 405 on a fourth side of the second chip 410; the rewiring structure 405 includes a passivation layer and a conductive structure within the passivation layer that is electrically connected with the second through-silicon via structure 404.
The chip structure further comprises: a number of metal pins 406 located on the rewiring structure, the metal pins 406 being electrically connected with the conductive structure.
The metal pins 406 include solder balls or copper pillars.
The metal pins 406 are used to connect the chip structure to an external power source or circuit.
In this embodiment, the sensor array has a first spacing L1 (not labeled) from the edge of the first chip 310, and the sensor unit 303 has a third width L2, where the first spacing L1 is smaller than the third width L2.
The range of the first spacing L1 is 10 micrometers to 50 micrometers; the third width L2 ranges from 10 micrometers to 100 micrometers.
To this end, a chip structure is formed, which includes a first chip 310 and a second chip 410 bonded to each other, where the first chip 310 has a sensor array therein, and the second chip 410 has a circuit structure 403 electrically connected to the sensor array therein. Therefore, the chip structure can realize two-dimensional array arrangement with four edges capable of being spliced, and meanwhile, the chip structure in two-dimensional array arrangement is not discontinuous in imaging or uneven in signal receiving, so that the requirement of a sensor with any area can be met.
Referring to fig. 9, further includes: providing a substrate 500; the chip structures are arranged in a two-dimensional array on the substrate 500, and the chip structures are connected with the substrate 500.
In this embodiment, the substrate 500 comprises an integrated circuit board. The chip structure is electrically connected to the integrated circuit board through metal pins 406.
With continued reference to fig. 9, the method further includes: an adhesive layer 501 is formed between a number of the chip structures and the substrate 500.
The adhesive layer 501 is used to fix the chip structure to the substrate 500.
The material of the adhesive layer 501 includes an insulating material; the insulating material comprises a thermoset glue.
In this embodiment, the adjacent chip structures have a second spacing L3 therebetween.
The second distance L3 ranges from 10 micrometers to 100 micrometers.
The first distance L1 is smaller than the third width L2, and the second distance L3 is increased by 2 times, the first distance L1 is 1-3 times the third width L2, so that the distances between adjacent sensor units 303 in a plurality of chip structures arranged in a two-dimensional array are relatively uniform, the arrangement distances between the sensor units 303 in the plurality of chip structures arranged in the two-dimensional array are uniform, and continuity of sensor imaging is facilitated.
Accordingly, an embodiment of the present invention further provides a sensor structure, please continue to refer to fig. 9, including:
the chip structures are arranged in a two-dimensional array;
the chip structure includes a first chip 310 and a second chip 410 bonded to each other, the first chip 310 having a sensor array therein, and the second chip 410 having a circuit structure 403 electrically connected to the sensor array therein.
In this embodiment, further comprising: a substrate 500; a plurality of the chip structures are located on the substrate 500, and the plurality of the chip structures are connected with the substrate 500.
In this embodiment, the substrate 500 comprises an integrated circuit board.
In this embodiment, further comprising: an adhesive layer 501 between a number of the chip structures and the substrate 500.
In this embodiment, the material of the adhesive layer 501 includes an insulating material; the insulating material comprises a thermoset glue.
In this embodiment, the sensor array comprises an image sensor array.
In this embodiment, the first chip 310 includes a first surface and a second surface opposite to each other, the sensor array is located on the first surface, and the sensor array includes a plurality of sensor units, and any one of the sensor units is electrically connected to the corresponding circuit structure 403; the second chip 410 includes a third surface and a fourth surface opposite to each other, the third surface of the second chip 410 has a circuit layer thereon, and the circuit structure 403 is located in the circuit layer; the second side of the first chip 310 is bonded to the third side of the second chip 410.
In this embodiment, the chip structure further includes: a plurality of first through silicon via structures 304, the first through silicon via structures 304 extending from the second surface of the first chip 310 to the first surface, any one of the first through silicon via structures 304 being electrically connected to one of the sensor units, and the plurality of first through silicon via structures 304 being electrically connected to the circuit structure 403; a plurality of second through silicon via structures 404, the second through silicon via structures 404 extending from the fourth surface of the second chip 410 to the third surface, the second through silicon via structures 404 being electrically connected to the circuit structures 403.
In this embodiment, the first through-silicon via structure 304 includes a first conductive layer (not shown) and a first insulating layer (not shown) between the first conductive layer and the first chip; the second through silicon via structure 404 includes a second conductive layer (not shown) and a second insulating layer (not shown) between the second conductive layer and the second chip.
In this embodiment, the material of the first conductive layer includes a metal including one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum nitride, ruthenium nitride, and aluminum; the material of the first conductive layer includes a metal including one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum nitride, ruthenium nitride, and aluminum.
In this embodiment, the material of the first insulating layer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide, and silicon oxycarbide; the material of the second insulating layer comprises one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide and silicon oxycarbonitride.
In this embodiment, the chip structure further includes: a rewiring structure 405 on a fourth side of the second chip 410; the rewiring structure includes a passivation layer (not shown) and a conductive structure (not shown) located within the passivation layer, the conductive structure being electrically connected with the second through-silicon via structure 404.
In this embodiment, the chip structure further includes: a number of metal pins 406 located on the rewiring structure 405, the metal pins being electrically connected with the conductive structure.
In this embodiment, the metal pins 406 include solder balls, copper pillars, gold pins, or pads.
In this embodiment, the sensor array has a first pitch from the edge of the first chip 310, a second pitch between adjacent chip structures, and a third width between adjacent sensor units; the first pitch is less than the third width, and the second pitch is less than the third width.
In this embodiment, the first distance L1 is smaller than the third width L2, and the first distance L1, which is 2 times the second distance L3, is 1 to 3 times the third width L2.
The chip structure includes a first chip 310 and a second chip 410 bonded to each other, the first chip 310 having a sensor array therein, and the second chip 410 having a circuit structure 403 electrically connected to the sensor array therein. Therefore, the chip structure can realize two-dimensional array arrangement with four edges capable of being spliced, and meanwhile, the chip structure in two-dimensional array arrangement is not discontinuous in imaging or uneven in signal receiving, so that the requirement of a sensor with any area can be met.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (29)

1. A sensor structure, comprising:
the chip structures are arranged in a two-dimensional array;
the chip structure comprises a first chip and a second chip which are bonded with each other, wherein a sensor array is arranged in the first chip, the first chip comprises a first surface and a second surface which are opposite, the sensor array is positioned on the first surface, the sensor array comprises a plurality of sensor units, and any one of the sensor units is electrically connected with a corresponding circuit structure; the second chip is internally provided with a circuit structure electrically connected with the sensor array, the second chip comprises a third surface and a fourth surface which are opposite, the third surface of the second chip is provided with a circuit layer, and the circuit structure is positioned in the circuit layer; the second surface of the first chip is bonded with the third surface of the second chip;
the sensor array has a first interval from the edge of the first chip, a second interval is arranged between adjacent chip structures, and the sensor unit has a third width; the first spacing is smaller than the third width, and the second spacing plus 2 times the first spacing is 1-3 times the third width.
2. The sensor structure of claim 1, further comprising: a substrate; the chip structures are located on the substrate, and the chip structures are connected with the substrate.
3. The sensor structure of claim 2, wherein the substrate comprises an integrated circuit board.
4. The sensor structure of claim 2, further comprising: and the bonding layers are positioned between the chip structures and the substrate.
5. The sensor structure of claim 4, wherein the material of the adhesive layer comprises an insulating material; the insulating material comprises a thermoset glue.
6. The sensor structure of claim 1, wherein the sensor array comprises an image sensor array.
7. The sensor structure of claim 1, wherein the chip structure further comprises: a plurality of first through silicon via structures extending from the second surface of the first chip to the first surface, any one of the first through silicon via structures being electrically connected to one of the sensor units, and the plurality of first through silicon via structures being electrically connected to the circuit structure; and the second through silicon via structures extend from the fourth surface of the second chip to the third surface, and are electrically connected with the circuit structures.
8. The sensor structure of claim 7, wherein the first through silicon via structure comprises a first conductive layer and a first insulating layer between the first conductive layer and the first chip; the second through silicon via structure includes a second conductive layer and a second insulating layer between the second conductive layer and the second chip.
9. The sensor structure of claim 8, wherein the material of the first conductive layer comprises a metal comprising a combination of one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum nitride, ruthenium nitride, and aluminum; the material of the first conductive layer includes a metal including one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum nitride, ruthenium nitride, and aluminum.
10. The sensor structure of claim 8, wherein the material of the first insulating layer comprises one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide, and silicon oxycarbonitride; the material of the second insulating layer comprises one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide and silicon oxycarbonitride.
11. The sensor structure of claim 1, wherein the chip structure further comprises: a rewiring structure on a fourth side of the second chip; the rewiring structure comprises a passivation layer and a conductive structure located in the passivation layer, wherein the conductive structure is electrically connected with the second through silicon via structure.
12. The sensor structure of claim 11, wherein the chip structure further comprises: and a plurality of metal pins positioned on the rewiring structure, wherein the metal pins are electrically connected with the conductive structure.
13. The sensor structure of claim 12, wherein the metal pins comprise solder balls, copper pillars, gold pins, or pads.
14. The sensor structure of claim 1, wherein the first pitch ranges from 10 microns to 50 microns; the second interval ranges from 10 micrometers to 100 micrometers; the third width ranges from 10 microns to 100 microns.
15. A method of forming a sensor structure, comprising:
providing a plurality of chip structures, and arranging the chip structures in a two-dimensional array;
the chip structure comprises a first chip and a second chip which are bonded with each other, wherein a sensor array is arranged in the first chip, the first chip comprises a first surface and a second surface which are opposite, the sensor array is positioned on the first surface, the sensor array comprises a plurality of sensor units, and any one of the sensor units is electrically connected with a corresponding circuit structure; the second chip is internally provided with a circuit structure electrically connected with the sensor array, the second chip comprises a third surface and a fourth surface which are opposite, the third surface of the second chip is provided with a circuit layer, and the circuit structure is positioned in the circuit layer; the second surface of the first chip is bonded with the third surface of the second chip;
the sensor array has a first interval from the edge of the first chip, a second interval is arranged between adjacent chip structures, and the sensor unit has a third width; the first spacing is smaller than the third width, and the second spacing plus 2 times the first spacing is 1-3 times the third width.
16. The method of forming a sensor structure of claim 15, further comprising: providing a substrate; and arranging a plurality of chip structures on the substrate in a two-dimensional array, wherein the chip structures are connected with the substrate.
17. The method of forming a sensor structure of claim 16, wherein the substrate comprises an integrated circuit board.
18. The method of forming a sensor structure of claim 15, further comprising: an adhesive layer is formed between a plurality of the chip structures and the substrate.
19. The method of forming a sensor structure of claim 18, wherein the material of the bonding layer comprises an insulating material; the insulating material comprises a thermoset glue.
20. The method of forming a sensor structure of claim 15, wherein the sensor array comprises an image sensor array.
21. The method of forming a sensor structure of claim 15, wherein the chip structure further comprises: a plurality of first through silicon via structures extending from the second surface of the first chip to the first surface, any one of the first through silicon via structures being electrically connected to one of the sensor units, and the plurality of first through silicon via structures being electrically connected to the circuit structure; and the second through silicon via structures extend from the fourth surface of the second chip to the third surface, and are electrically connected with the circuit structures.
22. The method of forming a sensor structure of claim 21, wherein the first through silicon via structure comprises a first conductive layer and a first insulating layer between the first conductive layer and the first chip; the second through silicon via structure includes a second conductive layer and a second insulating layer between the second conductive layer and the second chip.
23. The method of forming a sensor structure of claim 22, wherein the material of the first conductive layer comprises a metal comprising a combination of one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum nitride, ruthenium nitride, and aluminum; the material of the first conductive layer includes a metal including one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum nitride, ruthenium nitride, and aluminum.
24. The method of forming a sensor structure of claim 22, wherein the material of the first insulating layer comprises one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide, and silicon oxycarbonitride; the material of the second insulating layer comprises one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide and silicon oxycarbonitride.
25. The method of forming a sensor structure of claim 21, wherein the chip structure further comprises: a rewiring structure on a fourth side of the second chip; the rewiring structure comprises a passivation layer and a conductive structure located in the passivation layer, wherein the conductive structure is electrically connected with the second through silicon via structure.
26. The method of forming a sensor structure of claim 25, wherein the chip structure further comprises: and a plurality of metal pins positioned on the rewiring structure, wherein the metal pins are electrically connected with the conductive structure.
27. The method of claim 26, wherein the metal pins comprise solder balls or copper pillars.
28. The method of forming a sensor structure of claim 15, wherein the method of forming a chip structure comprises: providing a first wafer, wherein the first wafer comprises a plurality of chip areas and a first cutting area, and the first wafer comprises a first surface and a second surface which are opposite; forming a sensor array in a first surface chip area of a first wafer; forming a plurality of first through-silicon-via structures in a first wafer, wherein the first through-silicon-via structures are exposed from a second surface of the first wafer; providing a second wafer comprising a plurality of logic regions and a second dicing region, the second wafer comprising opposed third and fourth faces; forming a circuit layer in a third surface logic region of the second wafer, wherein the circuit layer is internally provided with a circuit structure; forming a plurality of second through-silicon-via structures in the second wafer, wherein the second through-silicon-via structures extend from the fourth surface to the third surface of the second wafer, and the second through-silicon-via structures are electrically connected with the circuit structure; bonding the second surface of the first wafer with the third surface of the second wafer, wherein a plurality of chip areas correspond to a plurality of logic areas one by one, a first cutting area corresponds to the second cutting area, and a plurality of first through silicon via structures are electrically connected with a plurality of circuit structures to form an initial chip structure; and cutting the initial chip structure along the first cutting area and the second cutting area to form a plurality of chip structures.
29. The method of forming a sensor structure of claim 15, wherein the first pitch ranges from 10 microns to 50 microns; the second interval ranges from 10 micrometers to 100 micrometers; the third width ranges from 10 microns to 100 microns.
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