CN106298718A - Integrated circuit, front illuminated sensor, backside-illuminated sensor and three dimensional integrated circuits - Google Patents
Integrated circuit, front illuminated sensor, backside-illuminated sensor and three dimensional integrated circuits Download PDFInfo
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- CN106298718A CN106298718A CN201610474165.1A CN201610474165A CN106298718A CN 106298718 A CN106298718 A CN 106298718A CN 201610474165 A CN201610474165 A CN 201610474165A CN 106298718 A CN106298718 A CN 106298718A
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 265
- 239000002184 metal Substances 0.000 claims abstract description 265
- 239000000758 substrate Substances 0.000 claims abstract description 207
- 230000004888 barrier function Effects 0.000 claims abstract description 35
- 238000001465 metallisation Methods 0.000 claims description 24
- 238000003466 welding Methods 0.000 claims description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 8
- 239000010931 gold Substances 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 8
- 239000010410 layer Substances 0.000 description 197
- 238000005530 etching Methods 0.000 description 33
- 238000000034 method Methods 0.000 description 28
- 239000011248 coating agent Substances 0.000 description 18
- 238000000576 coating method Methods 0.000 description 18
- 238000004519 manufacturing process Methods 0.000 description 18
- 230000006872 improvement Effects 0.000 description 13
- 229910052782 aluminium Inorganic materials 0.000 description 12
- 229910052802 copper Inorganic materials 0.000 description 11
- 239000010949 copper Substances 0.000 description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 10
- 238000005286 illumination Methods 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 239000003989 dielectric material Substances 0.000 description 8
- 238000000151 deposition Methods 0.000 description 7
- 238000003384 imaging method Methods 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 230000008859 change Effects 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 230000003287 optical effect Effects 0.000 description 6
- 238000002161 passivation Methods 0.000 description 6
- -1 aluminum bronze compound Chemical class 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- 229910000906 Bronze Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 239000000654 additive Substances 0.000 description 4
- 230000000996 additive effect Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000010974 bronze Substances 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- JRBRVDCKNXZZGH-UHFFFAOYSA-N alumane;copper Chemical compound [AlH3].[Cu] JRBRVDCKNXZZGH-UHFFFAOYSA-N 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000005622 photoelectricity Effects 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 208000006992 Color Vision Defects Diseases 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 201000000761 achromatopsia Diseases 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 201000007254 color blindness Diseases 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012634 optical imaging Methods 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1464—Back illuminated imager structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14634—Assemblies, i.e. Hybrid structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/1469—Assemblies, i.e. hybrid integration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
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- Engineering & Computer Science (AREA)
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- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Some embodiments of the present invention relate to a kind of three-dimensional (3D) integrated circuit (IC).3DIC includes the first substrate, and this first substrate includes the photoelectric detector being configured to receive light in a first direction from light source.Interconnection structure is arranged on above the first substrate and includes multiple metal levels and the insulating barrier overlie one another in an alternating fashion.In multiple metal levels one is nearest from light source, and another in multiple metal level is farthest from light source.In bond pad groove opening from the surface of the 3DIC nearest from light source extends to interconnection structure and terminate in away from bond pad.Bond pad and the spaced apart from surfaces of 3DIC and with directly contacting from farthest one of light source in multiple metal levels.Embodiments of the invention additionally provide integrated circuit, front illuminated sensor and backside-illuminated sensor.
Description
Technical field
Embodiments of the invention relate to semiconductor applications, relate more specifically to integrated circuit, front illuminated biography
Sensor, backside-illuminated sensor and three dimensional integrated circuits.
Background technology
Many modern electronic devices include that the optical imaging device using imageing sensor is (such as, digital
Camera).Including photoelectric detector and the upper setting of integrated circuit (IC) of logic array can be supported
Imageing sensor.The photoelectric detector that can correspond to single pixel is measured corresponding to optical imagery
Incident radiation (such as, light), and support that logic contributes to from IC reading number data.Defeated from IC
The numerical data gone out represents corresponding to the digital coding of optical imagery.
The IC manufacturing process of standard can be with (FSI) technology of illuminated before production and application or back-illuminated type (BSI)
The imageing sensor of technology.By FSI, before being collected at photoelectric detector, light falls IC's
On front side, and through electric interconnection structure, the such as stack of back-end process (BEOL) metal level.
Generally in FSI, BEOL metal level is adjusted structure to have above single photoelectric detector
Opening (hole (aperture)), this is because, if be arranged between incident illumination and photoelectric detector,
The material of BEOL metal level can block light.Photoelectric detector is arrived by this some holes in order to optimize
The quantity of light, generally uses microlens, waveguide and other opticses so that anti-in FSI
Penetrate and minimize and contribute to direct the light to each photoelectric detector.
In BSI, be not the light openings/apertures that passes BEOL metal level, but from dorsal part (that is, with
The face that the stack of BEOL metal level is relative) irradiate sensor.Comparing with FSI, BSI allows light
Photodetector has on a face of sensor on its electricity assembly, and another side and has its light ways for education
Footpath, this allows optical element preferably to separate with electric device.This means can be excellent independent of electricity assembly
Change optical path, and vice versa.The optical constraints condition of BSI is similar to the optical constraints of FSI
Condition, except, in BSI, being generally near the photoelectric detector of microlens location, present light electric-examination
Survey device to be arranged on thinning substrate surface.Additionally, due to BSI eliminate with in BEOL metal level
The relevant constraints in hole, so BSI eliminates the loss mechanisms of incident illumination, potentially device
Provide higher quantum efficiency.
Due to as the FSI of set technology have bigger pixel lower cost apply in be favourable,
And the BSI as emerging technology is favourable in the high-end applications with less pixel, so FSI
It is all the valuable market segments with BSI technology.
Summary of the invention
The embodiment provides a kind of integrated circuit (IC), including: the first substrate, including
It is configured to receive in a first direction the photoelectric detector of light from light source；Interconnection structure, is positioned at described
Above one substrate, and described interconnection structure includes multiple metal levels of overlieing one another in an alternating fashion
And insulating barrier, wherein, light source described in a metal leafing in the plurality of metal level is nearest, and
Light source described in another metal leafing in the plurality of metal level is farthest；And bond pad groove,
Opening from the surface nearest from described light source of described integrated circuit extends in described interconnection structure
And terminate at bond pad, wherein, described bond pad and the described surface of described integrated circuit
Spaced apart and with the plurality of metal level from described light source farthest described in another metal level direct
Contact.
Embodiments of the invention additionally provide illuminated (FSI) sensor before one, including: image sensing
Device substrate, has and is configured to receive the first surface irradiated and second table relative with described first surface
Face, wherein, the array of photoelectric detector is arranged in described first table in described image sensor substrate
Between face and described second surface；Imageing sensor interconnection structure, adjacent described first surface, described
Imageing sensor interconnection structure includes multiple metal levels and the insulating barrier overlie one another in an alternating fashion,
Wherein, the first metal layer and the described first surface of the plurality of metal level are spaced the first vertical dimension,
Described first vertical dimension less than other each metal levels to described first surface other each vertically away from
From；And bond pad structure, spaced and described with the array of described photoelectric detector
Bond pad structure includes extending from the upper surface of described imageing sensor interconnection structure and terminating in connecing
Closing the bond pad groove at pad, wherein, described bond pad directly connects with described the first metal layer
Touch.
Embodiments of the invention additionally provide a kind of back-illuminated type (BSI) sensor, including: image sensing
Device substrate, has and is configured to receive the first surface irradiated and second table relative with described first surface
Face, wherein, the array of photoelectric detector is arranged in described first table in described image sensor substrate
Between face and described second surface；Imageing sensor interconnection structure, adjacent described second surface, and
Described imageing sensor interconnection structure includes multiple metal levels and the insulation overlie one another in an alternating fashion
Layer；CMOS interconnection structure, is positioned at above described imageing sensor interconnection structure, and described CMOS
Interconnection structure includes multiple metal levels and the insulating barrier overlie one another in an alternating fashion；CMOS substrate,
It is arranged on above described CMOS interconnection structure, and described CMOS substrate includes by described
Multiple cmos devices of CMOS interconnection structure interconnection；And bond pad structure, with described photoelectricity
The array of detector is spaced, and described bond pad structure includes from described imageing sensor
The described first surface of substrate extends through described image sensor substrate, through described imageing sensor
Interconnection structure and terminate in the bond pad groove at bond pad, wherein, described bond pad
It is arranged in described CMOS interconnection structure.
Embodiments of the invention additionally provide a kind of three dimensional integrated circuits (3DIC), including: the first lining
The end, there is first surface and be positioned at the second surface above described first surface；Interconnection structure, is positioned at
Above described first substrate, and described interconnection structure include overlieing one another in an alternating fashion multiple
Metal level and insulating barrier, wherein, second surface described in the lower metal leafing in the plurality of metal level
Recently, second surface described in the upper metal leafing in the plurality of metal level is farthest, and middle gold
Belong to layer to be arranged between described upper metallization layer and described lower metal layer；Second substrate, is arranged on institute
State above interconnection structure, described second substrate have be positioned at the 3rd surface above described interconnection structure and
It is positioned at the 4th surface of described 3rd surface；And bond pad groove, from described first substrate
Described first surface in opening extend in described interconnection structure and terminate at bond pad,
Wherein, described bond pad directly contact with described upper metallization layer or with in described intermediate metal layer
One or more direct contacts.
Accompanying drawing explanation
When reading in conjunction with the accompanying drawings, the present invention may be better understood according to the following detailed description
Embodiment.It is emphasized that according to the standard practices in industry, to various parts by than
Example is drawn.It practice, in order to clearly discuss, the size of various parts can be arbitrarily increased or contract
Little.
Fig. 1 shows the collection of front illuminated (FSI) forms of sensor of the bond pad structure with improvement
Become the sectional view of some embodiments of circuit (IC).
Fig. 2 shows the IC of back-illuminated type (BSI) forms of sensor of the bond pad structure with improvement
The sectional view of some embodiments.
Fig. 3 A shows the three-dimensional (3D) of back-illuminated type (BSI) form of the bond pad structure with improvement
The sectional view of other embodiments of IC.
Fig. 3 B shows the sectional view of other embodiments of the 3DIC according to some embodiments.
Fig. 3 C shows the sectional view of other embodiments of the 3DIC according to some embodiments.
Fig. 4 to Fig. 6 shows the FSI bond pad areas such as can being included in the 3DIC of Fig. 1
More detailed example.
Fig. 7 shows that the 3DIC's including BSI sensor of some embodiments according to Fig. 2 is more detailed
Thin example.
Fig. 8 to Figure 10 shows the BSI bond pad in the 3DIC that such as can be included in Fig. 3 A
The more detailed example in region.
Figure 11 shows the FSI sensor for manufacturing the bond pad structure including having improvement
The flow chart of some embodiments of the method for 3DIC.
Figure 12 to Figure 18 shows the exemplary manufacturing process that jointly display is consistent with the method for Figure 11
A series of sectional views.
Figure 19 shows the FSI sensor for manufacturing the bond pad structure including having improvement
The flow chart of some embodiments of the method for 3DIC.
Figure 20 to Figure 28 B shows the exemplary manufacture stream that jointly display is consistent with the method for Figure 19
A series of sectional views of journey.
Figure 29 shows the BSI sensor for manufacturing the bond pad structure including having improvement
The flow chart of some embodiments of the method for 3DIC.
Figure 30 to Figure 40 shows the exemplary manufacturing process that jointly display is consistent with the method for Figure 29
A series of sectional views.
Figure 41 shows the FSI sensor for manufacturing the bond pad structure including having improvement
The flow chart of some embodiments of the method for 3DIC.
Figure 42 to Figure 49 shows the exemplary manufacturing process that jointly display is consistent with the method for Figure 41
A series of sectional views.
Detailed description of the invention
Disclosure below provides many different enforcements for realizing the different characteristic of provided theme
Example or example.The instantiation of assembly and layout is described below to simplify the present invention.Certainly, these
It is only example, and is not intended to limit the present invention.Such as, in the following description, on second component
Square or upper formation first component can include that first component is formed as the reality directly contacted with second component
Execute example, and can also be included between first component and second component and can form additional parts,
So that the embodiment that first component and second component can be not directly contacted with.Additionally, the present invention can
Repeat reference numerals and/or letter in various embodiments.This repeats to be for purposes of simplicity and clarity,
And itself do not indicate the relation between each embodiment discussed and/or configuration.
And, for ease of describing, this can use such as " in ... lower section ", " ... below ",
" bottom ", " ... above ", the space relative terms on " top " etc., in order to describe such as figure
A shown element or parts and another element or the relation of parts.In addition to the orientation shown in figure,
Space relative terms is intended to include device different azimuth in use or operation.Device can be with other
Mode orients (90-degree rotation or in other orientation), and space as used herein relative descriptors can
To explain the most accordingly.
The integrated circuit (IC) of such as BSI IC and FSI IC has bond pad structure, by engaging
Pad structure, integrated circuit coupled to printed circuit board (PCB) etc..Due to some reasons, conventional seam welding
Dish structure is not ideal.Such as, a reason is, the metal of the bond pad of some routines with and
The limited surface district corresponding for the low K dielectrics of the interconnection structure of IC directly contacts.Because low k
Electrolyte is typically porous material, and poor due between low K dielectrics and metal bond pad
Joint, so the bond pad of the BSI IC and FSI IC of some routines can from this porous material " stripping
From ".Occurring if peeled off, the IC produced is the most obsolete, causes during making technique
The wasting of resources.
Therefore, the present invention relates to the improvement buried further in the interconnection structure of BSI IC and FSI IC
Bond pad structure, thus between the surface on the IC below bond pad structure and they provide
Bigger contact surface area and higher joint.Therefore, these bond pad structure improved stop
Metal bond pad " is peeled off " from IC and is helped to improve yield and device reliability.
Fig. 1 to Fig. 3 A shows the BSI IC according to some embodiments of the present invention and the one of FSI IC
A little examples.Fig. 1 provides the reality of front illuminated (FSI) the IC 100a sensor according to some embodiments
Example, and Fig. 2 and Fig. 3 A each provide back-illuminated type (BSI) the IC 100b according to some embodiments,
The example of 100c.Each including and by Photoelectric Detection in these IC (100a, 100b, 100c)
Device 110 composition photosensor arrays 109 correspondence image sensor area 102 and with figure
As the bond pad areas 104 that sensor region 102 is spaced.In certain embodiments, exist
Logic region 106 it is spaced between image sensor area 102 and bond pad areas 104.If deposited
If, logic region 106 may be configured to support one in image sensor area 102
Or the logical device (not shown) of the operation of multiple photoelectric detector 110.
Tool is all included the most briefly referring to figs. 1 through Fig. 3 A, each IC (100a, 100b, 100c)
There is the first substrate of interconnection structure (respectively 114a, 114b, 114c) above it (respectively
108a、108b、108c).It is multiple that each interconnection structure all includes overlieing one another in an alternating fashion
Metal level and insulating barrier.One (respectively 120a, 120b, 120c) in multiple metal levels is from light
Source is nearest, incident illumination 112 from light source near 3DIC (respectively 100a, 100b, 100c), and
Another (respectively 122a, 122b, the 122c) of multiple metal levels is farthest from light source.Bond pad
Groove (respectively 124a, 124b, 124c) extends through interconnection structure and terminates at bond pad
(respectively 126a, 126b, 126c).Bond pad with away from light source metal level (respectively 122a,
122b, 122c) directly contact.' buried ' by this way interconnection structure (respectively 114a,
114b, 114c) in rather than be only bonded to bond pad from the nearest metal level of light source (point
Wei 126a, 126b, 126c) contribute to providing the stronger joint of bond pad, this reduce and connect
Close the probability that pad is peeled off from 3DIC 102a, 102b, 102c.
In certain embodiments, bond pad and metal level are made up of copper, aluminum or aluminum bronze compound,
And the insulating barrier between adjacent metal level is made up of low k dielectric.Bond pad can have
Be enough to allow the size of another structure that bond pad is bonded to such as printed circuit board (PCB).Such as, at figure
In the embodiment of 1, bond pad 126a can have the thickness that scope is from about 500 angstroms to about 3000 angstroms
T, the most about 1400 angstroms；And can have scope from about 10 square microns to about
The surface area of the exposure of 30 square microns, the most about 18 square microns.One
In a little embodiments, other bond pads can have the size that these are identical, but be described herein as and show
The embodiment gone out is not restricted to these sizes.
In the IC 100a of Fig. 1, it is the example of FSI sensor, and interconnection structure 114a is arranged in
Between light source and the first substrate 108a.Therefore, before being received by photoelectric detector 110, incident illumination
112 through the hole 111 (that is, light is through the front side 113 of IC 100a) in interconnection structure 114a.Cause
This, interconnection structure 114a is included in and the first substrate surface 108a ' is spaced the foot of the first distance
Metal level 122a, and the first substrate surface 108a ' interval second distance at topmost metal level 120a.
Second distance is more than the first distance.Such as, foot metal level 122a can be 1 layer of metal, and
Topmost metal level 120a can be the metal layer at top with the thickness bigger than the thickness of foot layer
(such as, metal 8 metal level) is to provide relatively low resistance.Lenticule 128 can aid in and will enter
Penetrate light and guide downwards with through hole 111 to single photoelectric detector 110, and from the different ripples of light
Long corresponding color filter 131 can filter incident illumination 112 so that photoelectric detector 110 is (real at some
Executing in mode is nature achromatopsia) different colours of resolution incident illumination.
As it can be seen, in the embodiment in figure 1, bond pad groove 124a is from interconnection structure upper surface
113 downwardly extend and through topmost metal level 120a.Bond pad 126a is arranged on this seam welding
Directly to contact with foot metal level 122a in dish groove 124a.' being buried ' is at interconnection structure
The bond pad 126a of the end face in 114a rather than being only bonded to topmost layer 120 contributes to providing
The stronger joint of bond pad 126a, which reduce bond pad 126a from IC 100a peel off can
Can property.
The IC 100b of Fig. 2 is the example of BSI sensor, and the first substrate 108b is arranged in light source with mutual
Link between structure 114b, so that incident illumination 112 is received by photoelectric detector 110, and do not have before
Have through interconnection structure 114b (that is, light is through the dorsal part 115 of IC 100b).Interconnection structure 114b
Be included in and the first substrate surface 108b ' be spaced the first distance foot metal level 120b and with
Topmost metal level 122b at first substrate surface 108b ' interval second distance.Second distance is more than the
One distance.Bond pad groove 124b extends up through the first substrate 108b, to interconnection structure 114b
In, and through foot metal level 120b.Bond pad 126b is straight with topmost metal level 122b
Contact.' being buried ' is in interconnection structure 114b rather than is only bonded to foot metal level
The bond pad 126b of the bottom surface of 120b contributes to providing the stronger joint of bond pad 126b, this
Decrease the probability that bond pad 126b peels off from IC 100b.
The IC 100c of Fig. 3 A is another example of BSI sensor, and it has and is arranged in light source and interconnection
The first substrate 108c between structure 114c, so that incident illumination 112 is by photoelectric detector 110
Receive, and be not passed through interconnection structure 114c (that is, light is through the dorsal part 117 of IC 100c) before.
The IC 100c of Fig. 3 A also includes the second substrate 130 being arranged on above the first substrate 108c, wherein,
Interconnection structure 114c is arranged between the first substrate 108c and the second substrate 130.Because the IC of Fig. 3 A
100c includes multiple logical device, the many substrates of complementary metal such as overlieing one another and engaging, so IC
100c is properly termed as " three-dimensional IC ".Second substrate 130 includes can passing through interconnection structure 114c can
It is operatively coupled to multiple complementary metal oxide semiconductors (CMOS)s (CMOS) device of photoelectric detector 110
Part.Interconnection structure 114c includes the first interconnection structure 132 and the coupling coupleding to photoelectric detector 110
Second interconnection structure 134 of the logical device to the second substrate 130.First interconnection structure 132 wraps
Include: and the first surface of the first substrate 108c be spaced the first foot metal level of the first distance
120c；And and the first substrate first surface interval second distance at the first topmost metal level
138, second distance is more than the first distance.Second interconnection structure 134 includes: with the second substrate 130
First surface interval the 3rd distance the second foot metal level 122c；And with the second substrate
Second topmost metal level 142 of first surface interval the 4th distance of 130, the 4th distance is more than the
Three distances.Topmost metal level 138,142 can be than corresponding foot metal level 120c, 122c
Thick to reduce the resistance of topmost metal level.Second topmost metal level 142 to the first topmost metal
Layer 138 than to the first foot metal level 120c closer to.Bond pad groove 124c upwardly extends and wears
Cross the first substrate 108c, through the first interconnection structure 132 and through the second topmost metal level 142,
And terminate at bond pad 126c.Bond pad 126c and the second foot metal level 122c is straight
Contact.Additionally, ' being buried ' rather than is only bonded to foot gold in interconnection structure 114c
The bond pad 126c of the bottom surface belonging to layer 122c contributes to providing the stronger joint of bond pad 126c,
Which reduce the probability that bond pad 126c peels off from 3DIC 100c.
Although bond pad 126a to bond pad 126c is shown as and from incidence in Fig. 1 to Fig. 3 A
The farthest metal level of light 112 directly contacts, but in certain embodiments, this to will with link mutually
The bond pad that other intermediate metal layers in structure 114a to interconnection structure 114c directly contact is benefited.
Such as, relative to Fig. 1, in some alternative embodiments, bond pad 126a does not couple directly to
Lower metal layer 122a, and it is coupled to the second metal level 125 (it is away from incident illumination second).Connect
Close pad 126a can directly contact with the 3rd metal level 127 alternatively.In some alternative embodiments,
Because bond pad 126a ' buries ' in interconnection structure 114a the most slightly, but with routine
Method is compared, and these embodiments still can provide some improvement that opposing " is peeled off ".To Fig. 2 and
Fig. 3 A makes similar amendment, and therefore, bond pad 126b and bond pad 126c can be with link mutually
Structure 114b directly contacts with the intermediate metal layer in interconnection structure 114c.
Although additionally, Fig. 1 to Fig. 3 A shows the bond pad under FSI IC and BSI IC background,
Wherein, bond pad areas 104 is laterally set around image sensor area 102；But should
Understand, although this bond pad is conceived function in FSI IC and BSI IC, but these seam weldings
Dish design is generally applicable for any kind of IC.Therefore, Fig. 3 B shows by interconnection structure 306
The example of the 3DIC 300 of the first substrate 302 that place is bonded together and the second substrate 304 composition.Also
The substrate (not shown) that adds and/or additional interconnection structure can be included.Therefore, with bond pad
Region 104 is compared around Fig. 1 to Fig. 3 A of image sensor area 102, and Fig. 3 B shows joint
Welding disking area 308 is around the example in IC region 310.IC region 310 is not restricted to photoelectric detector,
But can correspond to any type in IC region, and such as, such as logic region, MEMS district
Territory, cmos device region, capacitor area, biosensor area, memory area, test
Structural region or BiCMOS region.In such embodiments, bond pad structure can include
The pad recess 312 terminated at bond pad 314, wherein, bond pad 314 be buried in mutually
The metal level linked in structure 306 directly contacts.
In the example of Fig. 3 B, the first substrate 302 has first surface 316 and second surface 318.
Interconnection structure 306 is arranged in above the first substrate 302 and includes overlieing one another in an alternating fashion
Multiple metal levels and insulating barrier.Lower metal layer 320 is nearest from second surface 318, upper metallization layer
322 is farthest from second surface 318, and intermediate metal layer is (such as, 324,326,328,330,
332,334) it is arranged between upper metallization layer and lower metal layer.Set above interconnection structure 306
Put the second substrate 304.Second substrate 304 has the 3rd surface 336 being positioned at above interconnection structure 306
With the 4th surface 338 being positioned at above the 3rd surface 336.Bond pad groove 312 is from first surface
In opening in 316 extends to interconnection structure 306 and terminate at bond pad 314.Seam welding
Dish 314 and upper metallization layer 322 or with one or more intermediate metal layers (such as, 324,326,
328,330,332,334) directly contact.
Interconnection structure 306 can include the first interconnection structure 340 and the second interconnection structure overlie one another
342.First interconnection structure 340 is arranged on above the first substrate 302 and coupled in the first substrate
Semiconductor device.First interconnection structure 340 includes the first son of multiple metal levels of interconnection structure 306
Collection.First lower metal layer 320 of the first interconnection structure 340 is nearest from second surface 318, and first
First upper metallization layer 330 of interconnection structure 340 is farthest from second surface 318, and in the middle of first
Metal level 332,334 is arranged between the first lower metal layer 320 and the first upper metallization layer 330.
Second interconnection structure 342 is arranged on above the first interconnection structure 340 and coupled to the second substrate 304
Semiconductor device.Second interconnection structure 342 includes the second of multiple metal levels of interconnection structure 306
Subset, wherein, the second subset is the most overlapping with the first subset.Second bottom of the second interconnection structure 342
Metal level 322 is nearest from the 3rd surface 336, the second upper metallization layer 328 of the second interconnection structure 342
Farthest from the 3rd surface 336, and the second intermediate metal layer 326,324 is arranged on the second lower metal
Between layer 322 and the second upper metallization layer 328.First upper metallization layer 330 and the second upper metal
Layer 328 can be thicker than the first lower metal layer 320 and the second lower metal layer 322 respectively.At some
In embodiment, bond pad 314 and second upper metallization layer the 328, second lower metal layer 322 or
Directly contact with one or more second intermediate metal layers 326,324.In other embodiments, engage
Pad 314 and the first upper metallization layer 330 or with one or more first intermediate metal layers 332,334
Directly contact.
Fig. 3 C shows another example, wherein, and first mutual with such as another example of bond pad 314b
The intermediate metal layer 332 linked in structure 314 directly contacts.
Now under the background of FSI IC and BSI IC, provide some more detailed examples.Fig. 4 is to figure
6 show the more detailed of the FSI bond pad areas that such as can be included in the 3DIC of Fig. 1
Example.
The bond pad areas 400 of Fig. 4 at the example of the bond pad areas as FSI sensor
In, interconnection structure 114a ' is arranged between light source and the first substrate 108a, in certain embodiments should
First substrate is properly termed as again imaging substrate.Interconnection structure 114a ' is included in the first substrate 108a's
First surface be spaced the first distance foot metal level 122a ' (such as, 1 layer of metal), with
Topmost metal level 120a ' at the first surface interval second distance of the first substrate (108a) is (such as,
8 layers of metal).Second distance is more than the first distance.The thickness of topmost metal level 120a ' can be more than
The thickness of foot metal level 122a ' is to provide relatively low resistance.Interlayer dielectric (ILD) layer 118 will
Metal level is separated from one another.Metal level is electrically coupled to one another by through hole 404, and contact (not shown)
Foot metal level 122a ' is electrically coupled on photoelectric detector 110 and/or the first substrate 108a its
His device.Metal level 120a ', 122a ', through hole 404 and/or contact can be made of an electrically conducting material,
Such as aluminum bronze or tungsten or some other metals or conductive material.Such as, ILD layer 118 can be
Low k dielectric.
Bond pad groove 124a ' downwardly extends from the upper surface of interconnection structure 114a ' and through most
Portion metal level 120a '.The bond pad groove 124a ' illustrated has angled sidewall 404a, 406b,
Therefore, lower sides opens the first distance d1 in foot metal level 122a ' interval around.Sidewall 406a,
406b is spaced farther apart from the second distance d2 bigger than the first distance d1 at upper portion side wall.Such as,
The side wall spacer 402 being made up of the dielectric material of such as oxide cover angled sidewall 406a,
406b and extending above at the upper surface of interconnection structure.Side wall spacer 402 has contiguous engagement pad
The medial wall of the vertical or perpendicular of the lateral wall of 126a '.The lower surface of bond pad 126a ' with
Foot metal level 122a ' direct physical and electrical contact.In certain embodiments, bond pad 126a '
Upper and lower surface can be smooth or substantially flat.
In the bond pad areas 500 of Fig. 5, FSI bond pad structure includes having angled side
The bond pad groove 124a of wall 506a, 506b ".Bond pad 126a " is arranged on this bond pad recessed
The lower surface that groove 124a " in have and foot metal level 122a " directly contacts.Bond pad 126a "
Also have and abut directly against bond pad groove 124a " angled sidewall 506a, 506b and ILD layer
The lateral wall of 118.For example, it is possible to the dielectric liner 502 being made up of oxide is arranged on bond pad
Above the upper surface of 126a " top and interconnection structure 114a ".Fluting bond pad 126a " core,
So that the prominent marginal area of bond pad upwardly extends from the base portion of bond pad；And it is situated between
The electricity medial wall of liner 502 and bond pad 126a " medial wall alignment.
In figure 6, it is provided that according to another example of the BSI structure of some embodiments.Fig. 6's
In BSI structure, bond pad have the sidewall corresponding with metal level directly make electrical contact with and not with gold
Belong to upper surface or the sidewall of lower surface contact of layer.Such coupling can also contribute at bond pad
And bigger zygosity is provided between IC and contributes to stoping stripping.
In fig. 7 it is shown that the FSI bond pad areas such as can being included in the 3DIC of Fig. 2
More detailed example.In the example of figure 7, bond pad has the cross section of u shape, wherein, hangs down
Straight projection upwardly extends from the base portion of bond pad.Bond pad is arranged on and has eliminated substrate
On the marginal area of 3DIC.
Fig. 8 to Figure 10 shows that the FSI in the 3DIC 100c that such as can be included in Fig. 3 A engages
The more detailed example of welding disking area.
In fig. 8, in certain embodiments, BSI bond pad areas 800 includes being referred to as
First substrate 108c ' of imaging substrate and the second substrate 130 ' of CMOS substrate can also be referred to as.Mutually
Link structure 114c ' and include that be properly termed as imageing sensor interconnection structure in certain embodiments first is mutual
Link structure 132 ' and be properly termed as the second interconnection structure of CMOS interconnection structure in certain embodiments
134′.Interconnection structure 114c ' is arranged between imaging substrate 108c ' and CMOS substrate 130 '.Seam welding
Dish groove 124c ' extends through imaging substrate 108c ', through imaging interconnection structure 134 ' and extremely
CMOS interconnection structure 132 ' is interior and terminates in bond pad 126c ' place.Bond pad 126c ' with
Foot metal level 120c ' direct physical and electricity from the nearest imaging interconnection structure of CMOS substrate 130 '
Contact.Multilamellar passivating structure 146 can extend above at imaging substrate 108c ', and can include groove
Type flat plane antenna (SPA, slot-plane-antenna) free-radical oxidation nitride layer 802, HfO2Layer 804,
Ta2O5Layer 806, the oxide skin(coating) (PEOx) 808 of plasma enhancing, silicon nitride (SiN) layer
810, barrier layer (such as, Ti, TiN or W) 812 and oxide skin(coating) 814.
Bond pad groove 124c ' has angled sidewall 804a, 804b.Under bond pad groove
Portion's part 807 is generally of the first width, and bond pad groove is widened at shoulder regions 809,
So the upper part 811 of bond pad groove has the second width more than the first width.Upper side wall
Part covers the outer edge region (804) of the neighbouring bond pad groove of bond pad.Oxide liners
814 downwardly extend along the sidewall of the upper part 811 of bond pad groove.Because bond pad 126c '
Outward flange covered by the sidewall of CMOS interconnection structure 132 ', so compared with some additive methods,
Oxide skin(coating) 910 can help to reduce " stripping " of bond pad.
Fig. 9 shows another embodiment of the bond pad areas 900 for BSI sensor.At this
In example, the inner side of bond pad 126c " be the cross section of u-shaped and along the second interconnection structure 134 "
Wall conformally extends and abuts directly against the first interconnection structure 132 " topmost metal level 902.Cause
This, with the bond pad illustrated before and metal level (such as, the foot farthest from incident illumination 112
The example of metal level 120c ") directly contact is compared, and Fig. 9 shows bond pad 126c " with link mutually
Structure 114c " in the example that directly contacts of intermediate metal layer (such as, topmost metal level 902).Connect
Close pad 126c " topmost part project upwardly beyond shoulder regions 909 to bond pad groove 124 "
Upper part in.Conformal oxide skin(coating) 810 is arranged on above the sidewall of groove, and another oxygen
Compound layer 910 is arranged on above conformal oxide skin(coating) 810.Oxide skin(coating) 910 can have downwards
Extend low portion 912 to cover bond pad 126c " medial wall.In the example of Fig. 9, connect
Close pad 126c and " there is the vertical or sidewall of perpendicular and have smooth or substantially planar
The base portion of upper and lower surface.Because it is arranged on bond pad 126c " edge above, so
Compared with some additive methods, oxide skin(coating) 910 can aid in " stripping " reducing bond pad.
Figure 10 shows another embodiment of another bond pad areas 1000 for BSI sensor.
In this example, bond pad 126c " ' be the cross section of V-shaped and along the second interconnection structure 134 " '
Medial wall conformally extend and abut directly against the first interconnection structure 132 " ' topmost metal level.
Bond pad 126 " ' topmost part project upwardly beyond shoulder regions 1009 to bond pad groove
124c " ' upper part in.Oxide skin(coating) 1008 is arranged on bond pad 126c " ' top and
The medial wall of bond pad can be covered in the case of Xie.Because it is arranged on bond pad 126c " ' limit
Above edge, so compared with some additive methods, oxide skin(coating) 1008 can aid in reduction seam welding
Dish 126c " ' " stripping ".
Figure 11 provides the 3DIC of the FSI sensor for manufacturing the connected structure including having improvement
The flow chart of some embodiments of method 1100.Although the disclosure illustrated in this article and/or describe
Method 1100 and additive method can illustrate and/or be described as series of steps or event, but should
Understand that these steps or illustrating of event sequentially do not have limitation.Such as, some steps can be with
Different order occur and/or with other steps in addition to illustrated herein and/or described step or event
Or event occurs simultaneously.Furthermore, it is possible to do not require that all steps illustrated all are retouched herein for enforcement
The one or more aspects stated or embodiment, and can be on one or more single steps and/or rank
One or more steps shown herein is carried out in Duan.
In step 1102, the first substrate is received.First substrate has the light being arranged in the first substrate
Photodetector and have the first interconnection structure on the first substrate is set.
In step 1104, above the first interconnection structure, the first mask is formed.Utilize suitable position
In the first mask implement the first etching to expose the lower metal layer in interconnection structure.
In a step 1106, above the lower metal layer exposed, bond pad material is formed.
In step 1108, above bond pad material, the second mask is formed.Utilize suitable position
In the second mask implement the second etching with the bond pad that directly contacts with lower metal layer of formation.
In step 1110, above the upper surface and sidewall of bond pad, dielectric layer is formed.
In step 1112, implement chemical-mechanical planarization (CMP) with planarizing dielectric.
In step 1114, the dielectric layer in planarization forms the 3rd mask.Utilize suitable position
The 3rd mask in putting implements the 3rd etching to be exposed for the upper surface of the bond pad of joint.
Referring to figs 12 to Figure 18, it is provided that jointly illustrate the example consistent with some examples of Figure 11
A series of sectional views of property manufacturing process.Although it is relevant with the method to describe Figure 12 to Figure 18, but
It should be understood that structure disclosed in Figure 12 to Figure 18 is not restricted to the method, but can be as independence
Structure individualism in method.Similarly, although the method for description is relevant with Figure 12 to Figure 18, but
It is it should be understood that method is not restricted to the structure disclosed in Figure 12 to Figure 18, but can be independent of
Structure individualism disclosed in Figure 12 to Figure 18.
Figure 12 shows the sectional view of some embodiments of the step 1102 corresponding to Figure 11.At figure
In 12, receive Semiconductor substrate 108a.First substrate 108a has the light being arranged in the first substrate
Photodetector and have the first interconnection structure 114a on the first substrate is set.In some embodiments
In, the first substrate 108a can be bulk silicon substrate or the semiconductor-on-insulator of plate-like wafer form
(SOI) substrate (such as, silicon-on-insulator substrate).Such as, the first substrate 108a is also binary
Semiconductor substrate (e.g., GaAs), ternary semiconductor substrate (e.g., AlGaAs), higher order number
Semiconductor substrate or even Sapphire Substrate.First substrate 108a can include being formed in the substrate or
On doped region, formed in the substrate or on epitaxial layer, formed in the substrate or on insulating barrier,
Formed in the substrate or on photoresist layer and/or formed in the substrate or on conductive layer.Such as,
In many examples, the first substrate 108 of wafer form can have a following diameter: 1 inch (25mm)；
2 inches (51mm)；3 inches (76mm)；4 inches (100mm)；5 inches (130mm)
Or 125mm (4.9 inches)；150mm (5.9 inches, commonly referred to " 6 inches ")；200mm
(7.9 inches, commonly referred to " 8 inches ")；300mm (11.8 inches, commonly referred to " 12 English
Very little ")；Or 450mm (17.7 inches, commonly referred to " 18 inches ").
Interconnection structure 114a include ILD layer 118 and the metal level 122a being stacked on respectively between ILD layer,
125,127 and 120a.Metal level including upper metallization layer 120a with metal wire passes through through hole
404 are electrically coupled to one another.Such as, ILD layer 118 can be low-k dielectrics or silicon oxide.Such as, gold
Belong to layer 122a, 125,127 and 120a, through hole 404 can be such as aluminum, copper or tungsten or copper aluminum
The metal of compound.
Figure 13 shows the sectional view of some embodiments of the step 1104 corresponding to Figure 11.As schemed
Show, above the first interconnection structure 114a, form the first mask 1300.Such as, the first mask 1300
Can be photoresist mask and/or the hard mask of such as nitride hardmask.Utilize in suitable position
The first mask 1300, implement the first etching 1302 to expose the lower metal in interconnection structure 114a
Layer (such as, 122a).In other embodiments, can expose metal layer 125 or 127 alternatively.
After implementing the first etching 1302, the first mask 1300 can be removed.
Figure 14 shows the sectional view of some embodiments of the step 1106 corresponding to Figure 11.At figure
In 14, above lower metal layer 122a exposed and interconnection structure 114a, it is conformally formed seam welding
Disc layer 1400.Gas deposition (such as, chemical vapor deposition (CVD) or plasma vapour can be used
Mutually deposition (PVD)), electroplate, sputter or any other suitable deposition technique formed seam welding
Disc layer 1400.
Figure 15 shows the sectional view of some embodiments of the step 1108 corresponding to Figure 11.At figure
In 15, above bond pad layer 1400, form the second mask 1500.Such as, the second mask 1500
Can be photoresist mask and/or the hard mask of such as nitride hardmask.Utilize in suitable position
The second mask 1500 implement the second etching 1502 with formed directly contact with lower metal layer 122a
Bond pad 126a.In the example of Figure 15, bond pad 126a have with in interconnection structure
The lateral wall that sidewall spacers is opened.After the second etching 1502, the second mask 1500 can be removed.
Figure 16 shows the sectional view of some embodiments of the step 1110 corresponding to Figure 11.At figure
In 16, above the upper surface and sidewall of bond pad, form dielectric layer 1600.As it can be seen, dielectric
The interval that layer 1600 is completely filled with between bond pad and interconnection structure.For example, it is possible to by CVD,
PVD, oxidation, spin coating technique or any other deposition technique form dielectric layer 1600.
Figure 17 shows the sectional view of some embodiments of the step 1112 corresponding to Figure 11.At figure
In 17, implement chemical-mechanical planarization (CMP) 1700 with planarized dielectric layer 1600.
Figure 18 shows the sectional view of some embodiments of the step 1114 corresponding to Figure 11.At figure
In 18, above the dielectric layer 1600 of planarization, form the 3rd mask 1800.Utilize suitable position
In the 3rd mask 1800 implement the 3rd etching 1802 again to expose the upper surface of bond pad,
And remove the 3rd mask the most alternatively to prepare the bond pad 126a that produces for joint.
Figure 19 provides the 3DIC of the FSI sensor for manufacturing the connected structure including having improvement
The flow chart of some embodiments of method 1900.
In step 1902, receive the first substrate.First substrate has the light being arranged in the first substrate
Photodetector and have the first interconnection structure on the first substrate is set.
In step 1904, above the first interconnection structure, form the first mask.Utilize suitable position
In the first mask implement the first etching to expose the lower metal layer in interconnection structure.
In step 1906, above the lower metal layer exposed, form bond pad layer.
In step 1908, above the upper surface and sidewall of bond pad layer, form dielectric layer.
In step 1910, above bond pad material, form the second mask.Utilize suitable position
In the second mask implement the second etching with the bond pad that directly contacts with lower metal layer of formation.
In step 1912, implement the 3rd etching and make etch-back with optionally etch-back conductive layer
The upper surface of conductive layer and the upper surface flush of interconnection structure or be positioned at below the upper surface of interconnection structure.
By this way, the bond pad above it with dielectric cap (dielectric cap) is formed.
In step 1914, above the upper surface and sidewall of dielectric cap, form conformal dielectric layer.
Conformal dielectric layer also extends above at the upper surface of interconnection layer.
In step 1916, implement the CMP upper surface with plat structure.
In step 1918, optionally remove the remainder of dielectric cap to expose bond pad
Core is for joint.
Referring to figures 20 through Figure 28, it is provided that jointly illustrate the example consistent with some examples of Figure 19
A series of sectional views of property manufacturing process.
Figure 20 shows the sectional view of some embodiments of the step 1902 corresponding to Figure 19.At figure
In 20, receive the first substrate 108a.First substrate 108a can at least with about Figure 12 before institute
That states is substantially the same.
Figure 21 shows the sectional view of some embodiments of the step 1904 corresponding to Figure 19.As schemed
Show, above the first interconnection structure 114a, form the first mask 2100.Such as, the first mask 2100
Can be photoresist mask and/or the hard mask of such as nitride hardmask.Utilize in suitable position
The first mask 2100, implement the first etching 2102 to expose the lower metal in interconnection structure 114a
Layer (such as, 122a).In other embodiments, can expose metal layer 125 or 127 alternatively.
After implementing the first etching 2102, the first mask 2100 can be removed.
Figure 22 shows the sectional view of some embodiments of the step 1906 corresponding to Figure 19.At figure
In 22, above lower metal layer 122a exposed and interconnection structure 114a, form bond pad layer 2200.
In certain embodiments, bond pad layer can include aluminum or copper or aluminum bronze compound.Vapour can be used
Mutually deposition (such as, chemical vapor deposition (CVD) or plasma vapor deposition (PVD)),
Plating, sputtering or any other suitable deposition technique form bond pad layer 2200.
Figure 23 shows the sectional view of some embodiments of the step 1908 corresponding to Figure 19.At figure
In 23, above the upper surface and sidewall of bond pad layer 2200, form dielectric layer 2300.
Figure 24 shows the sectional view of some embodiments of the step 1910 corresponding to Figure 19.At figure
In 24, above bond pad material, form the second mask 2400.Utilize second in suitable position
Mask implements the second etching 2402 to remove leading of the outside being positioned at bond pad groove of dielectric layer
Part above the uppermost surface of electric layer.
Figure 25 shows the sectional view of some embodiments of the step 1912 corresponding to Figure 19.At figure
In 25, implement the 3rd and etch 2500 conductive layers making etch-back with optionally etch-back conductive layer
The upper surface flush of upper surface and interconnection structure or be positioned at below the upper surface of interconnection structure.With so
Mode, form the bond pad above it with dielectric cap 2504.
Figure 26 shows the sectional view of some embodiments of the step 1914 corresponding to Figure 19.At figure
In 26, above the upper surface and sidewall of dielectric cap 2504, form conformal dielectric layer 2600.Altogether
The dielectric layer 2600 of shape also extends above at the upper surface of interconnection layer.For example, it is possible to by CVD,
PVD, oxidation, spin coating technique or any other deposition technique form conformal dielectric layer 2600.
Figure 27 shows the sectional view of some embodiments of the step 1916 corresponding to Figure 19.At figure
In 27, implement the CMP upper surface with plat structure.
Figure 28 shows the sectional view of some embodiments of the step 1918 corresponding to Figure 19.At figure
In 28, optionally remove the remainder of dielectric cap to expose the central part of bond pad 2502
Divide for joint.
Figure 28 B shows another alternative embodiment.
Figure 29 provides the 3DIC of the FSI sensor for manufacturing the connected structure including having improvement
The flow chart of some embodiments of method 2900.
In step 2902, receive the IC including the first substrate.Oneth IC has and is arranged on
Photoelectric detector in one substrate and there is the first interconnection structure arranged on the first substrate.First
Interconnection structure is operably coupled to photoelectric detector.
In step 2904, receive the 2nd IC including the second substrate.2nd IC has and is arranged on
CMOS transistor in two substrates and there is the second interconnection structure being arranged on above the second substrate.
Second interconnection structure is operably coupled to CMOS transistor.
In step 2906, an IC is bonded to the 2nd IC so that the first interconnection structure and second mutual
Link structure to arrange adjacent to each other and be arranged between the first substrate and the second substrate.
In step 2908, formed blunt above the sidepiece relative with the first interconnection structure of the first substrate
Change layer.
In step 2910, the most square one-tenth the first mask.Utilize in suitable position
One mask, performs the first etching to form groove through the first substrate.Groove stops between the first lining
On dielectric layer between the end and the first interconnection structure.
In step 2912, form dielectric layer in a groove.
In step 2914, the most square one-tenth the second mask, and utilize in suitable position
The second mask implement the second etching to form bond pad groove.Bond pad groove includes having
The upper part and having of the angled sidewall separating the first width separates less than the first width
The low portion of the angled sidewall of the second width.Bond pad groove exposes in the second interconnection structure
Metal level.
In step 2916, the sidewall of low portion and lower surface of bond pad groove are formed and connects
Close pad.
In step 2918, above bond pad, form dielectric layer to fill the surplus of bond pad groove
Remaining upper part and low portion.
In step 2920, above the upper surface of dielectric layer, form barrier layer and oxide skin(coating).
In step 2922, the most square one-tenth the 3rd mask, and utilize in suitable position
The 3rd mask implement the 3rd etching to expose bond pad upper at the bottom surface of bond pad groove
Surface.
With reference to Figure 30 to Figure 40, it is provided that jointly illustrate the example consistent with some examples of Figure 29
A series of sectional views of property manufacturing process.
Figure 30 shows the sectional view of some embodiments of the step 2902 corresponding to Figure 29.At figure
In 30, it is provided that include an IC of the first interconnection layer above the first substrate and the first substrate.First
Substrate include photoelectric detector and can at least with about described substantially the same before Figure 12.
First interconnection structure 114a include ILD layer 118 and the metal level 122a being stacked on respectively between ILD layer,
125,127 and 120a.Metal level including upper metallization layer 120a with metal wire passes through through hole
404 are electrically coupled to one another.Such as, ILD layer 118 can be low-k dielectrics or silicon oxide.Such as, gold
Belong to layer 122a, 125,127 and 120a, through hole 404 can be such as aluminum, copper or tungsten or copper aluminum
The metal of compound.
Figure 31 shows the sectional view of some embodiments of the step 2904 corresponding to Figure 29.At figure
In 31, it is provided that include the 2nd IC of the second interconnection layer above the second substrate and the second substrate.Second
Substrate can include cmos device and can be shown without photoelectric detector or not have Photoelectric Detection
The array of device and the bulk silicon substrate as described in can including before about Figure 12, SOI substrate
Or other substrates.Second interconnection structure 114a includes ILD layer 118 and is stacked between ILD layer
Metal level.The metal level that second interconnection structure can have with an IC equal number maybe can have not
Metal level with quantity.Metal level including upper metallization layer 120a with metal wire passes through through hole
404 are electrically coupled to one another.Foot metal level is coupled to device area by contact (not shown), all
As in the second substrate or close on gate electrode or the regions and source/drain of the second substrate.Such as, ILD layer
118 can be low-k dielectrics or silicon oxide.Such as, metal level 120a, 122a, 125,127 and
Through hole 404 can be such as aluminum, copper or tungsten or the metal of copper aluminium compound.
Figure 32 shows the sectional view of some embodiments of the step 2906 corresponding to Figure 29.At figure
In 32, an IC and the 2nd IC is bonded together.The example engaged can include, but are not limited to melt
Fuse conjunction or eutectic engages.
Figure 33 shows the sectional view of some embodiments of the step 2908 corresponding to Figure 29.At figure
In 33, above the sidepiece relative with the first interconnection structure of the first substrate, form passivation layer 146.Blunt
Change layer 146 and can include grooved flat plane antenna (SPA) free-radical oxidation nitride layer 802, HfO2Layer 804,
Ta2O5Layer 806, the oxide skin(coating) (PEOx) 808 of plasma enhancing, silicon nitride (SiN) layer
810, barrier layer (such as, Ti, TiN or W) 812 and oxide skin(coating) 814.
Figure 34 shows the sectional view of some embodiments of the step 2910 corresponding to Figure 29.At figure
In 34, above passivation layer 146, form the first mask 3400, and utilize in suitable position
One mask 3400 performs the first etching 3402 to form the groove 3404 through the first substrate.First
Etch stop on the dielectric layer 3406 of such as oxide skin(coating), this dielectric layer by the first substrate 108c with
First interconnection structure separates.First mask 3400 is formed at above passivation layer and can be such as photoetching
The hard mask of glue mask and/or such as nitride hardmask.In other embodiments, can be alternatively
Expose the lower metal layer in the second interconnection structure.After implementing the first etching 3402, can remove
First mask 3400.
Figure 35 shows the sectional view of some embodiments of the step 2912 corresponding to Figure 29.At figure
In 35, form dielectric layer 3500 in a groove.Such as, dielectric layer 3500 can be oxide, all
Such as silicon dioxide.
Figure 36 shows the sectional view of some embodiments of the step 2914 corresponding to Figure 29.At figure
In 36, the most square one-tenth the second mask 3602, and utilize in suitable position second to cover
Mould implements the second etching 3604 to form bond pad groove 3606.Bond pad groove includes tool
The upper part 3608 having the angled sidewall separating the first width separates ratio first with having
The low portion 3610 of the angled sidewall of the second width that width is little.Bond pad groove exposes the
Metal level 3612 in two interconnection structures.
Figure 37 shows the sectional view of some embodiments of the step 2916 corresponding to Figure 29.At figure
In 37, the sidewall of low portion and lower surface of bond pad groove form bond pad 126c " '.
Bond pad 126c can be formed by following operation " ': in sidewall and the following table of bond pad groove
The conformal conductive layer of such as copper, aluminum or copper aluminium compound is formed on face；On the bottom of conductive layer
The mask of square one-tenth such as photoresist mask；And it is then carried out etching to remove the selection of conductive layer
Part is to leave bond pad in the low portion of bond pad groove.
Figure 38 shows the sectional view of some embodiments of the step 2918 corresponding to Figure 29.At figure
In 38, above bond pad groove, form dielectric layer 3800 to fill the residue of bond pad groove
Upper part and low portion.Such as, dielectric layer 3800 can be oxide, such as silicon dioxide.
Figure 39 shows the sectional view of some embodiments of the step 2920 corresponding to Figure 29.At figure
In 39, above the upper surface of dielectric layer 3800, form barrier layer 3902 and oxide skin(coating) 3904.Example
As, barrier layer 3902 can be the metal of such as Ti, TiN or W；And such as, oxide skin(coating)
3904 can be silicon dioxide.
Figure 40 shows the sectional view of some embodiments of the step 2922 corresponding to Figure 29.At figure
In 40, the most square one-tenth the 3rd mask 4000, and utilize the 3rd in suitable position to cover
Mould implements the 3rd etching 4010 to expose the bond pad 126c on the bottom surface of bond pad groove " '
Upper surface.Therefore, bond pad 126c is exposed now " ' so that during assembling, such as solder ball
Or the conductive fasteners of other conductor wires is coupled to bond pad 126c " '.
Figure 41 provides the 3DIC of the FSI sensor for manufacturing the connected structure including having improvement
The flow chart of some embodiments of method 4100.
In step 4102, receive the IC including the first substrate.Oneth IC has and is arranged on
Photoelectric detector in one substrate and there is the first interconnection structure arranged on the first substrate.First
Interconnection structure is operably coupled to photoelectric detector.
In step 4104, receive the 2nd IC including the second substrate.2nd IC has and is arranged on
CMOS transistor in two substrates and there is the second interconnection structure being arranged on above the second substrate.
Second interconnection structure is operably coupled to CMOS transistor.
In step 4106, an IC is bonded to the 2nd IC so that the first interconnection structure and second mutual
Link structure to arrange adjacent to each other and be arranged between the first substrate and the second substrate.
In step 4108, formed blunt above the sidepiece relative with the first interconnection structure of the first substrate
Change layer.
In step 4110, the most square one-tenth the first mask.Utilize in suitable position
One mask, performs the first etching with the sidepiece exposing the first substrate.
In step 4112, above the upper surface of dielectric layer, form barrier layer and oxide skin(coating).
In step 4114, form the second mask, and utilize the second mask in suitable position
Implement the second etching to form the upper part of bond pad groove.
In step 4116, above the upper part of bond pad groove, form dielectric layer.
In step 4118, the most square one-tenth the 3rd mask, and utilize in suitable position
The 3rd mask implement the 3rd etching with formed bond pad groove low portion.Bond pad is recessed
The low portion of groove exposes the metal level in the second interconnection structure.
In step 4120, the sidewall of low portion and lower surface of bond pad groove are formed altogether
The conductive layer of shape.
In step 4122, above conformal conductive layer, form dielectric layer to fill bond pad groove
Remaining upper part and low portion.
In step 4124, the most square one-tenth the 4th mask, and utilize in suitable position
The 4th mask implement the 4th etching with expose bond pad upper surface.
With reference to Figure 42 to Figure 49, it is provided that jointly illustrate the example consistent with some examples of Figure 41
A series of sectional views of property manufacturing process.
Figure 42 shows the sectional view of some embodiments of the step 4108 corresponding to Figure 41.At figure
Before 42, an IC and the 2nd IC is bonded together and forms passivation layer above it, such as it
Front about described in Figure 30 to Figure 33.In Figure 42, above passivation layer 146, form the first mask
4200, and utilize the first mask 4200 in suitable position to perform the first etching 4202 with shape
Become the groove 4204 through the first substrate.First etching 4202 stops at the dielectric of such as oxide skin(coating)
On layer 3406, the first substrate 108c and the first interconnection structure are separated by this dielectric layer.First mask 4200
It is formed at above passivation layer and can be such as photoresist mask and/or such as nitride hardmask
Hard mask.In other embodiments, the lower metal layer in the second interconnection structure can be exposed alternatively.
After implementing the first etching 4202, the first mask 4200 can be removed.
Figure 43 shows the sectional view of some embodiments of the step 4112 corresponding to Figure 41.At figure
In 43, above the upper surface of dielectric layer, form barrier layer 4302 and oxide skin(coating) 4304.
Figure 44 shows the sectional view of some embodiments of the step 4114 corresponding to Figure 41.At figure
In 44, form the second mask 4400, and utilize the second mask 4400 in suitable position real
Execute the second etching 4402 to form the upper part 4404 of bond pad groove.
Figure 45 shows the sectional view of some embodiments of the step 4116 corresponding to Figure 41.At figure
In 45, above the upper part of bond pad groove, form dielectric layer 4500.
Figure 46 shows the sectional view of some embodiments of the step 4118 corresponding to Figure 41.At figure
In 46, the most square one-tenth the second mask 4600, and utilize in suitable position second to cover
Mould 4600 implements the second etching 4602 to form the low portion 4604 of bond pad groove.Engage
The low portion 4604 of pad recess exposes the metal level 4606 in the second interconnection structure.
Figure 47 shows the sectional view of some embodiments of the step 4120 corresponding to Figure 41.At figure
In 47, the sidewall of low portion and lower surface of bond pad groove form bond pad 4700.
Bond pad 4700 can be formed: at sidewall and the lower surface of bond pad groove by following operation
The conformal conductive layer of upper formation such as copper, aluminum or copper aluminium compound；Above the bottom of conductive layer
Form the mask of such as photoresist mask；And it is then carried out etching the portion of the selection to remove conductive layer
Divide to leave bond pad in the low portion of bond pad groove.
Figure 48 shows the sectional view of some embodiments of the step 4122 corresponding to Figure 41.At figure
In 48, above conformal conductive layer, form dielectric layer 4800 to fill the residue of bond pad groove
Upper part and low portion.
Figure 49 shows the sectional view of some embodiments of the step 4124 corresponding to Figure 41.At figure
In 49, the most square one-tenth the 3rd mask 4900, and utilize the 3rd in suitable position to cover
Mould implements the 3rd etching to expose the upper surface of bond pad.
Therefore, as from above it should be understood that the invention provides a kind of three-dimensional (3D) integrated circuit
(IC).3DIC includes the first substrate, and this first substrate includes being configured in a first direction from light source
Receive the photoelectric detector of light.Interconnection structure is arranged on above the first substrate and includes with side alternately
Multiple metal levels that formula overlies one another and insulating barrier.In multiple metal levels one is nearest from light source, and
And another in multiple metal level is farthest from light source.Bond pad groove is from the 3DIC nearest from light source
Surface in opening extend in interconnection structure and terminate at bond pad.Bond pad with
The spaced apart from surfaces of 3DIC and the metal level farthest from light source with multiple metal levels directly connect
Touch.
In other embodiments, the invention provides illuminated (FSI) sensor before one.FSI senses
Device includes having the first surface being configured to receive irradiation and the figure of the second surface relative with first surface
As sensor substrate.The array of photoelectric detector be arranged in image sensor substrate first surface and
Between second surface.Imageing sensor interconnection structure adjoins second surface.Imageing sensor interconnection structure
Including the multiple metal levels overlie one another in an alternating fashion and insulating barrier.In multiple metal levels first
Metal level and second surface are spaced the first vertical dimension.First distance less than from other each metal levels to
Other each vertical dimensions of second surface.Between the array of bond pad structure and photoelectric detector is horizontal
Separate and include extending from the upper surface of imageing sensor cross tie part and terminating at bond pad
Bond pad groove, wherein, bond pad directly contacts with the first metal layer.
Other embodiments relate to a kind of back-illuminated type (BSI) sensor.BSI sensor includes having configuration
For receiving the first surface and the image sensor substrate of the second surface relative with first surface irradiated.
The array of photoelectric detector is arranged between first surface and second surface in image sensor substrate.
It is multiple that imageing sensor interconnection structure adjoins that second surface and including overlies one another in an alternating fashion
Metal level and insulating barrier.CMOS interconnection structure is arranged in above imageing sensor interconnection structure and wraps
Include the multiple metal levels and insulating barrier overlie one another in an alternating fashion.CMOS substrate is arranged on
Above CMOS interconnection structure and include the multiple cmos devices interconnected by CMOS interconnection structure.
Bond pad structure is spaced with the array of photoelectric detector and includes from image sensor substrate
First surface extend through image sensor substrate, through imageing sensor interconnection structure and eventually
The only bond pad groove at bond pad, wherein, bond pad is arranged on CMOS interconnection structure
In.
The embodiment provides a kind of integrated circuit (IC), including: the first substrate, including
It is configured to receive in a first direction the photoelectric detector of light from light source；Interconnection structure, is positioned at described
Above one substrate, and described interconnection structure includes multiple metal levels of overlieing one another in an alternating fashion
And insulating barrier, wherein, light source described in a metal leafing in the plurality of metal level is nearest, and
Light source described in another metal leafing in the plurality of metal level is farthest；And bond pad groove,
Opening from the surface nearest from described light source of described integrated circuit extends in described interconnection structure
And terminate at bond pad, wherein, described bond pad and the described surface of described integrated circuit
Spaced apart and with the plurality of metal level from described light source farthest described in another metal level direct
Contact.
According to one embodiment of present invention, wherein, described interconnection structure is arranged in described light source and institute
State between the first substrate, thus before described light is received by described photoelectric detector, described light passes
Described interconnection structure.
According to one embodiment of present invention, wherein, described interconnection structure includes: foot metal level,
And the first surface of described first substrate is spaced the first distance；Topmost metal level, with described first lining
The described first surface interval second distance at the end, described second distance is more than described first distance；And
Wherein, described bond pad groove most from described in the upper surface of described interconnection structure extends down through
Portion's metal level, and wherein, described bond pad directly contacts with described foot metal level.
According to one embodiment of present invention, wherein, described first substrate is arranged in described light source and institute
State between interconnection structure, thus described light is received by described photoelectric detector and is not passed through described before
Interconnection structure.
According to one embodiment of present invention, wherein, described interconnection structure includes: foot metal level,
And the first surface of described first substrate is spaced the first distance；Topmost metal level, with described first lining
The described first surface interval second distance at the end, described second distance is more than described first distance；And
Wherein, described bond pad groove extends up through described first substrate, through described interconnection structure
Lower surface and through described foot metal level, and wherein, described bond pad is with described
Topmost metal level directly contacts.
According to one embodiment of present invention, integrated circuit also includes: the second substrate, is arranged on described
Above first substrate and include the multiple logical devices being positioned on described second substrate, wherein, described
Interconnection structure is arranged between described first substrate and described second substrate.
According to one embodiment of present invention, wherein, described interconnection structure includes: the first interconnection structure,
It coupled to the described photoelectric detector on described first substrate；And second interconnection structure, be configured to by
Described logical device on described second substrate is electrically coupled to one another.
According to one embodiment of present invention, wherein, described first interconnection structure includes: with described
The first surface of one substrate is spaced the first foot metal level of the first distance；And serve as a contrast with described first
First topmost metal level of the described first surface interval second distance at the end, described second distance is more than
Described first distance；Wherein, described second interconnection structure includes: with the first table of described second substrate
Face is spaced the second foot metal level of the first distance；And with described first table of described second substrate
Second topmost metal level of interval, face second distance, described second distance is more than described first distance,
Wherein, described second topmost metal level to the most described first topmost metal level than to described first under
Portion's metal level is near；And wherein, described bond pad groove extend up through described first substrate,
Through described first interconnection structure and through described second topmost metal level, and wherein, institute
State bond pad directly to contact with described second foot metal level.
Embodiments of the invention additionally provide illuminated (FSI) sensor before one, including: image sensing
Device substrate, has and is configured to receive the first surface irradiated and second table relative with described first surface
Face, wherein, the array of photoelectric detector is arranged in described first table in described image sensor substrate
Between face and described second surface；Imageing sensor interconnection structure, adjacent described first surface, described
Imageing sensor interconnection structure includes multiple metal levels and the insulating barrier overlie one another in an alternating fashion,
Wherein, the first metal layer and the described first surface of the plurality of metal level are spaced the first vertical dimension,
Described first vertical dimension less than other each metal levels to described first surface other each vertically away from
From；And bond pad structure, spaced and described with the array of described photoelectric detector
Bond pad structure includes extending from the upper surface of described imageing sensor interconnection structure and terminating in connecing
Closing the bond pad groove at pad, wherein, described bond pad directly connects with described the first metal layer
Touch.
According to one embodiment of present invention, wherein, the lower sides of described bond pad groove is by
One apart from spaced apart, and the upper portion side wall of described bond pad groove is spaced apart by second distance, institute
State second distance more than described first distance.
According to one embodiment of present invention, wherein, described imageing sensor interconnection structure described absolutely
Edge layer is made up of low k dielectric, and described bond pad is by aluminum, copper or the compound of aluminum bronze
Make.
According to one embodiment of present invention, front illuminated sensor also includes: side wall spacer, by by institute
State the dielectric material system that the lateral wall of the bond pad sidewall corresponding with described low k dielectric separates
Become.
According to one embodiment of present invention, wherein, the one-tenth of the described dielectric material of described side wall spacer
Divide different from the composition of described low k dielectric.
According to one embodiment of present invention, wherein, described bond pad has adjacent described low k Jie
The lateral wall of the corresponding sidewall of electric material.
Embodiments of the invention additionally provide a kind of back-illuminated type (BSI) sensor, including: image sensing
Device substrate, has and is configured to receive the first surface irradiated and second table relative with described first surface
Face, wherein, the array of photoelectric detector is arranged in described first table in described image sensor substrate
Between face and described second surface；Imageing sensor interconnection structure, adjacent described second surface, and
Described imageing sensor interconnection structure includes multiple metal levels and the insulation overlie one another in an alternating fashion
Layer；CMOS interconnection structure, is positioned at above described imageing sensor interconnection structure, and described CMOS
Interconnection structure includes multiple metal levels and the insulating barrier overlie one another in an alternating fashion；CMOS substrate,
It is arranged on above described CMOS interconnection structure, and described CMOS substrate includes by described
Multiple cmos devices of CMOS interconnection structure interconnection；And bond pad structure, with described photoelectricity
The array of detector is spaced, and described bond pad structure includes from described imageing sensor
The described first surface of substrate extends through described image sensor substrate, through described imageing sensor
Interconnection structure and terminate in the bond pad groove at bond pad, wherein, described bond pad
It is arranged in described CMOS interconnection structure.
According to one embodiment of present invention, wherein, described CMOS interconnection structure includes with alternately
Multiple metal levels that mode overlies one another and insulating barrier, and wherein, described bond pad directly contacts
The first metal layer nearest from described CMOS substrate in the plurality of metal level.
According to one embodiment of present invention, wherein, described CMOS interconnection structure includes with alternately
Multiple metal levels that mode overlies one another and insulating barrier, and wherein, described bond pad directly contacts
The intermediate metal layer of the plurality of metal level, it is mutual that described intermediate metal layer is vertically set on described CMOS
Link in the first metal layer nearest from described CMOS substrate in structure and described CMOS interconnection structure
Second metal level farthest from described CMOS substrate between.
According to one embodiment of present invention, wherein, described CMOS interconnection structure includes with alternately
Multiple metal levels that mode overlies one another and insulating barrier, and wherein, described bond pad directly contacts
The metal level farthest from described CMOS substrate in described CMOS interconnection structure.
According to one embodiment of present invention, wherein, described bond pad groove includes having spaced apart
The upper bond pad recess of the angled sidewall of the first distance and there is spaced apart second distance
The lower bond pad recess of angled sidewall, described second distance is less than described first distance, and
And described upper bond pad recess and described lower bond pad recess meet at shoulder regions.
According to one embodiment of present invention, wherein, described CMOS interconnection structure includes with alternately
Multiple metal levels that mode overlies one another and insulating barrier, and wherein, the outward flange of described bond pad
Covered by the insulating barrier in described CMOS interconnection structure, and the core of described bond pad is not yet
Covered by the described insulating barrier in described CMOS interconnection structure.
Embodiments of the invention additionally provide a kind of three dimensional integrated circuits (3DIC), including: the first lining
The end, there is first surface and be positioned at the second surface above described first surface；Interconnection structure, is positioned at
Above described first substrate, and described interconnection structure include overlieing one another in an alternating fashion multiple
Metal level and insulating barrier, wherein, second surface described in the lower metal leafing in the plurality of metal level
Recently, second surface described in the upper metal leafing in the plurality of metal level is farthest, and middle gold
Belong to layer to be arranged between described upper metallization layer and described lower metal layer；Second substrate, is arranged on institute
State above interconnection structure, described second substrate have be positioned at the 3rd surface above described interconnection structure and
It is positioned at the 4th surface of described 3rd surface；And bond pad groove, from described first substrate
Described first surface in opening extend in described interconnection structure and terminate at bond pad,
Wherein, described bond pad directly contact with described upper metallization layer or with in described intermediate metal layer
One or more direct contacts.
According to one embodiment of present invention, wherein, described interconnection structure includes: the first interconnection structure,
It is positioned at above described first substrate and coupled to the semiconductor device in described first substrate, described
One interconnection structure includes the first subset of the plurality of metal level, wherein, in described first subset
One lower metal layer is nearest from described second surface, the first upper metal leafing in described first subset
Described second surface is farthest, and the first intermediate metal layer is arranged on described first upper metallization layer and institute
State between the first lower metal layer；And second interconnection structure, it is positioned at above described first interconnection structure
And coupleding to the semiconductor device of described second substrate, described second interconnection structure includes the plurality of
Second subset nonoverlapping with described first subset of metal level, wherein, in described second subset
3rd surface described in two lower metal leafing is nearest, the second upper metal leafing in described second subset
Described 3rd most portionafrom theasurface, and the second intermediate metal layer is arranged on described second upper metallization layer and institute
State between the second lower metal layer.
According to one embodiment of present invention, wherein, in described first upper metallization layer and described second
Portion's metal level ratio described first lower metal layer and described second lower metal thickness respectively, and described
Bond pad directly contact with described second upper metallization layer, described second lower metal layer or with institute
State the one or more direct contact in the second intermediate metal layer.
According to one embodiment of present invention, wherein, in described first upper metallization layer and described second
Portion's metal level ratio described first lower metal layer and described second lower metal thickness respectively, and described
Bond pad directly contact with described first upper metallization layer or with in described first intermediate metal layer
One or more direct contacts.
Foregoing has outlined the parts of some embodiments, those skilled in the art be may be better understood
The aspect of the present invention.It should be appreciated by those skilled in the art that they can readily use the present invention and make
Based on design or revise for realizing the purpose identical with in this introduced embodiment and/or realization
Other techniques of identical advantage and structure.Those skilled in the art are it should also be appreciated that the isomorphism such as this
Make without departing from the spirit and scope of the present invention and in the feelings without departing substantially from the spirit and scope of the present invention
Under condition, at this, they can make multiple change, replace and change.
Claims (10)
1. an integrated circuit (IC), including:
First substrate, including being configured to receive in a first direction the photoelectric detector of light from light source；
Interconnection structure, is positioned at above described first substrate, and described interconnection structure includes with alternately
Multiple metal levels that mode overlies one another and insulating barrier, wherein, a gold in the plurality of metal level
Belong to light source described in leafing nearest, and light source described in another metal leafing in the plurality of metal level
Farthest；And
Bond pad groove, the opening from the surface nearest from described light source of described integrated circuit prolongs
Extending in described interconnection structure and terminate at bond pad, wherein, described bond pad is with described
Integrated circuit described spaced and the institute farthest from described light source with the plurality of metal level
State another metal level directly to contact.
Integrated circuit the most according to claim 1, wherein, described interconnection structure is arranged in described
Between light source and described first substrate, thus before described light is received by described photoelectric detector, institute
State light through described interconnection structure.
Integrated circuit the most according to claim 2, wherein, described interconnection structure includes:
Foot metal level, and the first surface of described first substrate is spaced the first distance；
Topmost metal level, and the described first surface interval second distance of described first substrate, described
Second distance is more than described first distance；And
Wherein, described bond pad groove extends down through described from the upper surface of described interconnection structure
Topmost metal level, and wherein, described bond pad directly contacts with described foot metal level.
Integrated circuit the most according to claim 1, wherein, described first substrate is arranged in described
Between light source and described interconnection structure, thus described light is received by described photoelectric detector and is not had before
Through described interconnection structure.
Integrated circuit the most according to claim 4, wherein, described interconnection structure includes:
Foot metal level, and the first surface of described first substrate is spaced the first distance；
Topmost metal level, and the described first surface interval second distance of described first substrate, described
Second distance is more than described first distance；And
Wherein, described bond pad groove extends up through described first substrate, through described interconnection
The lower surface of structure and through described foot metal level, and wherein, described bond pad with
Described topmost metal level directly contacts.
Integrated circuit the most according to claim 4, also includes:
Second substrate, is arranged on above described first substrate and includes being positioned on described second substrate
Multiple logical devices, wherein, described interconnection structure is arranged in described first substrate and described second substrate
Between.
Integrated circuit the most according to claim 6, wherein, described interconnection structure includes:
First interconnection structure, coupled to the described photoelectric detector on described first substrate；And
Second interconnection structure, is configured to be electrically coupled to one another the described logical device on described second substrate.
8. illuminated (FSI) sensor before, including:
Image sensor substrate, have be configured to receive irradiate first surface and with described first surface
Relative second surface, wherein, the array of photoelectric detector is arranged in described image sensor substrate
Between described first surface and described second surface；
Imageing sensor interconnection structure, adjacent described first surface, described imageing sensor interconnection structure
Including the multiple metal levels overlie one another in an alternating fashion and insulating barrier, wherein, the plurality of metal
The first metal layer and the described first surface of layer are spaced the first vertical dimension, and described first vertical dimension is little
Other each vertical dimensions in other each metal levels to described first surface；And
Bond pad structure, spaced with the array of described photoelectric detector, and described joint
Pad structure includes extending from the upper surface of described imageing sensor interconnection structure and terminating in seam welding
The bond pad groove of Pan Chu, wherein, described bond pad directly contacts with described the first metal layer.
9. back-illuminated type (BSI) sensor, including:
Image sensor substrate, have be configured to receive irradiate first surface and with described first surface
Relative second surface, wherein, the array of photoelectric detector is arranged in described image sensor substrate
Between described first surface and described second surface；
Imageing sensor interconnection structure, adjacent described second surface, and the interconnection of described imageing sensor
Structure includes multiple metal levels and the insulating barrier overlie one another in an alternating fashion；
CMOS interconnection structure, is positioned at above described imageing sensor interconnection structure, and described CMOS
Interconnection structure includes multiple metal levels and the insulating barrier overlie one another in an alternating fashion；
CMOS substrate, is arranged on above described CMOS interconnection structure, and described CMOS substrate
Including the multiple cmos devices interconnected by described CMOS interconnection structure；And
Bond pad structure, spaced with the array of described photoelectric detector, and described joint
Pad structure includes that the described first surface from described image sensor substrate extends through described image and passes
Sensor substrate, through described imageing sensor interconnection structure and terminate in the joint at bond pad
Pad recess, wherein, described bond pad is arranged in described CMOS interconnection structure.
10. a three dimensional integrated circuits (3DIC), including:
First substrate, has first surface and is positioned at the second surface above described first surface；
Interconnection structure, is positioned at above described first substrate, and described interconnection structure includes with alternately
Multiple metal levels that mode overlies one another and insulating barrier, wherein, the bottom gold in the plurality of metal level
Belong to second surface described in leafing nearest, the second table described in the upper metal leafing in the plurality of metal level
Face is farthest, and intermediate metal layer is arranged between described upper metallization layer and described lower metal layer；
Second substrate, is arranged on above described interconnection structure, described second substrate have be positioned at described mutually
Even the 3rd surface of superstructure and the 4th surface being positioned at described 3rd surface；And
Bond pad groove, the opening from the described first surface of described first substrate extends to described
Interconnection structure is interior and terminates at bond pad, wherein, and described bond pad and described upper metal
Layer directly contacts or directly contacts with one or more in described intermediate metal layer.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201562184608P | 2015-06-25 | 2015-06-25 | |
| US62/184,608 | 2015-06-25 | ||
| US15/088,232 US10038026B2 (en) | 2015-06-25 | 2016-04-01 | Bond pad structure for bonding improvement |
| US15/088,232 | 2016-04-01 |
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| CN106298718A true CN106298718A (en) | 2017-01-04 |
| CN106298718B CN106298718B (en) | 2019-08-23 |
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|---|---|---|---|
| CN201610474165.1A Active CN106298718B (en) | 2015-06-25 | 2016-06-24 | Integrated circuit, sensor front-illuminated, backside-illuminated sensor and three dimensional integrated circuits |
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| Country | Link |
|---|---|
| US (5) | US10038026B2 (en) |
| CN (1) | CN106298718B (en) |
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| WO2020034152A1 (en) * | 2018-08-16 | 2020-02-20 | Yangtze Memory Technologies Co., Ltd. | Embedded pad structures of three-dimensional memory devices and fabrication methods thereof |
| WO2020172948A1 (en) * | 2019-02-27 | 2020-09-03 | 中芯集成电路（宁波）有限公司 | Cmos image sensor package module and forming method therefor, and camera device |
| CN112310135A (en) * | 2020-10-19 | 2021-02-02 | 锐芯微电子股份有限公司 | Sensor structure and method of forming a sensor structure |
| CN113644084A (en) * | 2021-08-06 | 2021-11-12 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
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Also Published As
| Publication number | Publication date |
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| TW201712846A (en) | 2017-04-01 |
| US10515995B2 (en) | 2019-12-24 |
| CN106298718B (en) | 2019-08-23 |
| US20200152675A1 (en) | 2020-05-14 |
| US20160379962A1 (en) | 2016-12-29 |
| US20180350857A1 (en) | 2018-12-06 |
| TWI613788B (en) | 2018-02-01 |
| US20220157864A1 (en) | 2022-05-19 |
| US11244981B2 (en) | 2022-02-08 |
| US11894410B2 (en) | 2024-02-06 |
| US20240162269A1 (en) | 2024-05-16 |
| US10038026B2 (en) | 2018-07-31 |
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