CN113644084B - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN113644084B
CN113644084B CN202110904012.7A CN202110904012A CN113644084B CN 113644084 B CN113644084 B CN 113644084B CN 202110904012 A CN202110904012 A CN 202110904012A CN 113644084 B CN113644084 B CN 113644084B
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layer
substrate
metal
back surface
hole
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CN113644084A (en
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叶国梁
胡胜
刘天建
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14632—Wafer-level processed structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1464—Back illuminated imager structures

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, wherein a groove and a through hole which penetrates from the bottom surface of the groove to the top surface of a metal interconnection structure are formed on the back surface of a substrate of a pad area, a first metal layer filled in the through hole is formed, and a pad structure is formed in the groove, so that the metal interconnection structure formed in a first device layer is connected through the pad structure and the first metal layer, the size of a chip can be further reduced, and the wiring complexity of the metal interconnection structure on the front surface of a first wafer is reduced.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a semiconductor device and a method of fabricating the same.
Background
The image sensor, as a core component of the image pickup apparatus, realizes an image capturing function by converting an optical signal into an electrical signal. Taking a CMOS image sensor (CMOS Image Sensors, CIS) as an example, it has advantages of low power consumption and high signal ratio, so that it is widely used in various fields.
In the conventional manufacturing process, after bonding the front surface of the pixel wafer and the carrier wafer, a bonding pad and a grid-shaped metal grid are formed on the substrate on the Back surface of the pixel wafer, and a Color Filter (Color Filter) matrix is formed in the grid of the metal grid.
And, through forming a deep trench penetrating the substrate in a large area on the back surface of the pixel wafer, and forming the bonding pad in the deep trench, the metal interconnection structure formed on the front surface of the pixel wafer can be connected out from the back surface of the pixel wafer through the bonding pad in the deep trench. However, since the deep trench occupies a large area and penetrates the substrate, the size of the substrate capable of forming the device structure is occupied, resulting in a decrease in chip size being disadvantageous; in addition, the metal interconnection structure on the front side of the pixel wafer is connected out from the back side of the pixel wafer through the bonding pad in the deep groove, so that the wiring of the metal interconnection structure on the front side of the pixel wafer is complicated to realize the electrical connection with the bonding pad, and the process difficulty is increased.
Therefore, how to further reduce the chip size and the wiring complexity of the metal interconnect structure on the front side of the pixel wafer is a problem that needs to be solved.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, which can further reduce the chip size and reduce the wiring complexity of a metal interconnection structure on the front surface of a first wafer.
In order to achieve the above object, the present invention provides a semiconductor device comprising:
Providing a substrate and a device layer formed on the front surface of the substrate, wherein a metal interconnection structure is formed in the device layer, the front surface and the back surface of the substrate are opposite surfaces, and the substrate comprises a device region and a bonding pad region;
forming a groove and a through hole penetrating from the bottom surface of the groove to the top surface of the metal interconnection structure on the back surface of the substrate of the pad area, wherein the back surface of the substrate, the groove and the surface of the through hole are covered with a first insulating medium layer in a conformal manner;
forming a first metal layer filled in the through hole, and forming a bonding pad structure in the groove, wherein the bonding pad structure is electrically connected with the metal interconnection structure through the first metal layer, and the first metal layer and the bonding pad structure are insulated from the substrate through the first insulating medium layer;
filling a second insulating dielectric layer in the groove, wherein the second insulating dielectric layer buries the pad structure;
flattening the second insulating dielectric layer and removing the first insulating dielectric layer with the thickness of the back surface part of the substrate of the device region, wherein the thickness of the first insulating dielectric layer positioned on the back surface of the substrate of the device region is smaller than that of the first insulating dielectric layer positioned on the back surface of the substrate of the bonding pad region;
And sequentially covering a second metal layer and a dielectric cap layer on the rest first insulating dielectric layer, and etching the dielectric cap layer and the second metal layer to form a metal grid layer and a shielding layer, wherein the metal grid layer is positioned on the first insulating dielectric layer of the device region, the shielding layer extends from the device region to the bonding pad region, and the shielding layer is in a step shape at the junction of the device region and the bonding pad region.
Optionally, forming a trench and a via penetrating from a bottom surface of the trench to a top surface of the metal interconnection structure on a substrate back surface of the pad region, and conformally covering the substrate back surface and the trench and the via surface with a first insulating medium layer, the steps including:
etching a part of the thickness of the substrate from the back surface of the substrate of the pad area to form a groove;
forming a first through hole on the bottom surface of the groove, wherein the first through hole penetrates through the substrate to expose the device layer;
forming a first insulating medium layer on the back surface of the substrate, the first through hole and the inner surface of the groove; the method comprises the steps of,
and etching the first insulating medium layer at the bottom surface of the first through hole and the device layer with partial thickness to form a second through hole exposing the metal interconnection structure, wherein the first through hole and the second through hole form the through hole.
Optionally, the first insulating medium layer includes a first oxide layer, a nitride layer and a second oxide layer which cover the back surface of the substrate, the trench, and the surface of the through hole in sequence.
Optionally, the step of planarizing the second insulating dielectric layer and removing the first insulating dielectric layer of the thickness of the substrate backside portion of the device region includes:
planarizing the second insulating dielectric layer of the pad region to the nitride layer;
and removing the second oxide layer and the nitride layer on the back surface of the device region substrate, and reserving at least part of the first oxide layer.
Optionally, the method for manufacturing a semiconductor device further includes:
and forming an opening in the second insulating medium layer, wherein the opening exposes the bonding pad structure.
The present invention also provides a semiconductor device including:
the semiconductor device comprises a substrate and a device layer formed on the front surface of the substrate, wherein a metal interconnection structure is formed in the device layer, the front surface and the back surface of the substrate are opposite surfaces, and the substrate comprises a device region and a bonding pad region; a groove is formed on the back surface of the substrate of the pad area, the groove is positioned in the substrate with partial thickness, a through hole is formed between the metal interconnection structure and the groove, the groove is communicated with the through hole, and the through hole exposes the metal interconnection structure;
The first metal layer is filled in the through hole and is electrically connected with the metal interconnection structure;
the pad structure is formed in the groove, is electrically connected with the first metal layer, and is covered with a first insulating medium layer along with the back surface of the substrate, the groove and the surface of the through hole, and the first metal layer and the pad structure are insulated with the substrate through the first insulating medium layer; the thickness of the first insulating medium layer positioned on the back surface of the device region substrate is smaller than that of the first insulating medium layer positioned on the back surface of the bonding pad region substrate;
the second insulating medium layer is filled in the groove, and an opening exposing the bonding pad structure is formed in the second insulating medium layer;
the shielding layer extends from the device region to the pad region, and the shielding layer is in a step shape at the junction of the device region and the pad region.
Optionally, the through hole comprises a first through hole and a second through hole which are sequentially formed between the groove and the metal interconnection structure, the first through hole penetrates through the substrate, and a first insulating medium layer is formed between the substrate of the inner surfaces of the first through hole and the groove and the first metal layer and the bonding pad structure; the second via penetrates the device layer through a portion of the thickness such that the second via exposes the metal interconnect structure.
Optionally, the semiconductor device further includes:
and the dielectric cap layer is formed on one surface of the metal grid layer and the shielding layer, which is far away from the substrate.
Optionally, the etching selectivity ratio of the materials of the metal grid layer and the shielding layer to the material of the dielectric cap layer is higher than that of tungsten to silicon oxide; and the surface roughness of the metal grid layer and the shielding layer is smaller than that of a structure formed by tungsten.
Optionally, the semiconductor device further comprises a second wafer bonded to a side of the device layer remote from the substrate.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. according to the manufacturing method of the semiconductor device, the groove for forming the bonding pad structure is formed in the first substrate with partial thickness, and the through hole for forming the first metal layer is formed between the groove and the metal interconnection structure, so that the metal interconnection structure formed in the first device layer (namely the metal interconnection structure positioned on the front surface of the first wafer) is connected through the bonding pad structure and the first metal layer, the chip size can be further reduced, and the wiring complexity of the metal interconnection structure positioned on the front surface of the first wafer is reduced.
2. According to the semiconductor device, the groove is formed in the first substrate with partial thickness, the through hole is formed between the groove and the metal interconnection structure, the bonding pad structure is formed in the groove, and the first metal layer is formed in the through hole, so that the metal interconnection structure formed in the first device layer (namely, the metal interconnection structure positioned on the front surface of the first wafer) is connected through the bonding pad structure and the first metal layer, the chip size can be further reduced, and the wiring complexity of the metal interconnection structure positioned on the front surface of the first wafer is reduced.
Drawings
Fig. 1 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 2a to 2i are schematic views of a device in the method of manufacturing a semiconductor device shown in fig. 1.
Wherein, the reference numerals of the figures 1-2 i are as follows:
11-a first substrate; 111-grooves; 112-a first through hole; 113-a second through hole; 12-a first device layer; 121-a metal interconnect structure; 13-a first insulating dielectric layer; 131-a first oxide layer; 132-a nitride layer; 133-a second oxide layer; 14-a first metal layer; 15-pad structure; 16-a second insulating medium layer; 17-a second metal layer; 171-a metal grid layer; 172-a shielding layer; 18-dielectric capping layer; 19-opening; 21-a second substrate; 22-second device layer.
Detailed Description
In order to make the objects, advantages and features of the present invention more apparent, the following more particular description of the semiconductor device and method of fabricating the same is provided. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. The meaning of "and/or" herein is either or both.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, referring to fig. 1, fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, where the method for manufacturing a semiconductor device includes:
step S1, providing a substrate and a device layer formed on the front side of the substrate, wherein a metal interconnection structure is formed in the device layer, the front side and the back side of the substrate are opposite surfaces, and the substrate comprises a device region and a bonding pad region;
s2, forming a groove and a through hole penetrating from the bottom surface of the groove to the top surface of the metal interconnection structure on the back surface of the substrate of the pad area, wherein the back surface of the substrate, the groove and the surface of the through hole are covered with a first insulating medium layer in a conformal manner;
S3, forming a first metal layer filled in the through hole, and forming a bonding pad structure in the groove, wherein the bonding pad structure is electrically connected with the metal interconnection structure through the first metal layer, and the first metal layer and the bonding pad structure are insulated from the substrate through the first insulating medium layer;
s4, filling a second insulating medium layer in the groove, wherein the second insulating medium layer buries the pad structure;
s5, flattening the second insulating medium layer and removing the first insulating medium layer with the thickness of the back surface part of the substrate of the device region, wherein the thickness of the first insulating medium layer positioned on the back surface of the substrate of the device region is smaller than that of the first insulating medium layer positioned on the back surface of the substrate of the bonding pad region;
step S6, sequentially covering a second metal layer and a dielectric cap layer on the rest first insulating dielectric layer, and etching the dielectric cap layer and the second metal layer to form a metal grid layer and a shielding layer, wherein the metal grid layer is positioned on the first insulating dielectric layer of the device region, the shielding layer extends from the device region to the bonding pad region, and the shielding layer is in a step shape at the junction of the device region and the bonding pad region.
The method for manufacturing the semiconductor device according to the present embodiment will be described in more detail with reference to fig. 2a to 2i, and fig. 2a to 2i are schematic longitudinal cross-sectional views of the semiconductor device. The embodiment shown in fig. 2a to 2i is exemplified by an image sensor using a 3D IC, but is not limited thereto.
According to step S1, a substrate and a device layer formed on the front side of the substrate are provided, wherein the substrate and the device layer form a first wafer. Referring to fig. 2a, in order to distinguish from the substrate and the device layer on the second wafer, the substrate and the device layer in the first wafer are defined as a first substrate 11 and a first device layer 12, the substrate and the device layer in the second wafer are defined as a second substrate 21 and a second device layer 22, and the first device layer 12 has a metal interconnection structure 121 formed therein, that is, the metal interconnection structure 121 is formed on the front surface of the first wafer.
The metal interconnect structure 121 may include a metal interconnect line and a pad electrically connected to the metal interconnect line, which may be exposed by the front side of the first device layer 12 (i.e., the side away from the first substrate 11).
Other functional structures may also be included in the first device layer 12, such as pixel arrays, transistors, or MEMS microstructures (e.g., diaphragm, electrode, etc. structures). The first wafer may be a device wafer, for example a pixel wafer comprising a pixel array of an image sensor, the kind of the first wafer being dependent on the function of the device to be finally fabricated. The first wafer may be a single-layer wafer structure, or may be a structure after bonding multiple layers of wafers, as shown in fig. 2a, where the first wafer is a single-layer wafer structure.
The portion of the first device layer 12 located between the first substrate 11 and the metal interconnection structure 121 may be an insulating material layer (not shown), for example, the insulating material layer may include a first oxide layer, a first nitride layer, and a second oxide layer formed in this order, the second oxide layer being in contact with the metal interconnection structure 121, and in particular, the second oxide layer being in contact with the metal interconnection line.
Conductive structures such as conductive plugs electrically connected to the metal interconnection lines may be further formed in the insulating material layer, so that the metal interconnection lines are electrically connected to the first substrate 11 through the conductive structures such as conductive plugs.
The first wafer may include a device region A2 and a pad region A1 surrounding the periphery of the device region A2.
In addition, the front side of the first wafer is bonded to a second wafer before the trench 111 is subsequently formed in the back side of the first substrate 11.
The second wafer may include a second substrate 21 and a second device layer 22 formed on the second substrate 21. The second wafer may be a logic wafer having CMOS circuitry formed therein; the second device layer 22 may include a MOS transistor, a resistor, a capacitor, a metal interconnect structure (not shown), and the like, and the metal interconnect structure in the second device layer 22 is electrically connected to the metal interconnect structure 121 in the first device layer 12. The second wafer may be a single-layer wafer structure or a multi-layer wafer bonded structure. Alternatively, the second wafer may be a carrier wafer, without the device function, on which the second device layer 22 is not formed.
A first bonding layer (not shown) may be formed on a side of the first device layer 12 away from the first substrate 11, and a second bonding layer (not shown) may be formed on the second wafer, and the first wafer and the second wafer may be bonded through the first bonding layer and the second bonding layer.
And, after bonding the first wafer and the second wafer, the first substrate 11 on the back surface of the first wafer may be thinned so that the thickness of the first substrate 11 on the back surface of the first wafer is thinned to a desired thickness.
According to step S2, referring to fig. 2a to 2d, a trench 111 and a via hole penetrating from the bottom surface of the trench 111 to the top surface of the metal interconnection structure 121 are formed on the back surface of the first substrate 11 of the pad area A1, and the back surface of the first substrate 11 and the surfaces of the trench 111 and the via hole are conformally covered with a first insulating medium layer 13.
The trench 111 is located in a part of the thickness of the first substrate 11, and the front surface and the back surface of the first substrate 11 are opposite surfaces.
Referring to fig. 2a, a partial thickness of the first substrate 11 may be etched from the back of the first substrate 11 of the pad region A1 to form the trench 111.
The step of forming the via hole between the trench 111 and the metal interconnection structure 121 and forming the first insulating dielectric layer 13 includes: first, as shown in fig. 2b, a first via 112 is formed on the bottom surface of the trench 111, where the first via 112 penetrates through the first substrate 11 to expose the first device layer 12, or the first via 112 may also penetrate through the first substrate 11 on the bottom surface of the trench 111 and through the first device layer 12 (for example, penetrate through the first oxide layer or penetrate through the first oxide layer and the first nitride layer) with a partial thickness between the first substrate 11 and the metal interconnection structure 121; then, as shown in fig. 2c, a first insulating dielectric layer 13 is formed on the inner surfaces of the first via 112 and the trench 111, the first insulating dielectric layer 13 also covering the back surface of the first substrate 11; next, as shown in fig. 2d, the first insulating dielectric layer 13 at the bottom of the first via 112 and the first device layer 12 between the first insulating dielectric layer 13 and the metal interconnection structure are etched to form a second via 113 exposing the metal interconnection structure 121, and the first via 112 and the second via 113 constitute the via.
Wherein the area of the cross section of the second through hole 113 may be smaller than or equal to the area of the cross section of the first through hole 112, and the area of the cross section of the first through hole 112 is smaller than the area of the bottom surface of the trench 111.
The material of the first insulating dielectric layer 13 includes at least one of silicon oxide and a high K dielectric with a dielectric constant K greater than 3.9. The first insulating dielectric layer 13 may be a stacked structure of at least two layers (e.g., a layer of silicon oxide and a layer of high-K dielectric). In this embodiment, as shown in fig. 2c, the first insulating dielectric layer 13 includes a first oxide layer 131, a nitride layer 132, and a second oxide layer 133 that sequentially cover the back surface of the first substrate 11, the trench 111, and the surface of the first via 112.
According to step S3, referring to fig. 2e, a first metal layer 14 filled in the via hole is formed, and a pad structure 15 is formed in the trench 111, wherein the pad structure 15 is electrically connected to the metal interconnection structure 121 through the first metal layer 14, and the first metal layer 14 and the pad structure 15 are insulated from the first substrate 11 through the first insulating dielectric layer 13.
Wherein the first metal layer 14 and the pad structure 15 may be formed simultaneously, and at this time, the materials of the first metal layer 14 and the pad structure 15 are the same; alternatively, the first metal layer 14 and the pad structure 15 are formed sequentially, and at this time, the materials of the first metal layer 14 and the pad structure 15 may be the same or different. The first metal layer 14 and the pad structure 15 are both made of metal materials, such as at least one of tungsten, aluminum, copper, gold, silver, and the like.
The first metal layer 14 and the first insulating dielectric layer 13 between the first substrate 11 on the side wall of the first through hole 112, the first metal layer 14 and the first insulating dielectric layer 13 between the first substrate 11 on the side wall of the second through hole 113, and the first device layer 12 (such as a first oxide layer or a first oxide layer and a first nitride layer) on the side wall of the second through hole 113 can block the metal in the first metal layer 14 from diffusing into the first substrate 11 and prevent voltage breakdown, and the first insulating dielectric layer 13 between the pad structure 15 and the first substrate 11 on the inner surface of the trench 111 can also block the metal in the pad structure 15 from diffusing into the first substrate 11 and prevent voltage breakdown.
The pad structure 15 may include a pad (not shown) and a metal wiring layer (not shown) electrically connected to the pad, and thus, a wiring structure of a desired metal wiring layer may be formed in the trench 111.
According to step S4, referring to fig. 2f, a second insulating dielectric layer 16 is filled in the trench 111, the second insulating dielectric layer 16 may fill the trench 111, a surface of the pad structure 15 away from the first metal layer 14 may be lower than a rear surface of the first substrate 11, and the second insulating dielectric layer 16 buries the pad structure 15.
According to step S5, continuing to refer to fig. 2f, planarizing the second insulating dielectric layer 16 and removing the first insulating dielectric layer 13 having a thickness of a portion of the back surface of the first substrate 11 of the device region A2, wherein the thickness of the first insulating dielectric layer 13 located on the back surface of the first substrate 11 of the device region A2 is smaller than the thickness of the back surface of the first substrate 11 located on the pad region A1.
If the first insulating dielectric layer 13 includes the first oxide layer 131, the nitride layer 132 and the second oxide layer 133, the step of planarizing the second insulating dielectric layer 16 and removing the first insulating dielectric layer 13 having a thickness of the back surface portion of the first substrate 11 of the device region A2 includes: firstly, planarizing the second insulating dielectric layer 16 of the pad area A1 and the first insulating dielectric layer 13 with partial thickness of the pad area A1 until the nitride layer 132, that is, taking the nitride layer 132 as a stop layer of the planarization process, removing the second oxide layer 133 on the back surface of the first substrate 11 of the pad area A1, wherein the top surface of the planarized second insulating dielectric layer 16 is flush with the top surface of the nitride layer 132 on the back surface of the first substrate 11 of the pad area A1; then, the second oxide layer 133 and the nitride layer 132 on the back surface of the first substrate 11 of the device region A2 are removed by chemical mechanical polishing or etching, and only a part of the thickness or the whole thickness of the first oxide layer 131 is remained, so as to avoid the nitride layer 132 from blocking light. Since the nitride layer 132 and the first oxide layer 131 remain on the back surface of the first substrate 11 of the pad region A1, and only the first oxide layer 131 remains on the back surface of the first substrate 11 of the device region A2, the thickness of the first insulating dielectric layer 13 on the back surface of the first substrate 11 of the device region A2 is smaller than the thickness on the back surface of the first substrate 11 of the pad region A1.
According to step S6, referring to fig. 2g to 2h, a second metal layer 17 and a dielectric cap layer 18 are sequentially covered on the remaining first insulating dielectric layer 13, the dielectric cap layer 18 and the second metal layer 17 are etched to form a metal grid layer 171 and a shielding layer 172, the metal grid layer 171 is located on the first insulating dielectric layer 13 of the device area A2, the shielding layer 172 extends from the device area A2 to the pad area A1, and the shielding layer 172 is in a step shape at the junction of the device area A2 and the pad area A1.
As shown in fig. 2g, the second metal layer 17 and the dielectric cap 18 extend from the first oxide layer 131 of the device region A2 to the nitride layer 132 of the pad region A1, and the dielectric cap 18 is etched to form a pattern exposing the second metal layer 17; referring to fig. 2h, the second metal layer 17 is etched to remove the metal grid layer 171 on the first oxide layer 131 of the device region A2 and the shielding layer 172 extending from the first oxide layer 131 of the device region A2 to the nitride layer 132 of the pad region A1.
In addition, the method for manufacturing the semiconductor device further comprises the following steps: a passivation layer (not shown) is formed on sidewalls of the metal grid layer 171 and the shielding layer 172 for preventing moisture, etc., and the passivation layer may further bury the dielectric cap layer 18, the remaining first insulating dielectric layer 13, and the planarized second insulating dielectric layer 16.
The manufacturing method of the semiconductor device further comprises the following steps: openings 19 are formed in the passivation layer and the second insulating medium layer 16, the openings 19 exposing the pad structures 15, as shown in fig. 2i, the openings 19 exposing a portion of the surface of the pad structures 15 away from the first metal layer 14, so that the metal interconnect structures 121 on the front side of the first wafer are connected out through the pad structures 15.
The shielding layer 172 is configured to block light from entering the first wafer at the junction of the device area A2 and the pad area A1, and may be used for heat dissipation; the metal grid layer 171 is distributed in a grid shape, and a filter layer (not shown) may be formed in the grid.
The second metal layer 17 is made of a metal material, for example, at least one of tungsten, aluminum, copper, gold, silver, etc., and the dielectric cap layer 18 is made of at least one of an insulating material such as silicon oxide, silicon oxynitride, silicon nitride, silicon oxycarbide, etc.
The etching selectivity ratio of the material of the second metal layer 17 to the material of the dielectric cap layer 18 is higher than that of tungsten to silicon oxide, and the surface roughness of the second metal layer 17 is smaller than that of a structure formed by tungsten. For example, the material of the second metal layer 17 may be aluminum, and the etching selectivity ratio of aluminum to silicon oxide is higher than that of tungsten to silicon oxide, and the surface roughness of the second metal layer 17 formed with aluminum is smaller than that of a structure formed with tungsten.
As is apparent from the above-described method for manufacturing a semiconductor device, the present invention forms the via hole between the trench 111 and the metal interconnection structure 121 by forming the trench 111 in the first substrate 11 having a partial thickness, and forms the pad structure 15 in the trench 111 and the first metal layer 14 in the via hole, so that the metal interconnection structure 121 formed in the first device layer 12 (i.e., the metal interconnection structure 121 located on the front surface of the first wafer) is connected through the pad structure 15 and the first metal layer 14. Compared with the existing semiconductor device structure in which deep trenches penetrating through the substrate are formed on the back surface of the pixel wafer (the region where the deep trenches in the substrate with the whole thickness are located cannot form a device structure any more) and the semiconductor device structure in which the bonding pads are formed in the deep trenches, the trench 111 for forming the bonding pad structure 15 occupies only part of the thickness of the first substrate 11, so that the device structure can be formed in the first substrate 11 between the trench 111 and the first device layer 12, and the chip size can be further reduced; in addition, compared with the existing semiconductor device structure in which the metal interconnection structure on the front side of the pixel wafer is connected only through the bonding pad, since the through hole in the invention directly penetrates into the first device layer 12 from the first substrate 11, the electrical connection between the bonding pad structure 15 and the metal interconnection structure 121 is realized only through the first metal layer 14 in the through hole, and the wiring complexity of the metal interconnection structure 121 is reduced because the wiring structure of the metal interconnection structure 121 is not complicated, and the required wiring structure can be formed in the groove 111 due to the bonding pad structure 15, which is equivalent to transferring part of the wiring structure in the metal interconnection structure 121 into the groove 111 on the back side of the first substrate 11 through the first metal layer 14, thereby further reducing the wiring complexity of the metal interconnection structure 121.
In order to ensure the electrical connection and disconnection performance of the pad structure 15, the thickness of the pad structure 15 is greater than the thicknesses of the metal grid layer 171 and the shielding layer 172, and the pad structure 15 is fabricated in the trench 111 on the back surface of the first substrate 11, so that the uneven height of the back surface of the semiconductor device caused by directly forming the pad structure 15 on the back surface of the first substrate 11 can be avoided, and the problem of uneven surface of the filter layer subsequently covering the back surface of the semiconductor device can be avoided.
In addition, since the pixel size is reduced, the number of pixels is increased, and the thickness of the metal grid layer is increased, there is a trend in the current semiconductor technology. If the thickness of the metal grid layer 171 in the semiconductor device is required to be large, and when the dielectric cap layer 18 is used as a mask to etch the second metal layer 17 to form the metal grid layer 171, if the etching selectivity of the material of the second metal layer 17 to the material of the dielectric cap layer 18 is low, for example, the material of the second metal layer 17 is tungsten and the material of the dielectric cap layer 18 is silicon oxide (the etching selectivity of the two is low), the dielectric cap layer 18 is also rapidly etched and removed (the thickness is reduced), and then the etching of the second metal layer 17 can be completed by the dielectric cap layer 18 with a large thickness, so that the process of forming the dielectric cap layer 18 is improved, the process difficulty of etching the second metal layer 17 is also improved, and the regularity of the morphology of the formed metal grid layer 171 is reduced. Therefore, the etching selectivity ratio of the material of the second metal layer 17 to the material of the dielectric cap layer 18 is higher than that of tungsten to silicon oxide, so that the process difficulty of forming the dielectric cap layer 18 and forming the metal grid layer 171 with a large thickness is reduced, and the shape regularity of the metal grid layer 171 is improved.
Also, when the material of the second metal layer 17 is tungsten, the surface of the metal layer 17 formed by using a Chemical Vapor Deposition (CVD) is very rough, resulting in poor uniformity of the height of the metal grid layer 171 formed, and thus, uneven surface of a filter layer subsequently coated on the back surface of the semiconductor device, resulting in poor uniformity of imaging after light is irradiated on the filter layer, and affecting optical performance. Accordingly, the surface roughness of the second metal layer 17 formed in the present invention is smaller than that of a structure formed using tungsten, so that the uniformity of the height of the metal grid layer 171 is improved, and thus the optical performance is improved.
Based on the same inventive concept, an embodiment of the present invention provides a semiconductor device including: the semiconductor device comprises a substrate and a device layer formed on the front surface of the substrate, wherein a metal interconnection structure is formed in the device layer, the front surface and the back surface of the substrate are opposite surfaces, and the substrate comprises a device region and a bonding pad region; a groove is formed on the back surface of the substrate of the pad area, the groove is positioned in the substrate with partial thickness, a through hole is formed between the metal interconnection structure and the groove, the groove is communicated with the through hole, and the through hole exposes the metal interconnection structure; the first metal layer is filled in the through hole and is electrically connected with the metal interconnection structure; the bonding pad structure is formed in the groove, the bonding pad structure is electrically connected with the first metal layer, the back surface of the substrate, the groove and the surface of the through hole are covered with a first insulating medium layer in a conformal manner, and the first metal layer and the bonding pad structure are insulated from the substrate through the first insulating medium layer; the thickness of the first insulating medium layer positioned on the back surface of the device region substrate is smaller than that of the first insulating medium layer positioned on the back surface of the bonding pad region substrate; the second insulating medium layer is filled in the groove, and an opening exposing the bonding pad structure is formed in the second insulating medium layer; the shielding layer extends from the device region to the pad region, and the shielding layer is in a step shape at the junction of the device region and the pad region.
The semiconductor device provided in this embodiment is described in detail below with reference to fig. 2 i. Fig. 2i is also a schematic longitudinal cross-sectional view of the semiconductor device. The embodiment shown in fig. 2i is exemplified by an image sensor using a 3D IC, but is not limited thereto.
The substrate and the device layer formed on the front surface of the substrate form a first wafer. In order to distinguish between the substrate and the device layer on the second wafer, the substrate and the device layer in the first wafer are defined as a first substrate 11 and a first device layer 12, the substrate and the device layer in the second wafer are defined as a second substrate 21 and a second device layer 22, and the first device layer 12 has a metal interconnection structure 121 formed therein, i.e. the metal interconnection structure 121 is formed on the front surface of the first wafer.
The metal interconnect structure 121 may include a metal interconnect line and a pad electrically connected to the metal interconnect line, which may be exposed by the front side of the first device layer 12 (i.e., the side away from the first substrate 11).
Other functional structures may also be included in the first device layer 12, such as pixel arrays, transistors, or MEMS microstructures (e.g., diaphragm, electrode, etc. structures). The first wafer may be a device wafer, for example a pixel wafer comprising a pixel array of an image sensor, the kind of the first wafer being dependent on the function of the device to be finally fabricated. The first wafer may be a single-layer wafer structure, or may be a structure after bonding multiple layers of wafers, as shown in fig. 2i, where the first wafer is a single-layer wafer structure.
The portion of the first device layer 12 located between the first substrate 11 and the metal interconnection structure 121 may be an insulating material layer (not shown), for example, the insulating material layer may include a first oxide layer, a first nitride layer, and a second oxide layer formed in this order, the second oxide layer being in contact with the metal interconnection structure 121, and in particular, the second oxide layer being in contact with the metal interconnection line.
Conductive structures such as conductive plugs electrically connected to the metal interconnection lines may be further formed in the insulating material layer, so that the metal interconnection lines are electrically connected to the first substrate 11 through the conductive structures such as conductive plugs.
The first wafer may include a device region A2 and a pad region A1 surrounding the periphery of the device region A2.
In addition, the semiconductor device further includes a second wafer bonded to a side of the first device layer 12 remote from the first substrate 11.
The second wafer may include a second substrate 21 and a second device layer 22 formed on the second substrate 21. The second wafer may be a logic wafer having CMOS circuitry formed therein; the second device layer 22 may include a MOS transistor, a resistor, a capacitor, a metal interconnect structure (not shown), and the like, and the metal interconnect structure in the second device layer 22 is electrically connected to the metal interconnect structure 121 in the first device layer 12. The second wafer may be a single-layer wafer structure or a multi-layer wafer bonded structure. Alternatively, the second wafer may be a carrier wafer, without the device function, on which the second device layer 22 is not formed.
A first bonding layer (not shown) may be formed on a surface of the first device layer 12 away from the first substrate 11, and a second bonding layer (not shown) may be formed on the second wafer, where the first wafer and the second wafer are bonded through the first bonding layer and the second bonding layer.
A groove (not shown) is formed in the back surface of the first substrate 11 of the pad region A1, and the groove is located in the first substrate 11 of a partial thickness, the front surface and the back surface of the first substrate 11 being opposite surfaces.
A via (not shown) is formed between the metal interconnection structure 121 and the trench, the trench communicates with the via, and the via exposes the metal interconnection structure 121.
The via hole may include a first via hole (not shown) and a second via hole (not shown) sequentially formed between the trench and the metal interconnection structure 121, the first via hole being connected to the trench and penetrating the first substrate 11, or the first via hole may penetrate the first substrate 11 of the trench bottom surface and penetrate the first device layer 12 (for example, penetrate the first oxide layer, or penetrate the first oxide layer and the first nitride layer) located at a partial thickness between the first substrate 11 and the metal interconnection structure 121; the second via penetrates a portion of the thickness of the first device layer 12 such that the second via exposes the metal interconnect structure 121.
In the pad area A1, the groove is correspondingly communicated with the position of the through hole.
The area of the cross section of the second through hole may be smaller than or equal to the area of the cross section of the first through hole, and the area of the cross section of the first through hole is smaller than the area of the bottom surface of the groove.
The first metal layer 14 is filled in the via hole, and the first metal layer 14 is electrically connected to the metal interconnection structure 121.
The pad structure 15 is formed in the trench, and the pad structure 15 is electrically connected to the first metal layer 14.
The pad structure 15 may include a pad (not shown) and a metal wiring layer (not shown) electrically connected to the pad, and thus, a wiring structure of a desired metal wiring layer may be formed in the trench.
The materials of the first metal layer 14 and the pad structure 15 may be the same or different. The first metal layer 14 and the pad structure 15 are both made of metal materials, such as at least one of tungsten, aluminum, copper, gold, silver, and the like.
The back surface of the first substrate 11, the grooves and the through hole surfaces are covered with a first insulating medium layer 13 in a conformal manner, and the first metal layer 14 and the pad structure 15 are insulated from the first substrate 11 through the first insulating medium layer 13; the thickness of the first insulating dielectric layer 13 on the back surface of the first substrate 11 in the device region A2 is smaller than the thickness of the first substrate 11 on the back surface of the pad region A1.
The second via penetrates through the first insulating dielectric layer 13 at the bottom of the first via and the first device layer 12 between the first insulating dielectric layer 13 and the metal interconnection structure 121 to expose the metal interconnection structure 121.
The material of the first insulating dielectric layer 13 includes at least one of silicon oxide and a high K dielectric with a dielectric constant K greater than 3.9. The first insulating dielectric layer 13 may be a stacked structure of at least two layers (e.g., a layer of silicon oxide and a layer of high-K dielectric).
The first insulating dielectric layer 13 on the surfaces of the trench and the via hole may include a first oxide layer 131, a nitride layer 132, and a second oxide layer 133 sequentially covering the trench, the first via hole surface in a conformal manner. The first insulating dielectric layer 13 on the back surface of the first substrate 11 of the pad region A1 may include the nitride layer 132 and the first oxide layer 131, and the first insulating dielectric layer 13 on the back surface of the first substrate 11 of the device region A2 may include the first oxide layer 131 such that the thickness of the first insulating dielectric layer 13 on the back surface of the first substrate 11 of the device region A2 is smaller than the thickness on the back surface of the first substrate 11 of the pad region A1.
The first metal layer 14 and the first insulating dielectric layer 13 between the first substrate 11 of the first via sidewall, the first metal layer 14 and the first insulating dielectric layer 13 between the first substrate 11 of the second via sidewall, the first device layer 12 of the second via sidewall (e.g., a first oxide layer, or a first oxide layer and a first nitride layer) can block the metal in the first metal layer 14 from diffusing into the first substrate 11 and prevent voltage breakdown, and the first insulating dielectric layer 13 between the pad structure 15 and the first substrate 11 of the trench inner surface can also block the metal in the pad structure 15 from diffusing into the first substrate 11 and prevent voltage breakdown.
The second insulating dielectric layer 16 is filled in the trench, and an opening 19 exposing the pad structure 15 is formed in the second insulating dielectric layer 16, and a surface of the pad structure 15 away from the first metal layer 14 may be lower than a back surface of the first substrate 11. The top surface of the second insulating dielectric layer 16 is flush with the top surface of the nitride layer 132 on the back surface of the first substrate 11 in the pad area A1.
The metal grid layer 171 is formed on the first insulating dielectric layer 13 on the back surface of the first substrate 11 of the device region A2. In this embodiment, the metal grid layer 171 is located on the first oxide layer 131.
The shielding layer 172 extends from the device region A2 to the pad region A1, and the shielding layer 172 is stepped at a junction between the device region A2 and the pad region A1. In this embodiment, the shielding layer 172 extends from the first oxide layer 131 of the device region A2 to the nitride layer 132 of the pad region A1.
The semiconductor device further includes a dielectric cap layer 18 formed on the side of the metal grid layer 171 and the shielding layer 172 remote from the first substrate 11.
In addition, passivation layers (not shown) may be formed on sidewalls of the metal grid layer 171 and the shielding layer 172 for preventing moisture, etc., the passivation layers may further bury the dielectric cap layer 18, the first insulating dielectric layer 13, and the second insulating dielectric layer 16 therein, the openings 19 are located in the passivation layers and the second insulating dielectric layer 16, and the openings 19 expose a portion of the surface of the pad structure 15 away from the first metal layer 14 so that the metal interconnection structure 121 on the front side of the first wafer is connected through the pad structure 15.
The shielding layer 172 is configured to block light from entering the first wafer at the junction of the device area A2 and the pad area A1, and may be used for heat dissipation; the metal grid layer 171 is distributed in a grid shape, a filter layer (not shown) may be formed in the grid, and the filter layer may bury the metal grid layer 171 and the shielding layer 172.
The metal grid layer 171 and the shielding layer 172 are made of a metal material, for example, at least one of tungsten, aluminum, copper, gold, silver, etc., and the dielectric cap layer 18 is made of at least one of an insulating material such as silicon oxide, silicon oxynitride, silicon nitride, silicon oxycarbide, etc.
The etch selectivity ratio of the material of the metal grid layer 171 and the shielding layer 172 to the material of the dielectric cap layer 18 is higher than that of tungsten to silicon oxide, and the surface roughness of the metal grid layer 171 and the shielding layer 172 is smaller than that of a structure formed by tungsten. For example, the material of the metal grid layer 171 and the shielding layer 172 may be aluminum, and the etching selectivity ratio of aluminum to silicon oxide is higher than that of tungsten to silicon oxide, and the surface roughness of the metal grid layer 171 and the shielding layer 172 formed of aluminum is smaller than that of a structure formed of tungsten.
As is known from the structure of the semiconductor device described above, since the trench for forming the pad structure 15 is formed in the first substrate 11 having a partial thickness, the via hole for forming the first metal layer 14 is formed between the trench and the metal interconnection structure 121, so that the metal interconnection structure 121 formed in the first device layer 12 (i.e., the metal interconnection structure 121 located on the front surface of the first wafer) is connected through the pad structure 15 and the first metal layer 14. Compared with the existing semiconductor device structure in which a deep trench penetrating through a substrate is formed on the back surface of a pixel wafer (the region where the deep trench in the substrate with the whole thickness is located cannot form a device structure any more) and a bonding pad is formed in the deep trench, the trench for forming the bonding pad structure 15 occupies only part of the thickness of the first substrate 11, so that a device structure can be formed in the first substrate 11 between the trench and the first device layer 12, and the chip size can be further reduced; in addition, compared with the existing semiconductor device structure in which the metal interconnection structure on the front side of the pixel wafer is connected only through the bonding pad, since the through hole in the present invention directly penetrates from the first substrate 11 to the first device layer 12, the electrical connection between the bonding pad structure 15 and the metal interconnection structure 121 is only realized through the first metal layer 14 located in the through hole, and the wiring complexity of the metal interconnection structure 121 is reduced because the wiring structure of the metal interconnection structure 121 is not complicated, and the required wiring structure can be formed in the groove due to the fact that the wiring structure of part of the metal interconnection structure 121 is transferred into the groove on the back side of the first substrate 11 through the first metal layer 14, thereby further reducing the wiring complexity of the metal interconnection structure 121.
In order to ensure the electrical connection and other performances of the pad structure 15, the thickness of the pad structure 15 is greater than the thicknesses of the metal grid layer 171 and the shielding layer 172, and the pad structure 15 is located in the groove on the back surface of the first substrate 11 in the present invention, so that the problem of uneven height of the back surface of the semiconductor device caused by directly forming the pad structure 15 on the back surface of the first substrate 11 can be avoided, and the problem of uneven surface of the filter layer subsequently covering the back surface of the semiconductor device can be avoided.
In addition, since the pixel size is reduced, the number of pixels is increased, and the thickness of the metal grid layer is increased, there is a trend in the current semiconductor technology. If the thickness of the metal grid layer 171 in the semiconductor device is required to be large, and if the etching selectivity of the material of the metal grid layer 171 to the material of the dielectric cap layer 18 is low when the dielectric cap layer 18 is used as a mask for etching to form the metal grid layer 171, for example, the material of the metal grid layer 171 is tungsten and the material of the dielectric cap layer 18 is silicon oxide (the etching selectivity of the two is low), the dielectric cap layer 18 is also rapidly etched and removed (the thickness is reduced) when the metal grid layer 171 is formed by etching, and the dielectric cap layer 18 with a large thickness is required to form the metal grid layer 171, so that the process difficulty of forming the dielectric cap layer 18 and etching to form the metal grid layer 171 is increased, and the regularity of the morphology of the etched metal grid layer 171 is reduced. Therefore, the etching selectivity ratio of the material of the metal grid layer 171 to the material of the dielectric cap layer 18 is higher than that of tungsten to silicon oxide, so that the process difficulty of forming the dielectric cap layer 18 and forming the metal grid layer 171 with a large thickness is reduced, and the shape regularity of the metal grid layer 171 is improved.
Also, since the surface of the material of the metal grid layer 171 formed by using a Chemical Vapor Deposition (CVD) process is very rough when the material of the metal grid layer 171 is tungsten, the uniformity of the height of the formed metal grid layer 171 is poor, and thus the surface of the filter layer subsequently coated on the back surface of the semiconductor device is uneven, thereby causing deterioration of uniformity of imaging after light is irradiated on the filter layer, and affecting optical performance. Accordingly, the surface roughness of the metal grid layer 171 formed in the present invention is smaller than that of a structure formed using tungsten, so that the uniformity of the height of the metal grid layer 171 is improved, and thus the optical performance is improved.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising:
providing a substrate and a device layer formed on the front surface of the substrate, wherein a metal interconnection structure is formed in the device layer, the front surface and the back surface of the substrate are opposite surfaces, and the substrate comprises a device region and a bonding pad region;
Forming a groove and a through hole penetrating from the bottom surface of the groove to the top surface of the metal interconnection structure on the back surface of the substrate of the pad region, wherein the back surface of the substrate, the groove and part of the surfaces of the through hole are covered with a first insulating medium layer in a conformal manner;
forming a first metal layer filled in the through hole, and forming a bonding pad structure in the groove, wherein the bonding pad structure is electrically connected with the metal interconnection structure through the first metal layer, and the first metal layer and the bonding pad structure are insulated from the substrate through the first insulating medium layer;
filling a second insulating dielectric layer in the groove, wherein the second insulating dielectric layer buries the pad structure;
flattening the second insulating dielectric layer and removing the first insulating dielectric layer with the thickness of the back surface part of the substrate of the device region, wherein the thickness of the first insulating dielectric layer positioned on the back surface of the substrate of the device region is smaller than that of the first insulating dielectric layer positioned on the back surface of the substrate of the bonding pad region;
and sequentially covering a second metal layer and a dielectric cap layer on the rest first insulating dielectric layer, and etching the dielectric cap layer and the second metal layer to form a metal grid layer and a shielding layer, wherein the metal grid layer is positioned on the first insulating dielectric layer of the device region, the shielding layer extends from the device region to the bonding pad region, and the shielding layer is in a step shape at the junction of the device region and the bonding pad region.
2. The method of manufacturing a semiconductor device according to claim 1, wherein a trench and a via hole penetrating from a bottom surface of the trench to a top surface of the metal interconnection structure are formed on a substrate back surface of the pad region, and the substrate back surface and the trench, the via hole portion surfaces are conformally covered with a first insulating dielectric layer, comprising:
etching a part of the thickness of the substrate from the back surface of the substrate of the pad area to form a groove;
forming a first through hole on the bottom surface of the groove, wherein the first through hole penetrates through the substrate to expose the device layer;
forming a first insulating medium layer on the back surface of the substrate, the first through hole and the inner surface of the groove; the method comprises the steps of,
and etching the first insulating medium layer at the bottom surface of the first through hole and the device layer with partial thickness to form a second through hole exposing the metal interconnection structure, wherein the first through hole and the second through hole form the through hole.
3. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating dielectric layer includes a first oxide layer, a nitride layer, and a second oxide layer which cover the back surface of the substrate and the surfaces of the trench and the via portion in this order.
4. The method of manufacturing a semiconductor device according to claim 3, wherein the step of planarizing the second insulating dielectric layer and removing the first insulating dielectric layer of the thickness of the substrate back surface portion of the device region comprises:
planarizing the second insulating dielectric layer of the pad region to the nitride layer;
and removing the second oxide layer and the nitride layer on the back surface of the device region substrate, and reserving at least part of the first oxide layer.
5. The method for manufacturing a semiconductor device according to claim 1, wherein the method for manufacturing a semiconductor device further comprises:
and forming an opening in the second insulating medium layer, wherein the opening exposes the bonding pad structure.
6. A semiconductor device, comprising:
the semiconductor device comprises a substrate and a device layer formed on the front surface of the substrate, wherein a metal interconnection structure is formed in the device layer, the front surface and the back surface of the substrate are opposite surfaces, and the substrate comprises a device region and a bonding pad region; a groove is formed on the back surface of the substrate of the pad area, the groove is positioned in the substrate with partial thickness, a through hole is formed between the metal interconnection structure and the groove, the groove is communicated with the through hole, and the through hole exposes the metal interconnection structure;
The first metal layer is filled in the through hole and is electrically connected with the metal interconnection structure;
the pad structure is formed in the groove, is electrically connected with the first metal layer, and is covered with a first insulating medium layer along with the back surface of the substrate, the groove and the through hole part surface, and the first metal layer and the pad structure are insulated with the substrate through the first insulating medium layer; the thickness of the first insulating medium layer positioned on the back surface of the device region substrate is smaller than that of the first insulating medium layer positioned on the back surface of the bonding pad region substrate;
the second insulating medium layer is filled in the groove, and an opening exposing the bonding pad structure is formed in the second insulating medium layer;
the shielding layer extends from the device region to the pad region, and the shielding layer is in a step shape at the junction of the device region and the pad region.
7. The semiconductor device of claim 6, wherein the via includes a first via and a second via formed in sequence between the trench and the metal interconnect structure, the first via penetrating the substrate, and a first insulating dielectric layer formed between the substrate and the first metal layer and the pad structure at an inner surface of the first via and the trench; the second via penetrates the device layer through a portion of the thickness such that the second via exposes the metal interconnect structure.
8. The semiconductor device according to claim 6, wherein the semiconductor device further comprises:
and the dielectric cap layer is formed on one surface of the metal grid layer and the shielding layer, which is far away from the substrate.
9. The semiconductor device of claim 8, wherein an etch selectivity ratio of a material of the metal grid layer and the blocking layer to a material of the dielectric cap layer is higher than an etch selectivity ratio of tungsten to silicon oxide; and the surface roughness of the metal grid layer and the shielding layer is smaller than that of a structure formed by tungsten.
10. The semiconductor device of claim 6, further comprising a second wafer bonded to a side of the device layer remote from the substrate.
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