CN108417594B - Interconnection process method of back-illuminated CMOS image sensor structure - Google Patents

Interconnection process method of back-illuminated CMOS image sensor structure Download PDF

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CN108417594B
CN108417594B CN201810164170.1A CN201810164170A CN108417594B CN 108417594 B CN108417594 B CN 108417594B CN 201810164170 A CN201810164170 A CN 201810164170A CN 108417594 B CN108417594 B CN 108417594B
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王伟军
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Shanghai IC R&D Center Co Ltd
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    • H01L27/14601—Structural or functional details thereof
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Abstract

The invention discloses an interconnection process method of a back-illuminated CMOS image sensor structure, which comprises the following steps: providing a bonded back-illuminated CMOS image sensor silicon wafer, forming a second dielectric layer on the back of a silicon wafer substrate, carrying out photoetching and etching patterning processes of a through hole, filling a BARC in the through hole, carrying out photoetching and etching processes of a back channel and removing photoresist to form a side wall of a back channel structure, and filling a metal material in the back channel structure to form a pin pattern. According to the invention, through adjusting the forming sequence of the through hole and the back channel structure, the relevant steps of photoetching can be carried out on a plane, and the photoetching process effects such as exposure and the like can be improved; the process is favorable for improving the photoresist removing residue, so that the damage of the photoresist removing to the surface of the metal interconnection layer for a long time can be reduced, and the reliability of electric connection is improved.

Description

Interconnection process method of back-illuminated CMOS image sensor structure
Technical Field
The invention relates to the technical field of semiconductor manufacturing processes, in particular to an interconnection process method of a back-illuminated CMOS image sensor structure.
Background
In the past decade, with the popularization and upgrading of consumer electronics, image sensors have been widely used and their performance has been greatly improved. Currently, there are two main types of image sensors: complementary Metal Oxide Semiconductor (CMOS) and Charge Coupled Device (CCD), both of which use the principle of silicon photoelectric effect in light detection, differ in the way in which the photo-generated charges are read out from the pixels: the CCD transfers output charges through vertical and horizontal CCDs, and the voltage of a CMOS Image Sensor (CIS) is read out by row-column decoding similar to DRAM memory. Compared with the CCD, the CIS has advantages of high integration level, low power consumption, compatibility with an integrated circuit manufacturing process, and the like, and thus its share is steadily increasing.
The CMOS image sensor mainly comprises an image sensing unit array, a row driver, a column driver, a time sequence control logic, an AD converter, a data output interface, a control interface and the like. Semiconductor processes are used to form image sensing cells (photodiodes), row and column drivers, and other control circuitry in the sensor array. To collect the color pixels, color filters are also placed on the image sensitive cells. In order to reduce the pixel size and improve the resolution, the CIS technology has undergone the development from front-illuminated (FSI) to back-illuminated (BSI). At present, the BSI CIS has become a mainstream technology, and can realize the pixel size of 1.4-1.1 μm. To form the BSI CIS, a semiconductor process is performed on the back surface of the bonded silicon wafer and electrical connection is achieved. In the related semiconductor process flow, the patterning of a larger size, a deeper structure and a complex film layer is involved, which brings certain difficulties to the related process steps.
At present, research on the BSI CIS is relatively deep, which mainly starts from various aspects such as structure design, performance improvement, material selection, and the like, and the improvement on the device structure often affects the realized specific process. A method for specifically configuring bonding pads in an interconnect structure is proposed in U.S. patent No. 9165970, but it does not relate to the implementation of a specific process in detail, nor does it describe the process implementation of a conventional BSI CIS interconnect structure too much.
Therefore, a reasonable process flow needs to be provided for specific structural features of BSI CIS back-end interconnection, so as to reduce the difficulty in process implementation and improve the reliability of the process.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned drawbacks of the prior art, and provides an interconnection process for a backside illuminated CMOS image sensor structure.
In order to achieve the purpose, the technical scheme of the invention is as follows:
an interconnection process method of a back-illuminated CMOS image sensor structure comprises the following steps:
step S01: providing a bonded back-illuminated CMOS image sensor silicon wafer, wherein the silicon wafer comprises a substrate and a first dielectric layer on the front surface of the substrate, and a metal interconnection structure is formed in the first dielectric layer;
step S02: forming a second dielectric layer on the back surface of the substrate, and forming a through hole which is connected to the metal interconnection structure downwards through photoetching and etching;
step S03: filling an organic anti-reflection layer material in the through hole, and covering the surface of the second dielectric layer;
step S04: photoetching a back channel pattern, and enabling an exposure area to comprise a through hole pattern;
step S05: etching the back channel pattern, stopping etching on the first medium layer, and removing the photoresist to form a back channel structure connected with the through hole; in the etching process, synchronously etching the organic anti-reflection layer material filled in the through hole, and removing the residual organic anti-reflection layer material in the through hole by using a photoresist removing process after the etching is finished;
step S06: forming a third dielectric layer on the surfaces of the back channel structure and the through hole structure, removing the through hole and the third dielectric layer at the bottom of the back channel structure by utilizing anisotropic etching, and simultaneously controlling the loss amount of the third dielectric layer on the side wall to form the side wall of the back channel structure;
step S07: and filling a metal material in the back channel structure to form a pin pattern.
Preferably, in step S03, a protective layer is selectively grown on the surface of the metal interconnection structure at the bottom of the through hole, and then an organic anti-reflection layer material is filled in the through hole; step S05 further includes removing the protective layer at the bottom of the via.
Preferably, the protective layer is a CoWP film or a graphene film.
Preferably, in step S03, the CoWP film is formed by electroless plating; in step S05, the CoWP film is removed by wet etching.
Preferably, in step S03, the graphene film is formed by PECVD; in step S05, the graphene film is removed simultaneously during the photoresist stripping process.
Preferably, in step S02, a composite film layer and a metal layer are sequentially formed on the back surface of the substrate, a metal shielding pattern and an alignment mark between pixels are formed through a patterning process, and then a planarized second dielectric layer is formed on the composite film layer, the metal shielding pattern, and the alignment mark.
Preferably, the composite film layer comprises SiO2、HfO2TaO and TEOS.
Preferably, an antireflection medium layer is formed on the surface of the metal layer.
Preferably, the first dielectric layer, the second dielectric layer and the third dielectric layer are made of silicon dioxide.
Preferably, the metal layer material is Al or W, the metal interconnection structure material is Cu, and the pin material is Al.
According to the technical scheme, the forming sequence of the through hole and the back channel structure is adjusted, so that the relevant steps of photoetching can be performed on a plane, and the photoetching process effects such as exposure and the like are improved; the process is favorable for improving the photoresist removing residue, so that the damage of the photoresist removing to the surface of the metal interconnection layer for a long time can be reduced, and the reliability of electric connection is improved.
Drawings
FIG. 1 is a flow chart of an interconnection process for a backside illuminated CMOS image sensor structure according to the present invention;
FIGS. 2-7 are schematic cross-sectional views of the steps of the method of FIG. 1 according to a first preferred embodiment of the present invention;
FIG. 8 is a cross-sectional view of a related process step of the method of FIG. 1 in accordance with a second preferred embodiment of the present invention.
Detailed Description
The invention relates to an interconnection process method of a back-illuminated CMOS image sensor structure (CIS-BSI), which is mainly used for forming an interconnection structure and a pin (Pad) after a pixel silicon chip and a logic silicon chip are bonded; the method also has reference function for similar silicon wafer bonding structures.
The core idea of the back-illuminated CIS interconnection process is to adjust the formation sequence of the through hole and the back channel structure, so that the photoetching process is basically carried out in a plane area, exposure is facilitated, photoresist removing residues are improved, and damage to the metal surface caused by long-time photoresist removing is reduced.
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
In the following embodiments of the present invention, referring to fig. 1, fig. 1 is a flow chart of an interconnection process of a backside illuminated CMOS image sensor structure according to the present invention; referring to fig. 2-7, fig. 2-7 are schematic cross-sectional views illustrating process steps of the method of fig. 1 according to a first preferred embodiment of the present invention. As shown in fig. 1, the interconnection process method of a backside illuminated CMOS image sensor structure of the present invention includes the following steps:
step S01: and providing a bonded back-illuminated CMOS image sensor silicon wafer, wherein the silicon wafer comprises a substrate and a first dielectric layer on the front surface of the substrate, and a metal interconnection structure is formed in the first dielectric layer.
Please refer to fig. 2. Providing bonded back-illuminated CIS silicon chips, wherein the number of the silicon chips is two; one of the silicon chips mainly comprises structures such as a pixel unit, a logic circuit, a bonding pressure point and the like; the other silicon wafer mainly includes a substrate 200 and a metal interconnection structure 101 located in a first dielectric layer (interlayer dielectric layer) 100 on the substrate. The first dielectric layer material can adopt silicon dioxide, and the metal interconnection structure material can adopt Cu.
The substrate 200 of the silicon wafer is usually thinned, and may have a thickness of, for example, about 2.5 μm. Since the interconnection process flow related to this embodiment is performed on the back surface of the silicon wafer with the interconnection structure, and the patterning region is mainly a region corresponding to the interconnection layer, only the silicon wafer with the metal interconnection structure and a corresponding related region of the interconnection structure layer are labeled in fig. 2.
Step S02: and forming a second dielectric layer on the back surface of the substrate, and forming a through hole which is connected to the metal interconnection structure downwards through photoetching and etching.
Please refer to fig. 2. Firstly, sequentially forming a composite film layer 300 and a metal layer 400 on the back surface of a substrate 200; an anti-reflective dielectric layer (DARC) may be further formed on the metal layer according to a conventional process, and is not shown in the figure to make the relevant film layer related to the embodiment clearer. Then, a metal shielding pattern 401 and an alignment mark 402 between the pixels are formed through a patterning process.
The metal layer can be selectedAl and W, in this embodiment, Al is selected, and the thickness is 2500 &
Figure GDA0002596924660000041
Preferably, it is
Figure GDA0002596924660000042
The structure of the composite film 300 can be selected from various forms, including SiO in this embodiment2、HfO2TaO and TEOS. The metal shield pattern 401 is used for isolation between pixels to reduce mutual interference.
Please refer to fig. 3. Next, a second dielectric layer 500 is formed on the composite film layer, the metal shielding pattern, and the alignment mark, and the second dielectric layer is planarized. The second dielectric layer material can adopt silicon dioxide.
The silicon dioxide film layer (second dielectric layer) can be formed by Plasma Enhanced Chemical Vapor Deposition (PECVD), and the film deposition thickness can be
Figure GDA0002596924660000051
Preferably, it is
Figure GDA0002596924660000052
. The planarization process can be Chemical Mechanical Polishing (CMP), and the thickness of the silicon dioxide film layer on the metal shielding pattern can be
Figure GDA0002596924660000054
Preferably, it is
Figure GDA0002596924660000053
. After the planarization process, the surface of the silicon dioxide film 500 is smooth, which is helpful for the subsequent processes (such as photolithography).
Please refer to fig. 4. Next, a through hole (RV) patterning process is performed. A mask layer of a through hole pattern can be formed by utilizing a photoetching process, and the Critical Dimension (CD) of the through hole can be 0.3-0.5 mu m, and is preferably 0.4 mu m. The silicon dioxide film 500 and the films thereunder are etched until the metal interconnection structure 101 (metal one, M1).
The film type related to the etching process sequentially comprises a silicon dioxide layer 500 and a composite film 300(TEOS, TaO and HfO)2And SiO2) The Si substrate 200 and the interlayer dielectric layer 100 need to be completed by a one-step etching process.
Different types of films require corresponding etching conditions. Wherein, SiO2TEOS is oxide layer, and CF can be selected as etching gas4、CHF3In particular CF4110-130 sccm, preferably 120 sccm; CHF390-110 sccm, preferably 100 sccm; the chamber pressure is 100-120 mtorr, preferably 110 mtorr; the source power range is 700-900W, preferably 800W; the bias power range is 80-120W, and preferably 100W; the etching time is determined according to the thickness of the film layer and the actual etching rate of the pattern structure.
TaO、HfO2The film layer is thin, and the adopted etching gas is BCl3、Cl2、O2Ar, the process conditions are as follows: BCl325-35 sccm, preferably 30 sccm; cl240-50 sccm, preferably 45 sccm; o is25-7 sccm, preferably 6 sccm; ar is 16-20 sccm, preferably 18 sccm; the chamber pressure is 4-6 mtorr, preferably 5 mtorr; the source power range is 250-350W, preferably 300W; the bias power range is 150-170W, and preferably 160W.
The etching gas adopted by the Si substrate is Cl in combination2、O2The process conditions are as follows: cl280-120 sccm, preferably 100 sccm; o is26-14 sccm, preferably 8 sccm; the chamber pressure is 30-60 mtorr, preferably 40 mtorr; the source power range is 500-700W, and preferably 600W; the bias power range is 250-350W, preferably 300W.
The etching process parameters of the film layer can be adjusted according to actual conditions, so that the side wall appearance of different film layer interfaces is kept continuous. The resist is then stripped, and the resulting via structure 510 is shown in FIG. 4, which is a type of structure with multiple layers.
Step S03: and filling an organic anti-reflection layer material in the through hole, and covering the surface of the second dielectric layer.
Please refer to fig. 5. Next, an organic anti-reflective layer material (BARC) is filled in the via 510. After the via hole is formed, the BARC is filled in the via hole, so that the via hole is filled with BARC, and a BARC film layer is formed on the surface of the second dielectric layer 500. The BARC material has certain fluidity and the size of the through hole is larger, so that the BARC material can fill the whole through hole; in addition, the BARC film layer on the surface of the second dielectric layer oxide layer can be relatively flat through spin coating, and the subsequent photoetching process is facilitated.
Step S04: and photoetching the back channel pattern, and enabling the exposure area to comprise a through hole pattern.
Please refer to fig. 5. Thereafter, the photolithography process for forming the back side channel (BSL) of the pin (Pad) is continued. The basic size of the photoresist pattern 600 forming the back channel may be 4.5 to 5.5 μm, preferably 5 μm; the exposure region includes a via pattern.
Step S05: etching the back channel pattern, stopping etching on the first medium layer, and removing the photoresist to form a back channel structure connected with the through hole; and after the etching is finished, removing the residual organic anti-reflection layer material in the through hole by using a photoresist removing process.
Please refer to fig. 6. And then, etching the BSL pattern and removing the photoresist. Similar to the RV etching process, the etching process also includes various film materials, mainly including an oxide layer 500 and a composite film 300(TEOS, TaO, HfO)2And SiO2) The Si substrate 200 stops on the interlevel dielectric layer 100 of M1. The etching process conditions of the corresponding film layer can refer to the RV etching process. During the etching process, the BARC filled in the via hole is also simultaneously etched.
And after the etching process is finished, removing the photoresist and the residual BARC in the through hole by using a photoresist removing process. By adopting the method, the metal interconnection layer at the bottom of the through hole can be bombarded by the plasma only after the BARC is removed, so that the bombardment in the whole photoresist removing process is avoided, and the damage to the surface of the metal interconnection layer is reduced to a certain extent.
To this end, the final via structure 525 and the BSL pattern structure 515 involving various film layer structures within the interlayer dielectric layer 100 have been formed.
Step S06: and forming a third dielectric layer on the surfaces of the back channel structure and the through hole structure, removing the through hole and the third dielectric layer at the bottom of the back channel structure by utilizing anisotropic etching, and simultaneously controlling the loss amount of the third dielectric layer on the side wall to form the side wall of the back channel structure.
Please refer to fig. 7. Next, a sidewall 530 of the BSL structure is formed. Forming a third dielectric layer on the surface of the BSL and the through hole structure as a passivation film layer, wherein the preferred material of the passivation film layer is SiO2With a thickness of
Figure GDA0002596924660000071
Preferably, it is
Figure GDA0002596924660000072
And then, removing the passivation film layers at the bottoms of the through hole 525 and the back channel structure 515 by utilizing anisotropic etching, and simultaneously controlling the loss amount of the side wall passivation film layer to form effective electrical contact of the through hole structure.
Step S07: and filling a metal material in the back channel structure to form a pin pattern.
Finally, filling metal materials in the BSL structure to form a pin pattern; the pin material may be Al.
Referring to fig. 8, fig. 8 is a schematic cross-sectional view illustrating a related process step of the method of fig. 1 according to a second preferred embodiment of the present invention. As shown in fig. 8, the interconnection process method of the backside illuminated CMOS image sensor structure according to the present invention is improved based on the first embodiment, and includes the following specific contents:
in step S03, a protective layer 102 is selectively grown on the surface of the metal interconnection structure 101 at the bottom of the via, and then the via is filled with the organic anti-reflection layer material.
Since the metal interconnection structure 101 is made of Cu material, the protection layer 102 may be a CoWP (cobalt tungsten phosphorus) film formed by electroless plating, or a graphene film formed by PECVD, and the film thickness is as thin as
Figure GDA0002596924660000073
Preferably, it is
Figure GDA0002596924660000074
Correspondingly, in step S05, the method further includes removing the protective layer at the bottom of the via. Wherein, the CoWP thin film can be removed by adopting a wet etching mode; the graphene film can be removed synchronously in the photoresist removing process without adding an additional removing process step.
By adding the above steps to the first embodiment, plasma damage caused by photoresist stripping after the BSL pattern etching of the metal interconnection layer can be further avoided.
In summary, the forming sequence of the through hole and the back channel structure is adjusted, so that the related steps of the photoetching can be performed on a plane, and the photoetching process effects such as exposure and the like can be improved; the process is favorable for improving the photoresist removing residue, so that the damage of the photoresist removing to the surface of the metal interconnection layer for a long time can be reduced, and the reliability of electric connection is improved.
The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.

Claims (10)

1. An interconnection process method of a back-illuminated CMOS image sensor structure is characterized by comprising the following steps:
step S01: providing a bonded back-illuminated CMOS image sensor silicon wafer, wherein the silicon wafer comprises a substrate and a first dielectric layer on the front surface of the substrate, and a metal interconnection structure is formed in the first dielectric layer;
step S02: forming a second dielectric layer on the back surface of the substrate, and forming a through hole which is connected to the metal interconnection structure downwards through photoetching and etching;
step S03: filling an organic anti-reflection layer material in the through hole, and covering the surface of the second dielectric layer;
step S04: photoetching a back channel pattern, and enabling an exposure area to comprise a through hole pattern;
step S05: etching the back channel pattern, stopping etching on the first medium layer, and removing the photoresist to form a back channel structure connected with the through hole; in the etching process, synchronously etching the organic anti-reflection layer material filled in the through hole, and removing the residual organic anti-reflection layer material in the through hole by using a photoresist removing process after the etching is finished;
step S06: forming a third dielectric layer on the surfaces of the back channel structure and the through hole structure, removing the through hole and the third dielectric layer at the bottom of the back channel structure by utilizing anisotropic etching, and simultaneously controlling the loss amount of the third dielectric layer on the side wall to form the side wall of the back channel structure;
step S07: and filling a metal material in the back channel structure to form a pin pattern.
2. The interconnection process method of the backside illuminated CMOS image sensor structure of claim 1, wherein in step S03, a protective layer is selectively grown on the surface of the metal interconnection structure at the bottom of the via hole, and then an organic anti-reflection layer material is filled in the via hole; step S05 further includes removing the protective layer at the bottom of the via.
3. The interconnection process method of the back-illuminated CMOS image sensor structure of claim 2, wherein the protection layer is a CoWP thin film or a graphene thin film.
4. The interconnection process method of the backside illuminated CMOS image sensor structure of claim 3, wherein in step S03, the CoWP thin film is formed by electroless plating; in step S05, the CoWP film is removed by wet etching.
5. The interconnection process method of the backside illuminated CMOS image sensor structure of claim 3, wherein in step S03, the graphene film is formed by PECVD; in step S05, the graphene film is removed simultaneously during the photoresist stripping process.
6. The interconnection process of the backside illuminated CMOS image sensor structure of claim 1, wherein in step S02, a composite film layer and a metal layer are sequentially formed on the backside surface of the substrate, and a metal shielding pattern and an alignment mark between pixels are formed by a patterning process, and then a planarized second dielectric layer is formed on the composite film layer, the metal shielding pattern and the alignment mark.
7. The method for interconnecting process of backside illuminated CMOS image sensor structure of claim 6, wherein said composite film layer comprises SiO2、HfO2TaO and TEOS.
8. The method according to claim 6, wherein an anti-reflective dielectric layer is formed on the surface of the metal layer.
9. The interconnection process method of the back-illuminated CMOS image sensor structure of claim 1, wherein the first, second and third dielectric layers are made of silicon dioxide.
10. The interconnection process method of the backside illuminated CMOS image sensor structure of claim 6, wherein the metal layer material is Al or W, the metal interconnection structure material is Cu, and the pin material is Al.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1215833A (en) * 1997-10-07 1999-05-05 罗伯特-博希股份公司 Sensor with diaphragm
US20100178018A1 (en) * 2007-09-06 2010-07-15 Augusto Carlos J R P Photonic Via Waveguide for Pixel Arrays
CN102569326A (en) * 2012-03-07 2012-07-11 格科微电子（上海）有限公司 Image sensor and production method thereof
US20130277789A1 (en) * 2012-04-18 2013-10-24 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and Apparatus for Via Last Through-Vias

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1215833A (en) * 1997-10-07 1999-05-05 罗伯特-博希股份公司 Sensor with diaphragm
US20100178018A1 (en) * 2007-09-06 2010-07-15 Augusto Carlos J R P Photonic Via Waveguide for Pixel Arrays
CN102569326A (en) * 2012-03-07 2012-07-11 格科微电子（上海）有限公司 Image sensor and production method thereof
US20130277789A1 (en) * 2012-04-18 2013-10-24 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and Apparatus for Via Last Through-Vias

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