CN112349740A - Backside illuminated image sensor and forming method thereof - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 64
- 238000002955 isolation Methods 0.000 claims abstract description 148
- 239000000758 substrate Substances 0.000 claims abstract description 78
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims description 37
- 239000002184 metal Substances 0.000 claims description 37
- 238000000605 extraction Methods 0.000 claims description 17
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 230000036961 partial effect Effects 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 28
- 238000005286 illumination Methods 0.000 abstract description 4
- 230000002829 reductive effect Effects 0.000 abstract description 3
- 230000003287 optical effect Effects 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- 239000010703 silicon Substances 0.000 description 1
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- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14632—Wafer-level processed structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14687—Wafer level processing
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Abstract
The invention provides a back side illumination image sensor and a forming method thereof, comprising the following steps: providing a substrate; forming a pattern corresponding to the leading-out hole and the isolation groove on one mask plate; forming a patterned photoresist layer by using a mask, wherein the patterned photoresist layer comprises openings corresponding to the leading-out hole and the isolation groove; etching the substrate from one side of the back surface of the substrate by taking the patterned photoresist layer as a mask to form a leading-out hole and an isolation groove; forming an isolation layer at least covering the side wall of the isolation trench; an interconnect layer is formed. The method reduces the area of the opening hole and improves the utilization rate of the area of the chip. Patterns corresponding to the leading-out holes and the isolation grooves are formed on one mask, the leading-out holes and the isolation grooves are formed simultaneously through one-time etching process, the back leading process and the groove isolation process are carried out simultaneously, the process is simplified, and the process cost is reduced. The isolation layer at least covers the side wall of the isolation groove, and the electrical isolation capability among different pixel units is improved.
Description
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a back-illuminated image sensor and a forming method thereof.
Background
The back side illumination type image sensor (BSI) is a CMOS image sensor widely applied at present, and compared with a front side illumination type image sensor (FSI), the BSI has the process characteristic that a wafer with a pixel unit is turned over through a wafer bonding technology, so that incident light is directly irradiated on the back side of a silicon wafer without penetrating through a front side dielectric layer and a metal wiring layer, and the degree of freedom of pixel design is improved.
The backside illuminated image sensor generally uses a backside wire process, as shown in fig. 1, an insulating layer 02 and a substrate 01 in the backside illuminated image sensor are etched to form an opening V, a pad 05 is formed in the opening V, and the pad 05 is electrically connected to a metal wiring layer 04 embedded in a dielectric layer 03. In order to form the bonding pad 05, the backside wire-leading method needs to form a larger area of the opening V on the substrate 01, and the larger area of the opening V on the substrate 01 cannot be used for designing a device, so that the utilization rate of the chip area is low, and the further reduction of the chip size of the back-illuminated image sensor is limited, and the requirement of miniaturization of the back-illuminated image sensor cannot be met. In addition, the back lead process and the trench isolation process are formed separately, different masks are adopted, and the back lead process and the trench isolation process are formed in different etching steps, so that the process is complex.
Disclosure of Invention
The invention aims to provide a back-illuminated image sensor and a forming method thereof, which can reduce the area of an opening, improve the utilization rate of the area of a chip of the back-illuminated image sensor, simplify the process, and improve the anti-crosstalk capability, thereby improving the optical performance.
The invention provides a method for forming a back-illuminated image sensor, which comprises the following steps:
providing a substrate, wherein the substrate is provided with a front substrate surface and a back substrate surface which are opposite, a dielectric layer is formed on the front substrate surface, and a metal wiring layer is embedded in the dielectric layer;
providing a mask plate, wherein a pattern corresponding to the leading-out hole and the isolation groove is formed on the mask plate;
forming a patterned photoresist layer by using the mask plate, wherein the patterned photoresist layer comprises openings corresponding to the leading-out hole and the isolation groove;
etching the substrate from one side of the back surface of the substrate by taking the patterned photoresist layer as a mask to form the leading-out hole and the isolation groove; the leading-out hole exposes the metal wiring layer;
forming an isolation layer, wherein the isolation layer covers the side wall and the bottom surface of the leading-out hole, and at least covers the side wall of the isolation groove;
etching the isolation layer at the bottom of the leading-out hole to expose the metal wiring layer;
forming an interconnect layer that at least fills the exit hole and is electrically connected with the metal wiring layer.
Further, the isolation layer also fills the isolation trench.
Further, the interconnection layer also fills the isolation trench.
Further, the material of the interconnection layer includes: tungsten.
Further, the interconnection layer is formed by a chemical vapor deposition method, a plasma enhanced chemical vapor deposition method or a high density plasma chemical vapor deposition method.
Further, the material of the isolation layer includes: a silicon oxide layer and/or a silicon nitride layer.
The present invention also provides a back-illuminated image sensor, comprising:
the substrate is provided with a substrate front side and a substrate back side which are opposite, a dielectric layer is formed on the substrate front side, and a metal wiring layer is embedded in the dielectric layer;
the leading-out hole penetrates through the substrate and exposes the metal wiring layer, and the isolation groove penetrates through the substrate with partial thickness or all thickness;
the isolation layer covers the side wall of the leading-out hole, and at least covers the side wall of the isolation groove;
an interconnect layer at least filling the exit hole and electrically connected with the metal wiring layer.
Further, the interconnection layer also fills the isolation trench.
Furthermore, a plurality of pixel unit areas are formed on the substrate, the isolation grooves are distributed between the adjacent pixel unit areas, and color filter units and micro lenses are distributed right above each pixel unit area.
Further, on a cross section perpendicular to the substrate, the cross section of the extraction hole is rectangular.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a back side illumination image sensor and a forming method thereof, comprising the following steps: providing a substrate; providing a mask plate, wherein a pattern corresponding to the leading-out hole and the isolation groove is formed on the mask plate; forming a patterned photoresist layer by using the mask plate, wherein the patterned photoresist layer comprises openings corresponding to the leading-out hole and the isolation groove; etching the substrate from one side of the back surface of the substrate by taking the patterned photoresist layer as a mask to form the leading-out hole and the isolation groove; forming an isolation layer, wherein the isolation layer covers the side wall and the bottom surface of the leading-out hole, and at least covers the side wall of the isolation groove; an interconnect layer is formed. The method reduces the area of the opening and improves the utilization rate of the area of the chip of the back-illuminated image sensor. Patterns corresponding to the leading-out holes and the isolation grooves are formed on one mask, the leading-out holes and the isolation grooves are formed simultaneously through one-time etching process, the back leading process and the groove isolation process are carried out simultaneously, the process is simplified, and the process cost is reduced. The isolation layer at least covers the side wall of the isolation groove, and the electrical isolation capability among different pixel units is improved.
Further, the interconnection layer also fills the isolation trench. The isolation layer and the interconnection layer in the isolation groove have the functions of electrical isolation and optical isolation among different pixel units, so that the anti-crosstalk capability of the back-illuminated image sensor is improved, and the optical performance of the sensor is improved.
Drawings
FIG. 1 is a schematic diagram of a backside illuminated image sensor with a large opening;
fig. 2 is a flowchart illustrating a method for forming a backside illuminated image sensor according to an embodiment of the invention.
Fig. 3 to fig. 7 are schematic diagrams illustrating steps of a method for forming a backside illuminated image sensor according to an embodiment of the invention.
Fig. 8 to 11 are schematic diagrams illustrating steps of another method for forming a backside illuminated image sensor according to an embodiment of the invention.
Detailed Description
The embodiment of the invention provides a back-illuminated image sensor and a forming method thereof. The invention is described in further detail below with reference to the figures and specific examples. The advantages and features of the present invention will become more apparent from the following description. It is to be noted, however, that the drawings are designed in a simplified form and are not to scale, but rather are to be construed in an illustrative and descriptive sense only and not for purposes of limitation.
An embodiment of the present invention provides a method for forming a backside illuminated image sensor, as shown in fig. 2, including:
s1, providing a substrate, wherein the substrate is provided with a front substrate surface and a back substrate surface which are opposite, a dielectric layer is formed on the front substrate surface, and a metal wiring layer is embedded in the dielectric layer;
s2, providing a mask plate, wherein a pattern corresponding to the extraction hole and the isolation groove is formed on the mask plate;
s3, forming a patterned photoresist layer by using the mask, wherein the patterned photoresist layer comprises openings corresponding to the extraction hole and the isolation groove;
s4, etching the substrate from the back side of the substrate by taking the patterned photoresist layer as a mask to form the extraction hole and the isolation groove; the leading-out hole exposes the metal wiring layer;
s5, forming an isolation layer, wherein the isolation layer covers the side wall and the bottom surface of the extraction hole, and at least covers the side wall of the isolation groove;
s6, etching the isolation layer at the bottom of the leading-out hole to expose the metal wiring layer;
s7, forming an interconnection layer, wherein the interconnection layer at least fills the extraction hole and is electrically connected with the metal wiring layer.
The steps of a method for forming a backside illuminated image sensor according to an embodiment of the present invention will be described with reference to fig. 3 to 7.
As shown in fig. 3, a substrate 10 is provided, said substrate 10 having an opposite substrate front side f1And a substrate back surface f2Said substrate front side f1A dielectric layer 13 is formed, and a metal wiring layer 14 is embedded in the dielectric layer 13. Front side f of the substrate1A photodiode formed on one side, and a back surface f of the substrate2An insulating layer 11 is formed on one side. And providing a mask plate, wherein a pattern corresponding to the extraction hole and the isolation groove is formed on the mask plate. Forming a patterned photoresist layer 12 by using the mask, wherein the patterned photoresist layer 12 comprises openings corresponding to the extraction hole and the isolation groove; the opening corresponding to the lead-out hole is V1The opening corresponding to the isolation trench is V2. The metal wiring layer 14 may be a metal line distributed in a direction parallel to the substrate 10; the metal wiring layer 14 may also be a metal line running in a direction parallel to the substrate 10 and a lead-out line running in a direction perpendicular to the substrate 10, the lead-out line and the metal line being electrically connected.
As shown in fig. 4, the insulating layer 11 and the substrate 10 are etched to form the extraction hole Va and the isolation trench Vb by using the patterned photoresist layer 12 as a mask; the lead-out hole Va exposes the metal wiring layer 14.
As shown in fig. 4 and 5, an isolation layer 15a is formed, the isolation layer 15a covering the side wall and the bottom surface of the extraction hole Va, the isolation layer 15a further covering at least the side wall of the isolation trench Vb. The isolation layer 15a may be formed using an Atomic Layer Deposition (ALD) process or a plasma chemical vapor deposition (PECVD) process. For the small-sized (narrow cross-section width) isolation trench Vb, the isolation layer 15a may be filled in the isolation trench Vb, the isolation trench Vb is usually deep, and the isolation layer 15a is filled in the isolation trench Vb, which is also called Deep Trench Isolation (DTI), and plays a role in electrical isolation between different pixel units. The isolation layer 15a is made of, for example, a silicon oxide layer or a silicon nitride layer.
As shown in fig. 6, the isolation layer 15a at the bottom of the lead-out hole Va is etched to expose the metal wiring layer 14.
As shown in fig. 6 and 7, an interconnect layer 16a is formed, the interconnect layer 16a filling at least the extraction hole Va and being electrically connected to the metal wiring layer 14. The interconnection layer 16a may be formed by a chemical vapor deposition method, a plasma enhanced chemical vapor deposition method or a high density plasma chemical vapor deposition method, the interconnection layer 16a fills the extraction hole Va and covers the upper surface of the isolation layer 15a, and the interconnection layer 16a is planarized or plasma etched by a Chemical Mechanical Polishing (CMP) process, preferably, so that the top surface of the interconnection layer 16a is flush with the top surface of the isolation layer 15 a. The isolation layer 15a located on the sidewall of the extraction hole Va prevents the interconnect layer 16a from diffusing into the substrate 10.
The steps of another method for forming a backside illuminated image sensor according to an embodiment of the present invention are described below with reference to fig. 8 to 11. For larger size (wider cross-sectional width) isolation trenches, the interconnect layer also fills the isolation trenches.
As shown in fig. 8, the patterned photoresist layer 12 is used as a mask to etch the insulating layer 11 and the substrate 10 to form the extraction hole Va and the isolation trench Vc; the lead-out hole Va exposes the metal wiring layer 14.
As shown in fig. 9, an isolation layer 15b is formed, the isolation layer 15b covering the sidewalls and the bottom surface of the extraction hole Va, the isolation layer 15b also covering the sidewalls and the bottom surface of the isolation trench Vc. The isolation layer 15b may be formed using an Atomic Layer Deposition (ALD) process or a plasma chemical vapor deposition (PECVD) process. For isolation trench Vc of larger size (wider cross-sectional width), isolation layer 15b cannot be completely filled when deposited, and isolation layer 15b only covers the sidewalls and bottom surface of isolation trench Vc.
As shown in fig. 10, the isolation layer 15b at the bottom of the lead-out hole Va is etched to expose the metal wiring layer 14.
As shown in fig. 11, an interconnect layer 16b is formed, the interconnect layer 16b filling the extraction hole Va and being electrically connected to the metal wiring layer 14, the interconnect layer 16b also filling the isolation trench Vc. The material of the interconnect layer 16b is, for example, tungsten. The interconnect layer 16b filled in the lead-out hole Va is electrically connected to the metal wiring layer 14, and leads out the metal wiring layer 14. The interconnect layer 16b filled in the isolation trench Vc functions as optical isolation between different pixel cells. The isolation trench Vc is generally deep, an isolation layer 15b and an interconnect layer 16b formed in the isolation trench Vc perform isolation, also referred to as Deep Trench Isolation (DTI), and the isolation layer 15b and the interconnect layer 16b located in the isolation trench Vc perform electrical isolation and optical isolation between different pixel units. The isolation layer 15b is made of, for example, a silicon oxide layer or a silicon nitride layer.
The present embodiment also provides a back-illuminated image sensor including:
the substrate is provided with a substrate front side and a substrate back side which are opposite, a dielectric layer is formed on the substrate front side, and a metal wiring layer is embedded in the dielectric layer;
the leading-out hole penetrates through the substrate and exposes the metal wiring layer, and the isolation groove penetrates through the substrate with partial thickness or all thickness;
the isolation layer covers the side wall of the leading-out hole, and at least covers the side wall of the isolation groove;
an interconnect layer at least filling the exit hole and electrically connected with the metal wiring layer.
The isolation trench penetrates through part of or all of the thickness of the substrate; the isolation trench is mainly used for restraining the back surface f of the substrate2Lateral crosstalk of one-sided incoming light, pixel cell region A located near the back surface f of the substrate2When the substrate is arranged on one side, the isolation groove penetrates through the substrate with partial thickness to play a role in inhibiting the transverse crosstalk of light. The isolation trench penetrates through the substrate with the whole thickness, so that the specific position of the pixel unit area A in the direction vertical to the substrate does not need to be considered, and isolation in the whole substrate thickness range is realized.
Fig. 7 shows that the isolation layer 15a fills the isolation trench Vb for a small-sized (narrow cross-sectional width) isolation trench Vb.
Fig. 11 shows that for isolation trench Vc of larger size (wider cross-sectional width), isolation layer 15b is deposited so as not to completely fill isolation trench Vc, and isolation layer 15b only covers the sidewalls and bottom surface of isolation trench Vc. The interconnect layer 16b also fills the isolation trench Vc.
A plurality of pixel unit areas A are formed on the substrate 10, the isolation grooves are distributed between the adjacent pixel unit areas A, and deep groove isolation is used between the pixels to inhibit transverse crosstalk. Color filter units and microlenses are distributed over each of the pixel unit regions A. Specifically, the color filter units and the microlenses are sequentially distributed over the isolation layer 15 b. Wherein the micro-lenses, the color filter units and the pixel unit regions correspond to each other in a direction perpendicular to the substrate.
In summary, the backside illuminated image sensor and the forming method thereof provided in the present embodiment include: providing a substrate; providing a mask plate, wherein a pattern corresponding to the leading-out hole and the isolation groove is formed on the mask plate; forming a patterned photoresist layer by using the mask plate, wherein the patterned photoresist layer comprises openings corresponding to the leading-out hole and the isolation groove; etching the substrate from one side of the back surface of the substrate by taking the patterned photoresist layer as a mask to form the leading-out hole and the isolation groove; forming an isolation layer, wherein the isolation layer covers the side wall and the bottom surface of the leading-out hole, and at least covers the side wall of the isolation groove; an interconnect layer is formed. The method reduces the area of the opening and improves the utilization rate of the area of the chip of the back-illuminated image sensor. Patterns corresponding to the leading-out holes and the isolation grooves are formed on one mask, the leading-out holes and the isolation grooves are formed simultaneously through one-time etching process, the back leading process and the groove isolation process are carried out simultaneously, the process is simplified, and the process cost is reduced. The isolation layer at least covers the side wall of the isolation groove, and the electrical isolation capability among different pixel units is improved.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the device disclosed by the embodiment, the description is relatively simple because the device corresponds to the method disclosed by the embodiment, and the relevant part can be referred to the method part for description.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method of forming a backside illuminated image sensor, comprising:
providing a substrate, wherein the substrate is provided with a front substrate surface and a back substrate surface which are opposite, a dielectric layer is formed on the front substrate surface, and a metal wiring layer is embedded in the dielectric layer;
providing a mask plate, wherein a pattern corresponding to the leading-out hole and the isolation groove is formed on the mask plate;
forming a patterned photoresist layer by using the mask plate, wherein the patterned photoresist layer comprises openings corresponding to the leading-out hole and the isolation groove;
etching the substrate from one side of the back surface of the substrate by taking the patterned photoresist layer as a mask to form the leading-out hole and the isolation groove; the leading-out hole exposes the metal wiring layer;
forming an isolation layer, wherein the isolation layer covers the side wall and the bottom surface of the leading-out hole, and at least covers the side wall of the isolation groove;
etching the isolation layer at the bottom of the leading-out hole to expose the metal wiring layer;
forming an interconnect layer that at least fills the exit hole and is electrically connected with the metal wiring layer.
2. The method of forming a back-illuminated image sensor of claim 1, wherein the isolation layer further fills the isolation trench.
3. The method of forming a back-illuminated image sensor of claim 1, wherein the interconnect layer further fills the isolation trench.
4. The method of claim 1, wherein the interconnect layer comprises: tungsten.
5. The method of forming a back-illuminated image sensor as claimed in claim 1, wherein the interconnection layer is formed by a chemical vapor deposition method, a plasma enhanced chemical vapor deposition method, or a high density plasma chemical vapor deposition method.
6. The method of claim 1, wherein the spacer layer comprises: a silicon oxide layer and/or a silicon nitride layer.
7. A backside illuminated image sensor, comprising:
the substrate is provided with a substrate front side and a substrate back side which are opposite, a dielectric layer is formed on the substrate front side, and a metal wiring layer is embedded in the dielectric layer;
the leading-out hole penetrates through the substrate and exposes the metal wiring layer, and the isolation groove penetrates through the substrate with partial thickness or all thickness;
the isolation layer covers the side wall of the leading-out hole, and at least covers the side wall of the isolation groove;
an interconnect layer at least filling the exit hole and electrically connected with the metal wiring layer.
8. The back-illuminated image sensor of claim 7, wherein the interconnect layer further fills the isolation trench.
9. The back-illuminated image sensor of claim 7,
a plurality of pixel unit areas are formed on the substrate, the isolation grooves are distributed between the adjacent pixel unit areas, and color filter units and micro lenses are distributed right above the pixel unit areas.
10. The back-illuminated image sensor of claim 7, wherein a cross-sectional shape of the extraction hole in a cross-section perpendicular to the substrate is rectangular.
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CN115084180A (en) * | 2022-06-27 | 2022-09-20 | 上海集成电路装备材料产业创新中心有限公司 | Backside illuminated image sensor and manufacturing method thereof |
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