JP4427949B2 - Solid-state imaging device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device, and more particularly, to a solid-state imaging device in which a well for increasing light collection efficiency is provided on a light receiving sensor unit and a manufacturing method thereof.
[0002]
[Prior art]
In recent years, a well in which a high refractive index layer is embedded in a low refractive index layer has been provided on a plurality of light receiving sensor portions including, for example, photodiodes constituting a pixel, and a critical angle of incident light from above the well is provided. A configuration is known in which incident light having a larger incident angle is totally reflected at the interface between the high refractive index layer and the low refractive index layer, thereby improving the light collection efficiency to the light receiving sensor unit. (See Patent Document 1).
[0003]
FIG. 12 shows a configuration of a solid-state imaging device having such a configuration, for example, a CMOS solid-state imaging device (CMOS sensor).
In the illustrated example, a cross-sectional view of one pixel of the CMOS type solid-state imaging device is shown.
In the CMOS type solid-state imaging device 30, a light receiving sensor unit 33 for receiving light is formed in a predetermined region in the semiconductor substrate 31 separated by the element isolation region 32, and insulation is provided at a predetermined position on the light receiving sensor unit 33. A transfer gate 35, a conductive plug 36, and a wiring layer 37 are formed in the interlayer insulating film 38 via the film 34.
[0004]
The wiring layer 37 is formed in two layers (371 and 372) in the illustrated example, and the wiring layers 371 and 372 are connected by a conductive plug. Above the uppermost wiring layer 372, a color filter 41 is formed on the interlayer insulating film 38 via a passivation film 39 and a planarizing film 40, and at a position corresponding to the light receiving sensor unit 33 on the color filter 41. An on-chip lens 42 is formed.
[0005]
A well 43 is formed in the interlayer insulating film 38 on the light receiving sensor portion 33 so as to connect the light receiving sensor portion 33 and the on-chip lens 42 to the lower end of the passivation film 39. A high refractive index layer (plasma SiN film) 44 having a higher refractive index (for example, n = 2.0) than that of the insulating film 38 is embedded. Reference numeral 45 denotes an etching stop film.
[0006]
In the CMOS type solid-state imaging device 30 having such a configuration, for example, light (arrow X in the figure) incident on the well 43 through the on-chip lens 42 reaches the light receiving sensor unit 33 until the high refractive index layer 44. Thus, total reflection is repeated at the interface between and the interlayer insulating film 38 and is guided to the light receiving sensor unit 33. Thereby, the light incident in the well 43 can be incident on the light receiving sensor unit 33 without leaking as much as possible.
[0007]
A method for manufacturing such a solid-state imaging device, particularly a method for forming the well 43, is shown in FIGS.
First, as shown in FIG. 13A, a light receiving sensor unit 33 that receives incident light is formed in a predetermined region in the semiconductor substrate 31 separated by the element isolation region 32, and an insulating film 34 is formed on the light receiving sensor unit 33. A description will be given from the formed state.
[0008]
Next, as shown in FIG. 13B, a transfer gate 35 is formed at a predetermined position via an insulating film 34, and an etching stopper film (for example, a SiN film) is formed on a portion corresponding to the light receiving sensor portion 33 by, for example, a low pressure CVD method. 45 is formed.
The etching stopper film 45 has a high etching selectivity with respect to the interlayer insulating film 38 in the step of forming the well 43 in the interlayer insulating film 38 on the light receiving sensor portion 33 described later (see FIG. 14D). Yes.
[0009]
Next, as shown in FIG. 13C, an interlayer insulating film 38 is formed on the entire surface covering the transfer gate 35, the etching stopper film 45, and the element isolation region 31, and after planarizing the surface, the conductive plug 36, A wiring layer 37 is formed. In the illustrated example, since the wiring layer 37 is formed in a two-layer structure (371, 372), the conductive plug 36 is first formed at a predetermined position in the interlayer insulating film 38, and then the planarized interlayer insulating film 38 is formed. A wiring layer 371 as the first layer is formed on the light receiving sensor unit 33 except for the region on the light receiving sensor unit 33. Next, the interlayer insulating film 38 is formed again on the entire surface covering the wiring layer 371, the surface is planarized, and the conductive plug 36 is formed at a predetermined position. As described above, the light receiving sensor section 33 is formed. A second wiring layer 372 is formed on the interlayer insulating film 38 except for the upper region. Then, an interlayer insulating film 38 is formed again on the entire surface covering the wiring layer 372, and the interlayer insulating film 37 is planarized.
Thus, the wiring layer 37 (371, 372) having a two-layer structure is formed.
[0010]
  Next, as shown in FIG. 14D, a resist film (not shown) is formed on the interlayer insulating film 38, and the resist film is formed on a resist mask having a well formation pattern using a known lithography technique. The interlayer insulating film 38 is removed by etching, for example, by anisotropic dry etching through this resist mask, and a well (so-called opening) 43 is formed at a corresponding position on the light receiving sensor portion 33.
  As a reactive gas used for anisotropic dry etching, for example,C ₄ F ₈ gasAr gas,O ₂ gasEtc. can be used.
[0011]
Next, as shown in FIG. 14E, the resist mask is removed, and a high refractive index layer having a higher refractive index than the interlayer insulating film 38 is formed on the entire surface of the interlayer insulating film 38 including the well 43. As this high refractive index layer, for example, a SiN film (so-called plasma SiN film) 44 using a high density plasma CVD method is formed.
[0012]
Next, as shown in FIG. 15F, the plasma SiN film 44 is removed up to the surface of the interlayer insulating film 38 using, for example, a CMP method or an etch back method, and a planarization process is performed.
[0013]
Next, as shown in FIG. 15G, a passivation film 39, a planarizing film 40, and a color filter 41 are sequentially formed on the entire surface including the interlayer insulating film 38 and the plasma SiN film 44 embedded in the well 43. An on-chip lens 42 is formed at a position corresponding to the light receiving sensor portion 33 of the color filter 41, that is, above the well 44.
In this way, the CMOS type solid-state imaging device 30 having a configuration for improving the light collection efficiency is formed.
[0014]
[Patent Document 1]
JP 2000-150845 A
[0015]
[Problems to be solved by the invention]
By the way, in the CMOS type solid-state imaging device 30 as described above, since the wiring layers 37 are formed in multiple layers (in the illustrated example, the first wiring layer 371 and the second wiring layer 372), all the wiring layers 37 are formed. When the well (opening) 43 is formed from the outermost surface layer to the light receiving sensor portion 33 after the formation (see FIG. 14D), the depth h of the well 43 is formed deep (for example, h = 5 μm).
Further, along with the recent demand for miniaturization, for example, when miniaturization is attempted with such a CMOS solid-state imaging device, the pixels themselves are further reduced, so the diameter (width) d of the well 43 is further reduced. Will be formed. Therefore, the well 43 having a very high aspect ratio is formed.
[0016]
Thus, when the well 43 having a high aspect ratio is formed, when the SiN film 44 is embedded in the well 43 by, for example, a high-density plasma CVD method in the next step (see FIG. 14E), FIG. As shown in FIG. 16, there is a problem that a cavity (so-called void) 46 is formed in the well 43.
[0017]
Such a problem occurs when the high density plasma CVD method is used when embedding the SiN film 44 in the well 43, and the formation of the buried material in the vicinity of the entrance of the well 43 is a region behind the well 43. This is because it is faster than.
As a result, the vicinity of the entrance of the well 43 is gradually blocked, the supply of radicals as film formation species to the inside of the well 43 is reduced, the vicinity of the entrance of the well 43 is completely blocked, and the inside of the well 43 Thus, a void 46 is formed.
[0018]
Thus, when the cavity 46 is formed in the well 43, reflection and refraction are caused by the cavity 46, so that the light condensing effect is deteriorated and sensitivity characteristics are varied.
[0019]
Conventionally, it is contained in the plasma SiN film 44 by, for example, an annealing process in order to reduce the interface state in the light receiving sensor unit 33 or to repair the disorder of the crystal lattice and suppress the generation of white spots. However, when the cavity 46 is formed, the volume of the plasma SiN film 44 is reduced accordingly, so that the supply rate of hydrogen to the light receiving sensor unit 33 is increased. As a result, the effect of suppressing the occurrence of white spots is reduced.
[0020]
In the future, unless the wiring structure is further multilayered (for example, 5 to 7 layers), it will not be possible to meet the demands for increasing the number of pixels and miniaturizing the element size. It is considered that the burying property of the SiN film 44 is further deteriorated.
[0021]
Thus, the problem that the cavity 46 is formed in the well 43 is that not only the CMOS solid-state image pickup device (CMOS sensor) 30 as described above but also the aspect ratio of the CCD solid-state image pickup device with the miniaturization of the pixel, for example. Since it becomes high, it is conceivable that the same occurs.
[0022]
In view of the above-described points, the present invention provides a solid-state imaging device capable of causing light to enter a light receiving sensor unit with high light collection efficiency even when a wiring layer is multilayered or a pixel is miniaturized, and a method for manufacturing the same. It is to provide.
[0023]
[Means for Solving the Problems]
  The solid-state imaging device according to the present invention is provided on the light receiving sensor unitIn order to cause incident light to be totally reflected at the interface between the high refractive index layer and the low refractive index layer and to be condensed on the light receiving sensor part,A well in which a high refractive index layer is embedded in a low refractive index layer is provided, and the well is constituted by a plurality of layers having different diameters. Also, the lower layer of the upper layer is formed to have a small diameter.
[0024]
According to the solid-state imaging device according to the present invention, since the well is composed of a plurality of layers having different diameters, the depth of each layer is shallow, so that the high refractive index layer can be satisfactorily embedded, and the cavity Can be prevented. In addition, in the layers adjacent to each other among the plurality of layers, the lower diameter of the upper layer is smaller than the upper diameter of the lower layer, so that the lower layer is wide at the stepped portion between each layer, and unnecessary reflection or refraction does not occur at this stepped portion. Therefore, the light can be sufficiently condensed on the light receiving sensor unit.
[0025]
  The manufacturing method of the solid-state imaging device according to the present invention, on the light receiving sensor unit,In order to cause incident light to be totally reflected at the interface between the high refractive index layer and the low refractive index layer and to be condensed on the light receiving sensor part,A method of manufacturing a solid-state imaging device provided with a well formed by embedding a high refractive index layer in a low refractive index layer, forming the low refractive index layer so as to cover a surface, and forming the low refractive index layer on the low refractive index layer Forming the well by forming an opening and embedding the high refractive index layer in the opening a plurality of timesTo do.
[0026]
According to the method for manufacturing a solid-state imaging device of the present invention, the opening is formed in the low refractive index layer, and the step of embedding the high refractive index layer in the opening is performed a plurality of times to form the well. It is possible to embed the high refractive index layer satisfactorily by reducing the depth of the film. This eliminates cavities in the embedded high refractive index layer.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
As an embodiment of the present invention, FIG. 1 shows a schematic configuration when the present invention is applied to a CMOS solid-state imaging device (CMOS sensor).
In the illustrated example, a cross section corresponding to one pixel of the CMOS type solid-state imaging device is shown.
In the CMOS type solid-state imaging device 1 according to the present embodiment, a light receiving sensor unit 4 that receives incident light is formed in a predetermined region in the semiconductor substrate 2 separated by the element isolation region 3. At a predetermined position, a transfer gate 6 and a conductive plug 7 connected to a wiring layer described later are formed in the interlayer insulating film 8 through the insulating film 5.
[0028]
In the illustrated example, the wiring layer 9 is formed in two layers (a first wiring layer 91 and a second wiring layer 92), and the wiring layers 91 and 92 are connected by a conductive plug 7. Above the uppermost wiring layer 92, a color filter 12 is formed on the interlayer insulating film 8 via a passivation film 10 and a planarizing film 11, and at a position corresponding to the light receiving sensor unit 4 on the color filter 12. An on-chip lens 13 is formed.
[0029]
On the light receiving sensor unit 4, a well 14 is formed up to the lower end of the passivation film 10 so as to connect the light receiving sensor unit 4 and the on-chip lens 13, and a refractive index higher than the interlayer insulating film 8 (in the well 14). A high refractive index layer (for example, a plasma SiN film formed by a high-density plasma CVD method) 15 having n = 2.0) is embedded. Reference numeral 16 denotes an interlayer insulating film (for example, SiO 2₂An etching stop film (for example, a SiN film) having a high selectivity with respect to the film 8).
As a result, the CMOS solid-state imaging device 1 having a structure in which the light collection efficiency of incident light is increased is configured.
[0030]
In this embodiment, in particular, the well 14 is configured by a plurality of layers.
In the present embodiment, the well 14 is configured by two layers 14A and 14B, for example. The upper surface of the layer 14A is formed so as to be flush with the upper surface of the flattened interlayer insulating film 8 indicated by a broken line below the wiring layer 91, for example. Further, the upper surface of the layer 14B is formed so as to be flush with the upper surface of the planarized interlayer insulating film 8 below the passivation film 10, for example.
[0031]
With this configuration, for example, the well 43 is not formed by embedding the high refractive index layer 44 in one deep hole as in the prior art (see FIG. 12), but the high refractive index layer 15 is formed in the hole. Since the well 14 is formed by having a plurality of layers 14A and 14B embedded with, the embedding property of the plasma SiN film 15 in each layer 14A and 14B is better than the embedding property of the conventional plasma SiN film. Thus, no cavities are generated in the plasma SiN film 15.
[0032]
By the way, since the well 14 is formed of the plurality of layers 14A and 14B in this way, there is a concern about a problem of displacement between layers, for example.
For example, when a resist mask for forming the second layer 14B is formed by using the lithography technique, when an overlay shift occurs with the first layer 14A, an enlarged view of the vicinity of the interlayer is shown in FIG. As shown, a step 21 is formed at the connecting portion 20 of the layers 14A and 14B on the side walls of the layers 14A and 14B that are continuous in the vertical direction.
[0033]
As described above, when the step 21 is formed in the connection portion 20 between the layers 14A and 14B, for example, light (arrow X in the figure) incident from the upper portion of the well 14 is a plasma SiN film embedded in the inside. 15 enters the interlayer insulating film 8, so that depending on the incident angle, the light is refracted at the step 21 and proceeds into the interlayer insulating film 8 (arrow Y in the figure), or the light is totally reflected at the step 21. Then, it proceeds upward in the well 14 and diffuses from the surface to the outside (arrow Z in the figure). Alternatively, the light is totally reflected again at the interface between the surface of the well 14 and the upper layer (for example, the passivation film 10), and returns to the well 14 again.
Thus, it is clear that the formation of the step 21 reduces the light condensing property of the incident light to the light receiving sensor unit 4 and decreases the light condensing efficiency.
[0034]
Therefore, in the present embodiment, the diameters of the adjacent layers 14A and 14B are made different. That is, as shown in FIG. 3, the lower diameter Bd of the upper layer 14B is formed smaller than the upper diameter Ad of the lower layer 14A. Thereby, the fall of the condensing efficiency mentioned above can be improved.
In this case, although the connecting portion 20 has a step, the upper diameter Ad of the lower layer is wider in the connecting portion 20, so that unnecessary reflection or refraction as shown in FIG. 2 does not occur.
[0035]
In this way, in order to form the lower diameter Bd of the upper layer 14B smaller than the upper diameter Ad of the lower layer 14A, the mask diameter may be reduced accordingly. At this time, since the maximum amount of deviation that occurs in the lithography process is about 0.1 μm, the lower diameter Bd is smaller than the upper diameter Ad of the lower layer 14A, for example, in the lithography process when forming the upper layer 14B. ... 2 μm (0.1 × 2) may be controlled.
Thereby, the level | step difference 21 which arises in the connection part 20 between each layer 14A, 14B as mentioned above can be avoided.
[0036]
According to the solid-state imaging device 1 of the present embodiment, for example, a high refractive index layer 15 is buried in a hole, instead of a well formed by embedding a high refractive index layer in one deep hole as in the prior art. Since the well 14 is formed by having a plurality of layers 14A and 14B, the embedding property of the plasma SiN film 15 in each of the layers 14A and 14B is similar to the embedding property of the plasma SiN film in one conventional layer 47. It is better than that. Thereby, it is possible to provide a solid-state imaging device having a well with good filling property in which no cavity is generated in the plasma SiN film 15.
[0037]
Moreover, since the lower diameter Bd of the upper layer 14B is formed smaller than the upper diameter Ad of the lower layer 14A between the layers 14A and 14B (connection portion 20), unnecessary reflection and refraction do not occur in the connection portion 20. It is possible to provide a solid-state imaging device in which light collection efficiency is not reduced.
[0038]
Further, in order to reduce the interface state in the light receiving sensor unit 4 or repair the disorder of the crystal lattice and suppress the generation of white spots, for example, hydrogen contained in the plasma SiN film 15 is removed by annealing treatment. When supplying the light receiving sensor unit 4, the plasma SiN film 15 in the well 14 does not have a cavity and has a sufficient volume. Therefore, a sufficient amount of hydrogen is supplied from the plasma SiN film 15 to the light receiving sensor unit 4. And the effect of suppressing the occurrence of white spots can be sufficiently exhibited.
[0039]
In addition, when a cavity is formed in the well, the coverage of the high refractive index layer in the well is poor and the high refractive index layer is easily peeled off. Therefore, the coverage of the high refractive index layer 15 in the well 14 can be improved.
[0040]
In the above-described embodiment, the side wall of at least one of the plurality of layers 14A and 14B constituting the well 14 may be formed in a tapered shape.
For example, as shown in FIG. 4, in the above-described embodiment, when the side wall of the uppermost layer 14B is tapered, the light is introduced into the well 14 as compared with the configuration shown in FIG. Can be easily incorporated. Further, the embedding property of the plasma SiN film 15 in the layer 14B is further improved.
[0041]
In the above-described embodiment, the well 14 is formed by the two layers 14A and 14B. However, as another embodiment, the well 14 is formed by, for example, three layers 14A, 14B, and 14C. The configuration is shown in FIG.
In the present embodiment, for example, the upper surfaces of the respective layers 14A, 14B, and 14C are flush with the upper surface of the flattened interlayer insulating film 8 indicated by a broken line below the first wiring layer 91, and the second wiring layer 92. It is formed so as to be flush with the upper surface of the flattened interlayer insulating film 8 indicated by the lower broken line and flush with the upper surface of the flattened interlayer insulating film 8 below the passivation film 10. That is, the upper surface of each layer 14A, 14B, 14C and the flattened upper surface of the interlayer insulating film 8 are formed on the same surface.
Since the other parts are the same as those in FIG. 1, the corresponding parts are denoted by the same reference numerals, and redundant description is omitted.
[0042]
In the case of such a configuration, the layers 14B and 14C become shallow and the embedding property of the plasma SiN film 15 in each layer 14B and 14C is improved. Therefore, in the well 14 as compared with the configuration shown in FIG. Improves embedability.
[0043]
Further, for example, as shown in FIG. 6, in the configuration shown in FIG. 5 described above, when the side walls of the layers 14B and 14C are each tapered, in addition to the above-described operational effects, the light receiving sensor unit 4 starts the on-chip lens It is possible to prevent the diameters (upper diameters) of the layers 14A, 14B, and 14C formed upward to 13 from gradually decreasing. Further, the embedding property of the plasma SiN film 15 in the layers 14B and 14C is improved, and further, the embedding property in the well 14 is improved.
[0044]
Next, an embodiment of a method for manufacturing a solid-state imaging device according to the present invention will be described with reference to FIGS.
In the present embodiment, a method for manufacturing the CMOS solid-state imaging device shown in FIG. 1 will be described. In the illustrated example, a cross-sectional view corresponding to one pixel of the CMOS type solid-state imaging device is shown, and the same reference numerals are given to the portions corresponding to FIG. First, as shown in FIG. 7A, a light receiving sensor unit 4 that receives incident light is formed in a predetermined region (element forming region) in the semiconductor substrate 2 separated by the element isolation region 3. Then, the insulating film 5 is formed.
[0045]
Next, as shown in FIG. 7B, a transfer gate 6 and an etching stopper film 16 are formed on the light receiving sensor portion 4 via an insulating film 5.
Here, as the etching stopper film 16, when the opening 141 is formed in the interlayer insulating film 8 on the next etching stopper film 16, SiO 2₂A SiN film that can ensure a high etching selectivity with respect to the interlayer insulating film 8 made of a film is used. This SiN film can be formed by using, for example, a low pressure CVD method.
[0046]
  Next, an interlayer insulating film 8 is formed on the entire surface including the transfer gate 6, the etching stopper film 16, and the element isolation region 2, and a resist film (not shown) is further formed on the interlayer insulating film 8. Then, after forming a resist film on a resist mask having a pattern for forming the opening 141 using a known lithography technique, the interlayer insulating film 8 is removed by anisotropic dry etching through this resist mask.
  After that, by removing the resist mask, an opening 141 is formed in the interlayer insulating film 8 as shown in FIG. 7C.
  Anisotropic dry etching is processed with a parallel plate type etcher.C ₄ F ₈ gasAr gas,O ₂ gasEtc. can be used. When such a reactive gas is used, a high selection ratio can be secured between the interlayer insulating film 8 and the etching stopper film 16.
[0047]
At this time, as described above, since the etching stopper film 16 formed on the light receiving sensor portion 4 has a high selection ratio with the interlayer insulating film 8, the etching of the interlayer insulating film 8 is performed with the etching stopper film. It stops when it reaches 16 and does not affect the surface of the light receiving sensor unit 4. Further, for example, the depth 14Ah of the opening 141 can be uniformly formed for each pixel without variation.
As a result, since the opening 141 is formed before the wiring layer 9 described later is formed, the depth 14Ah of the opening 141 is reduced compared to the case where the opening is formed after all the wiring layers are formed. It can be formed shallow. That is, an opening 141 having a low aspect ratio is formed.
[0048]
Next, as shown in FIG. 8D, after the etching stopper film 16 exposed in the opening 141 is removed by, for example, isotropic dry etching, the interlayer insulating film is formed on the front surface of the interlayer insulating film 8 including the opening 141. A high refractive index layer 15 having a refractive index higher than 8, for example, a SiN film (plasma SiN film) 15 by a high density plasma CVD method is formed.
For isotropic etching when removing the etching stopper film 16, for example, chemical dry etching using downflow plasma can be used.
At this time, since the depth 14Ah of the opening 141 is shallow as described above, the plasma SiN film can be satisfactorily embedded without forming a cavity in the opening 141.
[0049]
Next, as shown in FIG. 8E, the plasma SiN film 15 is etched away to the surface of the interlayer insulating film 8 by using, for example, a CMP method or an etch back method.
At this time, it is necessary to perform etching removal so that the plasma SiN film 15 does not remain on the interlayer insulating film 8. This is because, when the plasma SiN film 15 remains on the interlayer insulating film 8, there is a possibility that incident light may be reflected in the plasma SiN film 15 and enter an adjacent pixel to be affected.
Here, for example, when the plasma SiN film 15 is removed by etching using the CMP method, the upper surface of the interlayer insulating film 8 is flattened without the plasma SiN film 15 remaining. There is no need to perform the planarization process again when forming the layer.
Thereby, the layer 14A in which the plasma SiN film 15 is embedded is formed.
[0050]
Next, as shown in FIG. 9F, the conductive plug 7 and the wiring layer 9 are formed.
First, the conductive plug 7 is formed at a predetermined position in the interlayer insulating film 8, and the wiring layer 91 as the first layer is formed on the planarized interlayer insulating film 8. Then, the interlayer insulating film 8 is formed again on the entire surface including the wiring layer 91, and after performing the planarization process, the conductive plug 7 is formed at a predetermined position, and the second layer wiring on the interlayer insulating film 8 is formed. Layer 92 is formed. Then, the interlayer insulating film 8 is formed again on the entire surface including the wiring layer 92, and the interlayer insulating film 8 is planarized. In this way, the wiring layer 9 (first wiring layer 91 and second wiring layer 92) having a two-layer structure is formed.
In the present embodiment, the wiring layer 9 has a two-layer structure. For example, when the number of the wiring layers 9 is increased to three, four, five, six, seven, and so on, such a process is performed. Is repeated.
[0051]
Next, a resist film (not shown) is formed on the interlayer insulating film 8, and the resist film is formed on a resist mask having a pattern for forming the opening 142 by using a lithography technique.
At this time, the pattern for forming the opening 142 corresponds to, for example, a shift amount (maximum 0.2 μm) in the lithography process, and the lower opening 141 whose lower diameter 14Bd is formed in the previous process (see FIG. 7C). It is formed to be smaller than the upper diameter 14Ad.
Here, there is a difference of about 0.2 μm between the opening diameters of the openings 141 and 142. Since the difference is as small as 0.2 μm in this way, for example, the resist mask used when forming the opening 141 is used. The same mask pattern can be used. That is, the opening diameter can be adjusted only by control in the lithography process.
Then, the interlayer insulating film 8 is removed by anisotropic dry etching through this resist mask.
Thereafter, by removing the resist mask, an opening 142 is formed in the interlayer insulating film 8 as shown in FIG. 9G.
[0052]
  At this time, the plasma SiN film 15 in the lower layer 14A functions as an etching stopper. This is the same as described above as a reactive gas used for anisotropic dry etching.C ₄ F ₈ gasAr gas,O ₂ gasThis is because a high selection ratio is ensured between the plasma SiN film 15 in the layer 14A and the interlayer insulating film 8 to be etched. Thereby, the surface of the plasma SiN film 15 in the layer 14A is not affected.
  In addition, since the lower diameter of the upper opening 142 is formed smaller than the upper diameter of the lower opening 141 between the openings (connecting portion 20), for example, a resist in the lithography process when forming the opening 142 is formed. Even if an overlay shift occurs between the opening pattern of the mask and the lower opening 142, the lower diameter 14Bd of the upper opening 142 does not protrude from the upper diameter 14Ad of the lower opening 141. The insulating film 8 is not partially etched.
  Also in this case, as described above, the depth 14Bh of the opening 142 can be formed as shallow as the opening 14A is formed in the previous stage.
[0053]
Next, as shown in FIG. 10H, a high refractive index layer having a higher refractive index than the interlayer insulating film 8 is formed on the front surface of the interlayer insulating film 8 including the opening 142. Also in this step, similarly to the case shown in FIG. 8D, a SiN film (so-called plasma SiN film) 15 is formed by, for example, a high-density plasma CVD method. Also in this case, since the opening 142 is shallow as described above, the plasma SiN film can be satisfactorily embedded in the opening 142.
[0054]
Next, as shown in FIG. 10I, the plasma SiN film 15 is etched away to the surface of the interlayer insulating film 8 by using a CMP method or an etch back method. Also in the planarization process, the plasma SiN film 15 is not left on the interlayer insulating film 8 as described above.
Also in this case, for example, when the plasma SiN film 15 is removed by etching using the CMP method, the upper surface of the interlayer insulating film 8 is planarized without the plasma SiN film 15 remaining. When the wiring layer is formed in the process, it is not necessary to perform the planarization process again.
Thereby, the layer 14B in which the plasma SiN film 15 is embedded is formed. Then, the well 14 is formed together with the previously formed lower layer 14A.
[0055]
Next, as shown in FIG. 11, a passivation film 10 is formed over the entire surface of the interlayer insulating film 8 and the plasma SiN film 15 embedded in the well 14, and the planarizing film 11 is formed on the passivation film 10. After the formation, the color filter 12 is formed. Then, an on-chip lens 13 is formed on the color filter 12 at a position corresponding to the well 14 on the light receiving sensor unit 4.
In this way, a CMOS solid-state imaging device having the structure shown in FIG. 1 can be formed.
[0056]
According to the method of manufacturing the image sensor according to the present embodiment described above, the process of forming the openings 141 and 142 in the interlayer insulating film 8 and embedding the plasma SiN film 15 in each of the openings 141 and 142 is performed a plurality of times. Since the well 14 is formed, for example, the respective depths 14Ah and 14Bh of the formed openings 141 and 142 are set to be the same as that of the openings formed once (for example, after all the wiring layers are formed). It can be formed shallower than the depth h. That is, it is possible to form an opening having a lower aspect ratio than in the prior art.
Thereby, when the plasma SiN film 15 having a high refractive index is embedded in each of the openings 141 and 142 using the plasma CVD method, the plasma SiN film 15 can be embedded satisfactorily.
[0057]
In addition, since the lower diameter 14Bd of the opening 142 formed in the next process is formed smaller than the upper diameter 14Ad of the opening 141 formed in the previous process, unnecessary reflection is caused in the connection portion 20 of the openings 141 and 142. Or refraction can be prevented.
[0058]
In the above-described embodiment, the side wall of at least one opening can be formed in a tapered shape.
For example, when the side wall of the opening 142 formed at the top is tapered, in the process shown in FIG. 9G, for example, the exposure conditions are adjusted when forming a resist pattern for forming the opening 142 using the lithography technique. This can be realized by etching the resist pattern to have a tapered shape. At this time, if C4F8 gas is used, a good taper shape can be easily formed due to the sidewall protective film forming effect of the CF-based buried material.
[0059]
Further, as described above, when the plasma SiN film 15 on the interlayer insulating film 8 is removed by, for example, the CMP method, the planarization process for the interlayer insulating film 8 and the plasma SiN film 15 is performed once. Can do.
[0060]
In the above-described embodiment, the well 14 is formed by forming the opening in two steps. However, depending on the balance of the embedding property, the number of wiring layers, the depth, and the like, the well 14 is divided into three or more times. An opening can also be formed.
When the wells 14 are formed by dividing the number of times, the burying property of the plasma SiN film 15 in each opening is further improved.
[0061]
In the above-described embodiment, the case where the present invention is applied to a CMOS solid-state imaging device has been described. However, the present invention can also be applied to other solid-state imaging devices such as a CCD solid-state imaging device.
[0062]
The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.
[0063]
【The invention's effect】
According to the solid-state imaging device of the present invention, since a well in which a high refractive index layer is satisfactorily embedded can be formed, the embedding property, covering property, etc. of the high refractive index layer in the well as compared with the conventional case. Is significantly improved, and a solid-state imaging device with improved reliability can be provided.
[0064]
In addition, since unnecessary reflection and refraction do not occur at the connection part, incident light can be guided into the light receiving sensor part without leaking, and the light collection efficiency and sensitivity characteristics are further improved compared to the conventional case. A solid-state imaging device can be provided.
[0065]
In addition, when the side wall of at least one layer among the plurality of layers of the well is tapered, incident light can easily enter the well, and the light collection efficiency is further improved.
[0066]
According to the method for manufacturing a solid-state imaging device of the present invention, it is possible to satisfactorily embed the high refractive index layer by reducing the depth of each opening. Thereby, a solid-state imaging device having high light collection efficiency can be manufactured.
[0067]
In addition, when the lower diameter of the upper opening is made smaller than the upper diameter of the lower opening formed in the previous step, there is no stepped portion that causes unnecessary reflection or refraction, so the light collection efficiency and sensitivity A solid-state imaging device with improved characteristics can be manufactured.
[0068]
Furthermore, when the side wall of at least one opening is formed in a tapered shape, light can be easily taken into the well, so that the light collection efficiency can be further improved.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing a configuration of a solid-state imaging device according to the present invention.
FIG. 2 is an enlarged cross-sectional view illustrating a problem that occurs between layers.
FIG. 3 is an explanatory diagram for defining the diameter of each layer between layers.
4 is a schematic cross-sectional view showing a case where the upper side wall of the well has a tapered shape in the configuration shown in FIG. 1;
5 is a schematic cross-sectional view showing a case where a well is formed of three layers in the configuration shown in FIG.
6 is a schematic cross-sectional view showing a case in which the side walls of two layers are tapered in the configuration shown in FIG.
FIGS. 7A to 7C are manufacturing process diagrams (part 1) illustrating a method for manufacturing a solid-state imaging device according to the present invention. FIGS.
FIGS. 8A to 8E are manufacturing process diagrams (part 2) illustrating the manufacturing method of the solid-state imaging device according to the present invention. FIGS.
FIGS. 9A to 9G are manufacturing process diagrams (part 3) illustrating the method for manufacturing the solid-state imaging device according to the present invention. FIGS.
FIG. 10 is a manufacturing process diagram (part 4) illustrating the method for manufacturing the solid-state imaging device according to the present invention.
FIG. 11 is a manufacturing process diagram (part 5) illustrating the manufacturing method of the solid-state imaging device according to the invention;
FIG. 12 is a schematic cross-sectional view showing a configuration of a conventional solid-state imaging device.
FIGS. 13A to 13C are manufacturing process diagrams (part 1) showing a conventional method for manufacturing a solid-state imaging device; FIGS.
FIGS. 14A to 14E are manufacturing process diagrams (part 2) illustrating a conventional method for manufacturing a solid-state imaging device; FIGS.
FIGS. 15A to 15G are manufacturing process diagrams (part 3) illustrating a conventional method for manufacturing a solid-state imaging device; FIGS.
FIG. 16 is an explanatory diagram for explaining a conventional problem.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Solid-state image sensor, 2 ... Semiconductor substrate, 3 ... Element isolation region, 4 ... Light-receiving sensor part, 5 ... Insulating film, 6 ... Transfer gate, 7 ... Conductivity Plugs, 8 ... interlayer insulating film, 9 (91, 92) ... wiring layer, 10 ... passivation film, 11 ... flattening film, 12 ... color filter, 13 ... on-chip Lens, 14 ... well, 141, 142 ... opening, 14A, 14B ... layer, 15 ... high refractive index layer (plasma SiN film), 20 ... connection, 21 ... step Part

Claims (5)

On the light receiving sensor unit, the incident light to be condensed on the light receiving sensor section by total reflection at the interface between the high refractive index layer and a low refractive index layer, wherein said high refractive index layer in the low refractive index layer There is a buried well,
The well is composed of a plurality of layers having different diameters,
A solid-state imaging device, wherein in the layers adjacent to each other among the plurality of layers, the lower diameter of the upper layer is formed smaller than the upper diameter of the lower layer.   The solid-state imaging device according to claim 1, wherein a side wall of at least one of the plurality of layers is formed in a tapered shape. On the light receiving sensor unit, the incident light to be condensed on the light receiving sensor section by total reflection at the interface between the high refractive index layer and a low refractive index layer, wherein said high refractive index layer in the low refractive index layer A method of manufacturing a solid-state imaging device provided with a buried well,
The well is formed by forming the low refractive index layer so as to cover a surface, forming an opening in the low refractive index layer, and embedding the high refractive index layer in the opening a plurality of times. A method for manufacturing a solid-state imaging device.   4. The method of manufacturing a solid-state imaging device according to claim 3, wherein, in the plurality of steps, the lower diameter of the opening formed in the next step is made smaller than the upper diameter of the opening formed in the previous step.   4. The method of manufacturing a solid-state imaging device according to claim 3, wherein a side wall of at least one of the openings formed in the plurality of steps is tapered.

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