JP2008210975A - Solid-state image pickup device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state image pickup device having a high waveguide effect and capable of easily forming the waveguide, and to provide its manufacturing method. <P>SOLUTION: The solid-state image pickup device comprises a plurality of pixels 50; a multilayer interconnection layer 54 with an interconnection 53 of a plurality of layers formed on the plurality of pixels 50 through an interlayer insulating film 52; and a waveguide 65 for guiding an incident light to a photoelectric converting unit PD of the pixel. The waveguide 65 has a core part of a first layer 63 having the predetermined refractive index regulated by a canopy part 61a formed at the multilayer interconnection layer 54, and a clad part of a void layer 64 formed between the first layer 63 and the multilayer interconnection layer 54. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device having a waveguide for guiding incident light to a photoelectric conversion portion of a pixel and a method for manufacturing the same.

  The solid-state imaging device of the present invention is a solid-state imaging device including a conversion unit that converts a charge generated by photoelectric conversion into a pixel signal in the pixel, that is, a solid-state imaging device including a plurality of pixels including a photoelectric conversion unit and a transistor, For example, a CMOS image sensor. Here, the CMOS image sensor is an image sensor created by applying or partially using a CMOS process. Further, as a form of the solid-state imaging device, it may be configured by one chip or a plurality of chips.

  2. Description of the Related Art In recent years, with the miniaturization of pixels and the increase in the number of pixels in solid-state imaging devices, technological development has been actively conducted to secure and improve sensitivity characteristics, which are important characteristics of solid-state imaging devices. In the solid-state imaging device, a configuration in which a waveguide for effectively guiding incident light to the photoelectric conversion unit of the pixel is provided in order to ensure and improve the sensitivity.

  For example, in Patent Document 1, an interlayer insulating film on a photodiode is removed by etching to form a hole, and a waveguide is formed by embedding a material layer having a higher refractive index than the interlayer insulating film in the side wall of the hole. A CCD solid-state imaging device configured as described above has been proposed. In Patent Document 2, an interlayer insulating film on a photodiode is removed by etching to form a hole, a low refractive index material layer is thinly formed on the sidewall of the hole, and then a high refractive index material layer is formed. A CMOS solid-state imaging device has been proposed which is embedded to form a waveguide. In Patent Document 3, an interlayer insulating film on a photodiode is removed by etching to form a hole, and a highly reflective material layer is formed thinly on the sidewall of the hole, and then a material layer with high transmittance is embedded. A CMD solid-state imaging device is proposed in which a waveguide is formed.

Japanese Patent Laid-Open No. 2003-298034 JP 2006-32705 A JP-A-7-45805

  By the way, in the solid-state imaging device, the above-described waveguide is formed on the photodiode which is a photoelectric conversion unit, so that incident light can be efficiently guided to the photodiode and high sensitivity can be achieved. However, in the configuration of Patent Document 1, since the waveguide effect is influenced by the refractive index of the interlayer insulating film, there is a possibility that the characteristics are deteriorated as compared with the waveguide configurations of Patent Documents 2 and 3. In the case of the configuration of Patent Document 2, it is difficult to form a low refractive index material layer thinly on the side wall of the hole when the pixel cell is miniaturized and the opening at the time of etching is narrowed. Further, it may be difficult to embed a high refractive index material layer thereafter, and it may be difficult to form a waveguide structure. Furthermore, in the case of the configuration of Patent Document 3, as in Patent Document 2, if the pixel cell is miniaturized, it may be difficult to form a waveguide structure. In addition, when the highly reflective material layer is formed on the side wall of the hole extracted by etching, the film is also formed on the bottom side, so that the number of steps for removing it increases.

  In view of the above, the present invention provides a solid-state imaging device having a high waveguide effect and facilitating the formation of a waveguide, and a method for manufacturing the same.

  The solid-state imaging device according to the present invention guides incident light to a plurality of pixels, a multilayer wiring layer in which a plurality of wirings are formed above the plurality of pixels via an interlayer insulating film, and a photoelectric conversion unit of the pixels. The waveguide has a waveguide, and the waveguide is formed between the first layer and the multilayer wiring layer, with the first layer having a required refractive index regulated by the eaves formed in the multilayer wiring layer as the core. The air gap layer is configured as a clad portion.

  In the solid-state imaging device of the present invention, the first layer restricted by the eaves formed in the multi-layer wiring layer is used as the core above the pixel, and the space between the first layer and the multi-layer wiring layer receding from the eaves A waveguide having the gap layer as a cladding portion is formed. Since the clad portion of this waveguide is formed of a gap layer, extremely good waveguide characteristics can be obtained regardless of the refractive index of the rough insulating film of the multilayer wiring layer.

  The method for manufacturing a solid-state imaging device according to the present invention includes a step of forming a multilayer wiring layer in which a plurality of layers of wirings are formed above a plurality of pixels via an interlayer insulating film and has an eaves portion forming material layer. A step of selectively forming an opening recess having a required depth in a portion of the multilayer wiring layer corresponding to the photoelectric conversion portion constituting the pixel, and wet etching the interlayer insulating film on the side wall of the opening recess to form the opening recess The first refractive index regulated by the eaves part is formed so that a gap layer is formed between the step of forming the eaves part from the eaves part forming material and the side wall of the interlayer insulating film in the opening recess. And a step of forming a waveguide having the first layer as a core portion and the air gap layer as a cladding portion.

  In the manufacturing method of the solid-state imaging device of the present invention, after forming the eaves portion forming material layer in the multilayer wiring layer and forming the opening recess, the interlayer insulating film is wet etched to form the eaves portion by the eaves portion forming material layer. Next, a first layer serving as a core is formed in the opening recess. In the embedding of the first layer into the opening concave portion, the embedding portion restricts the embedding portion to prevent the embedding into the over-etched portion by wet etching, thereby forming a void layer. A waveguide is easily formed by the gap layer and the first layer. In addition, a waveguide is formed with one type of embedding material.

  According to the present invention, it is possible to provide a solid-state imaging device having a high waveguide effect and easily forming a waveguide and a method for manufacturing the same.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows an overall schematic configuration of an embodiment of a solid-state imaging device according to the present invention, that is, a CMOS solid-state imaging device (image sensor). The solid-state imaging device 1 according to the present embodiment includes an imaging region 3 in which pixels 2 including a plurality of photoelectric conversion units are regularly arranged in a two-dimensional array on a semiconductor substrate 100 such as a silicon substrate, and its peripheral circuit And a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

  The control circuit 8 generates a clock signal, a control signal, and the like that serve as a reference for operations of the vertical drive circuit 4, the column signal processing circuit 5, and the horizontal drive circuit 6 based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. These clock signals and control signals are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.

  The vertical drive circuit 4 is configured by, for example, a shift register, and selectively scans each pixel 2 in the imaging region 3 in the vertical direction sequentially in units of rows, and receives light at a photoelectric conversion unit (photodiode) 31 of each pixel through the vertical signal line 9. A pixel signal based on the signal charge generated according to the quantity is supplied to the column signal processing circuit 5.

  The column signal processing circuit 5 is arranged, for example, for each column of the pixels 2, and a signal output from the pixels 2 for one row is formed for each pixel column in a black reference pixel (not shown, but around the effective pixel region). Signal processing such as CDS and signal amplification for removing fixed pattern noise unique to the pixel 2 is performed by the signal from At the output stage of the column signal processing circuit 5, a horizontal selection switch (not shown) is provided connected to the horizontal signal line 10.

The horizontal driving circuit 6 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, and outputs a pixel signal from each of the column signal processing circuits 5 to the horizontal signal line. 10 to output.
The output circuit 7 performs signal processing and outputs the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10.

  FIG. 2 is an equivalent circuit of an example of the pixel 2. The pixel 2 includes, for example, a photodiode (PD) 21 constituting a photoelectric conversion unit and a plurality of MOS transistors. The plurality of MOS transistors include, for example, a transfer transistor 22, a reset transistor 23, an amplifying transistor 24 that converts charges generated by the photodiode 21 into a pixel signal, and a selection transistor 25.

  The photodiode 21 photoelectrically converts the photoelectric charge (here, electrons) having a charge amount corresponding to the received light amount. The cathode of the photodiode 21 is connected to the gate of the amplifying transistor 24 via the transfer transistor 22. A node electrically connected to the gate of the amplifying transistor 24 is referred to as a floating diffusion portion FD. The floating diffusion portion FD is composed of the drain of the transfer transistor 22.

  The transfer transistor 22 is connected between the cathode of the photodiode 21 and the floating diffusion portion FD. In the transfer transistor 22, the gate pulse φTRG is applied to the gate of the transfer transistor 22 via the transfer wiring 27, so that the gate is turned on, and the charge of the photodiode 21 is transferred to the floating diffusion portion FD.

  The reset transistor 23 has a drain connected to the pixel power supply (Vdd) line 26 and a source connected to the floating diffusion portion FD. The reset transistor 23 is turned on by applying a reset pulse φRST to the gate via the reset wiring 27, and prior to the transfer of the signal charge from the photodiode 21 to the floating diffusion portion FD, the floating transistor 23 is turned on. By discarding the charge of the fusion portion FD to the pixel power supply line 26, the floating diffusion portion FD is reset.

  The amplifying transistor 24 has a gate connected to the floating diffusion portion FD and a drain connected to the pixel power supply line 26. In the amplifying transistor 24, the potential of the floating diffusion portion FD after being reset by the resetting transistor 23 is output as a reset level, and further, the signal charge is transferred by the transfer transistor 22 in the floating diffusion portion FD. The potential is output as a signal level.

  The selection transistor 25 has, for example, a drain connected to the source of the amplification transistor 24 and a source connected to the vertical signal line 30. The selection transistor 25 is turned on when a selection pulse φSEL is applied to the gate via the selection wiring 29, and the signal output from the amplification transistor 24 is relayed to the vertical signal line 30 with the pixel 2 being selected. .

  The horizontal wiring, that is, the reset wiring 27, the transfer wiring 28, and the selection wiring 29 are common to the pixels in the same row and are controlled by the vertical drive circuit 4.

  Note that the selection transistor 25 may have a circuit configuration connected between the pixel power supply wiring 26 and the drain of the amplification transistor 24. In the above example, a four-transistor pixel configuration is used, but in addition, a selection transistor may be omitted to form a three-transistor pixel configuration.

  In this embodiment, the waveguide structure that guides incident light to the photodiode, which is a photoelectric conversion unit, uses the eaves provided in the multilayer wiring, and simultaneously with the formation of the core portion having the required refractive index, the gap layer It is characterized by forming and forming a clad portion.

  FIG. 3 shows a first embodiment of a CMOS solid-state imaging device according to the present invention. This figure is a schematic cross-sectional view of the main part of the imaging region of the CMOS solid-state imaging device. The CMOS solid-state imaging device 111 according to the present embodiment has a first conductivity type, for example, an n-type charge storage region 32 and a second conductivity type p-type semiconductor region (p-type accumulator) on the main surface of the semiconductor substrate 100. A photodiode PD is formed by the (simulation layer) 33, and a plurality of MOS transistors are formed. FIG. 3 shows a transfer transistor Tr1 and a reset transistor Tr2 among a plurality of MOS transistors. The transfer transistor Tr1 includes an n-type semiconductor region 45 serving as a floating diffusion portion FD, a photodiode PD, and a transfer gate electrode 46 formed through a gate insulating film. The reset transistor Tr2 includes an n-type semiconductor region 45 serving as a floating diffusion portion FD, an n-type semiconductor region 47, and a reset gate electrode 48 formed through a gate insulating film. The unit pixel 50 is separated from adjacent pixels in the element isolation region 49.

  On the semiconductor substrate 100 on which the pixels are formed, a so-called multilayer wiring layer 54 is formed in which wirings 53 [531, 532, 533] made of a plurality of layers, in this example, three layers are formed via an interlayer insulating film 52. It is formed. The interlayer insulating film 52 can be formed of a material such as SiO, for example. The wiring 53 is formed except for a region corresponding to the photodiode PD. A color filter 56 is formed on the multilayer wiring layer 54 via a planarizing film 55, and an on-chip microlens 58 is further formed thereon via a planarizing film 57.

  In the first embodiment, an opening recess 62 is formed in the multilayer wiring layer 54 at a position corresponding to each photodiode PD, and a first refractive index having a required refractive index that becomes a core portion embedded in the opening recess 62 is formed. A waveguide 65 is formed by the layer 63 and a void layer (air layer) 64 serving as a cladding formed around the first layer 63. The first layer 63 can be formed of a material such as SiN or SiC, for example.

  That is, in this embodiment, the wirings 531 to 533 of each layer are formed of Cu wirings, and the diffusion prevention film 61 that prevents the diffusion of Cu wirings is formed in contact with the upper surfaces of the Cu wirings 531 to 533 of each layer. The diffusion prevention film 61 is formed on the entire surface of the multilayer wiring layer 54 except for the opening recess 62. Further, the diffusion preventing film 61 is formed such that an end portion thereof becomes an eave portion 61 a protruding into the opening recess 62. The eaves 61a is formed by forming the opening recess 62, and then performing so-called over-etching by removing the interlayer insulating film 52 on the sidewall of the opening recess 62 by a required width by wet etching using the diffusion prevention film 61 as a mask. Is done. The first layer 63 is embedded in the opening recess 62 so as to be regulated by the eaves portion 61a of each layer. By restricting the first layer 63 by the eaves portion 61 a, a gap layer 64 is formed between the first layer 63 and the side wall of the over-etched interlayer insulating film 52.

  The first layer 63 is formed of an insulating layer that is transparent (light transmissive) and has a high refractive index. Since the refractive index of the air gap layer 64 is 1, the refractive index of the first layer 63 is higher than that of the air gap layer 64 regardless of the material selected, and a waveguide can be formed. Although not shown, when the Cu wiring 53 is used, a barrier film that prevents diffusion of the Cu wiring is formed on the lower surface and the side surface of the Cu wiring 53. In the over-etching of the side wall of the opening recess 62, the etching is performed up to the vicinity of the barrier film.

  Next, an embodiment of a method for manufacturing the CMOS solid-state imaging device 111 according to the first embodiment will be described with reference to FIGS. In each figure, for easy understanding of the present invention, the pixel is represented only by the photodiode PD and is schematically shown with the MOS transistor omitted. The same applies to drawings showing manufacturing methods of other embodiments described later.

  First, as shown in FIG. 4A, on the main surface side of the semiconductor substrate 100, a plurality of pixels composed of photodiodes PD and a plurality of MOS transistors (not shown) are formed in a two-dimensional array. Thereby, an imaging region is formed. Next, a multilayer wiring layer 54 in which an interlayer insulating film 52 made of, for example, a silicon oxide film (SiO 2) or the like, a Cu wiring 53, and a Cu wiring diffusion prevention film 61 are repeatedly formed in multiple layers on the surface of the semiconductor substrate 100 where the pixels are formed. Form. The Cu wiring 53 [531, 532, 533] is formed so as to avoid the region facing the photodiode PD. The diffusion prevention film 61 can be formed of a multi-SiN film or a SiC film, and is formed over the entire surface of the multilayer wiring layer 54. Although not shown, a barrier layer that prevents diffusion of Cu wiring is formed on the lower surface and side surfaces of the Cu wiring 53 as needed.

  Next, as shown in FIG. 4B, a resist mask (not shown) is formed in a region other than the position corresponding to the photodiode PD on the multilayer wiring layer 54 including the diffusion prevention film 61 using a lithography technique. The opening portion 62 is formed by selectively etching the multilayer wiring layer 54 including the diffusion prevention film 61 by an etching method. That is, the opening recess 62 is formed in the multilayer wiring layer 54 at a position corresponding to each photodiode PD.

  Next, as shown in FIG. 4C, wet etching is performed using an etching solution (chemical solution) having a selection ratio between the diffusion preventing film 61 and the interlayer insulating film 52, that is, an etching solution for etching the interlayer insulating film 52. Then, an over-etched portion 62a having a required width is formed on the side wall of the opening recess 62. Due to the formation of the over-etching portion 62 a, the eaves portion 61 a of the diffusion prevention film 61 is formed so as to protrude into the opening recess 62.

  Next, as illustrated in FIG. 5D, an insulating material layer 63 </ b> A having a high light transmittance and a required refractive index (preferably a high refractive index) is formed so as to fill the opening recess 62. The embedding of the insulating material layer 63A is restricted by the eaves portion 61a of the diffusion prevention film 61, and the overetching portion 62a remains as a gap. That is, the gap layer 64 is formed between the buried insulating material layer 63A and the side wall of the over-etched portion 62a. The insulating material layer 63A can be formed using, for example, a CVD method with poor embeddability.

  Next, as shown in FIG. 5E, the insulating material layer 63A is planarized by, for example, a CMP (Chemical Mechanical Polishing) method. Here, the insulating material layer 63A can be formed of, for example, a silicon oxide film, a silicon nitride film, or the like. In the case where the embedded insulating material layer 63A has a good leveling property, for example, an organic material is applied and embedded, the leveling step in FIG. 5E is omitted.

  As a result, a waveguide 65 is formed with the first layer 63 made of an insulating material layer as a core portion and the gap layer 64 formed around the first layer 63 as a cladding portion.

  Next, as shown in FIG. 5F, a color filter 56, a planarizing film 57, and an on-chip microlens 58 are sequentially formed through a passivation film 55 serving as a planarizing film. Note that the passivation film 55 is omitted when the insulating material layer 63A serves as a passivation. In this way, the target CMOS solid-state imaging device 111 is obtained.

  According to the CMOS solid-state imaging device 111 according to the first embodiment, total reflection is likely to occur between the gap layer 64 and the embedded high refractive index first layer 63, and waveguide characteristics are obtained. That is, the waveguide 65 is configured by the first layer 63 serving as the core portion and the gap layer 64 serving as the cladding portion. Since the air gap layer 64 is provided, the refractive index of the air gap layer 64 is not affected by the refractive index of the interlayer insulating film 52, and the refractive index of the air gap layer 64 is as low as 1.0, so that a waveguide structure with better waveguide characteristics can be formed. As the material constituting the waveguide 65, only one kind of the first layer 63 embedded in the opening recess 62 is necessary, and the clad portion is a gap, so that in principle, any material is used as the first layer 63. This increases the freedom of material selection and facilitates manufacturing.

  Therefore, the light collection efficiency to the photodiode PD is improved, and a more sensitive CMOS solid-state imaging device can be provided. Even if the pixel cells are miniaturized, the waveguide structure can be easily configured. This CMOS solid-state imaging device 111 is suitable for application to a solid-state imaging device with finer pixels and more pixels.

  In the method of manufacturing the CMOS solid-state imaging device 111 according to the first embodiment, after the opening recess 62 is formed, only the interlayer insulating film 52 on the side wall of the opening recess 62 is selectively overetched by wet etching. 62a is formed, and then the insulating material layer 63A is embedded. In the embedding of the insulating material layer 63A, the eaves portion 61a of the diffusion preventing film 61 prevents the insulating material layer 63A from being embedded in the overetching portion 62a, so that the first layer 63 and the interlayer of the insulating material layer A gap layer 64 is automatically formed between the insulating film 52 and the insulating film 52. A waveguide structure can be formed with one type of material to be embedded. For this reason, the waveguide 65 can be easily formed, and the waveguide can be easily formed even if the pixel cell is miniaturized.

  FIG. 6 shows a second embodiment of the CMOS solid-state imaging device according to the present invention. This figure is a schematic cross-sectional view of the main part of the imaging region of the CMOS solid-state imaging device. The CMOS solid-state imaging device 112 according to the present embodiment has a first conductivity type, for example, an n-type charge storage region 32 and a second conductivity type p-type semiconductor region (p-type accumulator) on the main surface of the semiconductor substrate 100. A photodiode PD is formed by the (simulation layer) 33, and a plurality of MOS transistors are formed. FIG. 3 shows a transfer transistor Tr1 and a reset transistor Tr2 among a plurality of MOS transistors. The transfer transistor Tr1 includes an n-type semiconductor region 45 serving as a floating diffusion portion FD, a photodiode PD, and a transfer gate electrode 46 formed through a gate insulating film. The reset transistor Tr2 includes an n-type semiconductor region 45 serving as a floating diffusion portion FD, an n-type semiconductor region 47, and a reset gate electrode 48 formed through a gate insulating film. The unit pixel 50 is separated from adjacent pixels in the element isolation region 49.

  On the semiconductor substrate 100 on which the pixels are formed, a so-called multilayer wiring layer 54 in which wirings 73 [731, 732, 733] of a plurality of layers, in this example, three layers are formed via an interlayer insulating film 52 is formed. It is formed. The wiring 73 is formed except for a region corresponding to the photodiode PD. A color filter 56 is formed on the multilayer wiring layer 54 via a planarizing film 55, and an on-chip microlens 58 is further formed thereon via a planarizing film 57.

  In the second embodiment, basically, as in the first embodiment, an opening recess 62 is formed in the multilayer wiring layer 54 at a position corresponding to each photodiode PD, and is embedded in the opening recess 62. A waveguide 65 is formed by a first layer 63 having a required refractive index serving as a core and a void layer (air layer) 64 serving as a cladding formed around the first layer 63. .

  In other words, the present embodiment is an example in the case where the diffusion prevention film of the wiring material is not formed. In the present embodiment, each of the wirings 731 to 733 is formed of a metal that does not require a diffusion prevention film, for example, wiring of Al. In the multilayer wiring layer 54, an eaves portion forming material layer 71 is formed. The eaves portion forming material layer 71 may be provided for each wiring 73 layer, or may be provided in one of them, but is preferably provided in at least the uppermost layer of the multilayer wiring layer 54. In this example, an eaves portion forming material layer 71 is formed on the uppermost layer of the multilayer wiring layer 54. The eaves portion forming material layer 71 is formed on the entire surface of the multilayer wiring layer 54 except for the opening recess 62. The eaves part forming material layer 71 can be formed of a material such as SiN or SiC, for example.

  Further, the eaves part forming material layer 71 is formed so that the end part thereof becomes an eave part 71 a protruding into the opening recess 62. The eaves portion 71a is formed by forming the opening recess 62, and then removing the interlayer insulating film 52 on the side wall of the opening recess 62 by a required width by wet etching using the eaves portion forming material layer 71 as a mask, and performing so-called overetching. Formed. The first layer 63 is embedded in the opening recess 62 so as to be regulated by the eaves portion 71a. By restricting the first layer 63 by the eaves portion 71a, a void layer 64 is formed between the first layer 63 and the side wall of the over-etched interlayer insulating film 52.

  The first layer 63 is formed of an insulating layer that is transparent (light transmissive) and has a high refractive index. Since the refractive index of the air gap layer 64 is 1, the refractive index of the first layer 63 is higher than that of the air gap layer 64 regardless of the material selected, and a waveguide can be formed.

  Next, an embodiment of a method for manufacturing the CMOS solid-state imaging device 112 according to the second embodiment will be described with reference to FIGS.

  First, as shown in FIG. 7A, on the main surface side of the semiconductor substrate 100, a plurality of pixels composed of photodiodes PD and a plurality of MOS transistors (not shown) are formed in a two-dimensional array. Thereby, an imaging region is formed. Next, on the surface of the semiconductor substrate 100 where the pixels are formed, an interlayer insulating film 52 made of, for example, a silicon oxide film (SiO 2) or the like, and a multilayer wiring layer 54 in which metal, for example, Al wiring 73 is repeatedly formed in multiple layers are formed. The Al wiring 73 [731, 732, 733] is formed avoiding the region facing the photodiode PD.

  Next, as shown in FIG. 7B, an eaves portion forming material layer 71 is formed on the uppermost layer of the multilayer wiring layer 54. The eaves part material layer 71 is formed of a material having an etching rate different from that of the interlayer insulating film 52.

  Next, as shown in FIG. 7C, a resist mask (not shown) is formed in a region other than the position corresponding to the photodiode PD on the multilayer wiring layer 54 including the eaves portion forming material layer 71 using a lithography technique. Then, the multi-layer wiring layer 54 including the eaves portion forming material layer 71 is selectively etched by dry etching to form the opening recess 62. That is, the opening recess 62 is formed in the multilayer wiring layer 54 at a position corresponding to each photodiode PD.

  Next, as shown in FIG. 8D, wet etching is performed using an etching solution (chemical solution) having a selectivity between the eaves portion forming material layer 71 and the interlayer insulating film 52, that is, an etching solution for etching the interlayer insulating film 52. Etching is performed to form an over-etched portion 62a having a required width on the inside of the side wall of the opening recess 62. By forming the over-etched portion 62a, the eaves portion 71a is formed by the eaves portion forming material layer 71 so as to protrude into the opening recess 62.

  Next, as illustrated in FIG. 8E, an insulating material layer 63 </ b> A having a high light transmittance and a required refractive index (preferably a high refractive index) is formed so as to fill the opening recess 62. In this embedding of the insulating material layer 63A, the overetching portion 62a remains as a gap because it is restricted by the eaves portion 71a. That is, the gap layer 64 is formed between the buried insulating material layer 63A and the side wall of the over-etched portion 62a. The insulating material layer 63A can be formed using, for example, a CVD method with poor embeddability.

  Next, as shown in FIG. 9F, the insulating material layer 63A is planarized by, for example, a CMP (Chemical Mechanical Polishing) method. Here, the insulating material layer 63A can be formed of, for example, a silicon oxide film, a silicon nitride film, or the like. When the embedded insulating material layer 63A has good planarization properties, for example, an organic material is applied and embedded, the planarization step of FIG. 9F is omitted.

  As a result, a waveguide 65 is formed with the first layer 63 made of an insulating material layer as a core portion and the gap layer 64 formed around the first layer 63 as a cladding portion.

  Next, as shown in FIG. 9G, a color filter 56, a planarizing film 57, and an on-chip microlens 58 are sequentially formed through a passivation film 55 serving as a planarizing film. Note that the passivation film 55 is omitted when the insulating material layer 63A serves as a passivation. In this way, the target CMOS solid-state imaging device 112 is obtained.

  According to the CMOS solid-state imaging device 112 and the manufacturing method thereof according to the second embodiment, instead of the diffusion prevention film, the eaves portion forming material layer 71 plays a role in the formation of the void layer 64 after the opening recess 62 is formed. This is the same as the diffusion preventing film 61 of the first embodiment. Therefore, also in the second embodiment, it is possible to form a waveguide 65 with good waveguide characteristics, which includes the first layer 63 serving as the core portion and the gap layer 64 serving as the cladding portion. In addition, the same effects as those of the first embodiment can be obtained.

  FIG. 10 shows a third embodiment of a CMOS solid-state imaging device according to the present invention. This figure is a schematic cross-sectional view of the main part of the imaging region of the CMOS solid-state imaging device. In the first embodiment of FIG. 3, the CMOS solid-state imaging device 113 according to the present embodiment is a wet etching process after the opening recess 62 is formed outside the barrier layer 60 of the Cu wiring 53 in the multilayer wiring layer 54. Thus, an etching stopper layer 66 is formed so as to prevent wet etching from proceeding excessively. The barrier layer 60 is for preventing diffusion of the Cu wiring 53, and is formed on the lower surface and the side surface of the Cu wiring 53. The etching stopper layer 66 is provided outside the side surface of the barrier layer 60. Since the other configuration is the same as that of the first embodiment of FIG. 3, in FIG. 10, parts corresponding to those in FIG.

  11 to 12 show an embodiment of a manufacturing method of the CMOS solid-state imaging device 113 according to the third embodiment. 11 to 12 show the formation of the interlayer insulating film 52, the etching stopper layer 66, and the Cu wiring 53 of each layer in the multilayer wiring layer 54, and the waveguide and other manufacturing processes are the same as those of FIGS. 4 to 5 described above. Therefore, explanation is omitted.

First, as shown in FIG. 11A, after an interlayer insulating film 52 constituting a multilayer wiring layer is formed, a recess 81 is formed at a position on the upper surface of the interlayer insulating film 52 where a Cu wiring is to be formed.
Next, as illustrated in FIG. 11B, an etching stopper material layer 66 </ b> A is formed on the entire surface of the interlayer insulating film 52 including the inner surface of the recess 81.

Next, as shown in FIG. 11C, the etching stopper material layer 66A is etched back to form side walls, ie, etching stopper layers 66, made of the etching stopper material film 66A on the side walls in the recesses 81.
Next, as illustrated in FIG. 11D, a barrier layer 60 that prevents diffusion of Cu wiring is formed on the entire surface of the interlayer insulating film 52 including the bottom surface and side surfaces in the recess 81. As the barrier layer 60, a barrier metal is used.

  Next, as shown in FIG. 12E, a Cu layer 53 </ b> A is formed on the entire surface of the interlayer insulating film 52 so as to fill the recess 81.

  Next, as shown in FIG. 12F, the Cu layer 53A and the barrier layer 60 are etched back to form the Cu wiring 53 in which the barrier layer 60 is formed on the lower surface and the side surface in the recess 81, and the barrier layer 60 An etching stopper layer 66 is formed on the outer side surface. In this etch-back process, as indicated by a chain line 82 in FIG. 11D, an etch-back process is performed so as to be removed from the surface of the interlayer insulating film 52 to a required depth. Thereby, the etching stopper layer 66 is formed with a required thickness in the recess. As the etching stopper layer 66, for example, a layer made of a material such as SiN or SiC can be used.

  Next, as shown in FIG. 12G, a diffusion preventing film 61 is formed on the entire surface of the interlayer insulating film 52 including the Cu wiring 53.

  By repeating the steps of FIGS. 11A to 12G, the multilayer wiring layer 54 in which the etching stopper layer 66 is formed on the side surface of the barrier layer 60 of the Cu wiring 53 is formed. Thereafter, the CMOS solid-state imaging device 113 of the third embodiment is obtained through the steps of FIGS. 4A to 5F.

  According to the CMOS solid-state imaging device 113 and the manufacturing method thereof according to the third embodiment, the etching stopper layer 66 on the side surface side of the Cu wiring 53 is provided, so that the side wall of the opening recess 62 is over-etched in the step of FIG. In this case, the etching stopper layer 66 makes it difficult for overetching to proceed, and the overetching is not excessive. For example, when the barrier layer 60 is etched with a wet etching solution, it is preferable to apply this embodiment because the barrier layer 60 is not etched. In addition, the same effects as those of the first embodiment are obtained.

  FIG. 13 shows a fourth embodiment of a CMOS solid-state imaging device according to the present invention. This figure is a schematic cross-sectional view of the main part of the imaging region of the CMOS solid-state imaging device. In the second embodiment of FIG. 6, the CMOS solid-state imaging device 114 according to the present embodiment is a wet etching step after the formation of the opening recess 62 outside the Al wiring 71 in the multilayer wiring layer 54. An etching stopper layer 66 that makes it difficult to proceed excessively is formed. Since the other configuration is the same as that of the second embodiment in FIG. 6, in FIG. 13, parts corresponding to those in FIG.

  FIG. 14 shows an embodiment of a method for manufacturing a CMOS solid-state imaging device 114 according to the fourth embodiment. 14 shows the formation of the interlayer insulating film 52, the etching stopper layer 66, and the Al wiring 73 of each layer in the multilayer wiring layer 54, and the waveguide and other manufacturing processes are the same as those in FIGS. 7 to 9 described above. The description is omitted.

First, as shown in FIG. 14A, after an interlayer insulating film 52 constituting a multilayer wiring layer is formed, an Al wiring 73 is formed on the interlayer insulating film 52.
Next, as illustrated in FIG. 14B, an etching stopper material layer 66 </ b> A is formed along the entire surface of the interlayer insulating film 52 including the surface of the Al wiring 73.

Next, as shown in FIG. 14C, the etching stopper material layer 66 </ b> A is etched back to form side walls of the etching stopper material layer on the side surfaces of the Al wiring 73, so-called etching stopper layers 66.
Next, as shown in FIG. 14D, the cover portion forming material layer 71 is formed on the entire surface of the interlayer insulating film 52 including the Al wiring 73 by being backfilled with the interlayer insulating film 52.

  14A to 14D are repeated to form a multilayer wiring layer 54 in which an etching stopper layer 66 is formed on the side surface of the Al wiring 73 of each layer. Alternatively, the eaves portion forming material layer 71 is not formed in the step of FIG. 14D, and after repeating the steps of FIGS. 14A to 14C, the eaves portion forming material layer 71 is formed only in the uppermost layer to form the multilayer wiring layer 54. . Thereafter, the CMOS solid-state imaging device 114 of the fourth embodiment is obtained through the steps of FIGS. 7A to 9G.

  According to the CMOS solid-state imaging device 114 and the manufacturing method thereof according to the fourth embodiment, the etching stopper layer 66 is provided on the side surface of the Al wiring 73, so that the sidewall of the opening recess 62 is over-etched in the step of FIG. Sometimes, the etching stopper layer 66 makes it difficult for over-etching to progress, and the over-etching is not excessive. For example, when the Al wiring 73 is etched with a wet etching solution, it is preferable to apply this embodiment because the etching of the Al wiring 73 is prevented. In addition, the same effects as those of the first embodiment are obtained.

1 is a configuration diagram showing an overall schematic configuration of an embodiment of a solid-state imaging device according to the present invention. It is an equivalent circuit diagram showing an example of a unit pixel. It is sectional drawing of the principal part which shows schematic structure of 1st Embodiment which concerns on this invention. 1A to 1C are manufacturing process diagrams (part 1) illustrating an embodiment of a method for manufacturing a solid-state imaging device according to the first embodiment. DF is a manufacturing process diagram (part 2) illustrating the embodiment of the manufacturing method of the solid-state imaging device according to the first embodiment; It is sectional drawing of the principal part which shows schematic structure of 2nd Embodiment which concerns on this invention. FIGS. 8A to 8C are manufacturing process diagrams (part 1) illustrating an embodiment of a method for manufacturing a solid-state imaging device according to a second embodiment. FIGS. D to E are manufacturing process diagrams (part 2) illustrating the embodiment of the method of manufacturing the solid-state imaging device according to the second embodiment. FG is a manufacturing process diagram (part 3) illustrating the embodiment of the manufacturing method of the solid-state imaging device according to the second embodiment; It is sectional drawing of the principal part which shows schematic structure of 3rd Embodiment concerning this invention. FIGS. 9A to 9D are manufacturing process diagrams (part 1) of a main part illustrating an embodiment of a manufacturing method of a solid-state imaging device according to a third embodiment. FIGS. EG is a manufacturing process diagram (No. 2) of the principal part showing the embodiment of the manufacturing method of the solid-state imaging device according to the third embodiment. It is sectional drawing of the principal part which shows schematic structure of 4th Embodiment which concerns on this invention. AD is a manufacturing process diagram of the main part showing the embodiment of the manufacturing method of the solid-state imaging device according to the third embodiment.

Explanation of symbols

  1 .... Solid-state imaging device 2 .... Pixel 3 .... Imaging area 4 .... Vertical drive circuit 5 .... Column signal processing circuit 6 .... Horizontal drive circuit 7 .... Output circuit 8 .... Control Circuit, 9 ·· Vertical signal line, 10 ·· Horizontal signal line, 111 to 114 ·· CMOS solid-state imaging device, PD ·· Photoelectric conversion part (photodiode), Tr1, Tr2 ·· MOS transistor, 52 ·· Interlayer insulation Film 53 [531, 532, 533], 73 [731, 732, 733] ... wiring 54 ... multilayer wiring layer 55 ... passivation film 56 ... color filter 57 ... flattening film 58 ..On-chip microlens 60 ..Barrier layer 61 ..Diffusion prevention film 61 a .Eave portion 62. .Open recess 63.. First layer 64. Waveguide, 66 ... Etching stop Layer, 71 ... eave portion forming material layer, 71a ... eave

Claims (7)

A plurality of pixels;
A multilayer wiring layer in which a plurality of wirings are formed above the plurality of pixels via an interlayer insulating film;
A waveguide for guiding incident light to the photoelectric conversion portion of the pixel;
The waveguide includes a first layer having a required refractive index regulated by an eaves portion formed in the multilayer wiring layer as a core portion, and a gap formed between the first layer and the multilayer wiring layer. A solid-state imaging device characterized in that the layer is configured as a cladding part. The solid-state imaging device according to claim 1, wherein an etching stopper layer is formed on the gap layer side of the wiring. The solid-state imaging device according to claim 1, wherein the wiring is formed of Cu wiring, and the eaves portion is formed of a diffusion prevention film of C wiring. Forming a multi-layered wiring layer having a plurality of wirings formed over an interlayer insulating film and having an eaves portion forming material layer above the plurality of pixels;
Selectively forming an opening recess having a required depth in a portion corresponding to the photoelectric conversion portion constituting the pixel of the multilayer wiring layer;
Wet etching the interlayer insulating film on the side wall of the opening recess to form an eave portion by the eaves portion forming material in the opening recess; and
A first layer having a required refractive index regulated by the eaves portion is formed in the opening recess so that a void layer is formed between the side wall of the interlayer insulating film and the first layer is formed. Forming a waveguide having a core portion and the gap layer as a cladding portion. A method of manufacturing a solid-state imaging device. The method for manufacturing a solid-state imaging device according to claim 4, wherein the wiring of the multilayer wiring layer is formed of Cu wiring, and the eaves portion is formed of a diffusion prevention film of Cu wiring. The method of manufacturing a solid-state imaging device according to claim 4, further comprising a step of forming an etching stopper layer on the gap layer side of the wiring. 5. The method of manufacturing a solid-state imaging device according to claim 4, further comprising forming the eaves portion forming material layer having a selectivity with respect to the interlayer insulating film on the uppermost layer of the multilayer wiring layer.

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