CN107230684B - The encapsulating structure and its manufacturing method of wafer scale image sensing chip - Google Patents
The encapsulating structure and its manufacturing method of wafer scale image sensing chip Download PDFInfo
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- CN107230684B CN107230684B CN201710504398.6A CN201710504398A CN107230684B CN 107230684 B CN107230684 B CN 107230684B CN 201710504398 A CN201710504398 A CN 201710504398A CN 107230684 B CN107230684 B CN 107230684B
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- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 95
- 238000007789 sealing Methods 0.000 claims abstract description 89
- 229910052751 metal Inorganic materials 0.000 claims abstract description 75
- 239000002184 metal Substances 0.000 claims abstract description 75
- 239000011521 glass Substances 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 44
- 239000000565 sealant Substances 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 claims description 5
- 239000012790 adhesive layer Substances 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000007787 solid Substances 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 239000011135 tin Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 claims description 2
- 238000006116 polymerization reaction Methods 0.000 claims description 2
- 238000010422 painting Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 6
- 229920000642 polymer Polymers 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- -1 for example Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 239000013618 particulate matter Substances 0.000 description 2
- 229920000307 polymer substrate Polymers 0.000 description 2
- 238000012163 sequencing technique Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910001069 Ti alloy Inorganic materials 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- IUYOGGFTLHZHEG-UHFFFAOYSA-N copper titanium Chemical compound [Ti].[Cu] IUYOGGFTLHZHEG-UHFFFAOYSA-N 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229910000969 tin-silver-copper Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14632—Wafer-level processed structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
The invention discloses a kind of encapsulating structures, it include: transparent substrate, chip, sealing cover, sealing ring, the sealing ring is clipped between the first face of the sealing cover and the second face of the transparent substrate, and makes the space sealing formed by seal groove and transparent substrate.Image sensing chip is sealed in slide glass and is sealed by metal o-ring by some embodiments of the present invention, and die stress is small, good reliability, and sealing effect is good.
Description
Technical field
The present invention relates to encapsulation field more particularly to the encapsulating structures and its manufacturing method of wafer scale image sensing chip.
Background technique
As the size of image sensor is smaller and smaller, solder joint number is increasing, and spot pitch is more and more narrow, accordingly
Ground, to image sensor package, more stringent requirements are proposed.
Traditional image sensor package method is usually to be packaged using wire bonding, but fly with integrated circuit
Speed development, longer lead make package dimension be unable to reach ideal requirement, and therefore, wafer-level packaging (WLP) gradually replaces
Wire bond package becomes a kind of more common packaging method.Wafer-level packaging (WLP) technology is sealed to full wafer wafer
It cuts to obtain the technology of single finished product chip again after dress test, the chip size after encapsulation is completely the same with bare die, has complied with city
Increasingly light to microelectronic product, small, the short, thinning in field and low priceization requirement.
When being packaged using existing Wafer level packaging to image sensor, in order to protect shadow in encapsulation process
As the photosensitive area of sensor is injury-free and pollution, it usually needs form a cap in photosensitive zone position to protect its sense
Light area.
Fig. 1 shows the encapsulating structure of image sensor according to prior art, including transparent substrate 1, image sensing core
Piece 2, closing frame 3 and substrate 4.The periphery of transparent substrate second surface has metal to reroute region and pad network 13, and image passes
Pad 24 and salient point 25 on sensor chip active surface are electrically connected with the part pad formation in transparent substrate, the first table of substrate
There are wiring and connection pad network 13 on face, closing frame is enclosed in image sensor dice periphery, and closing frame both ends are respectively and thoroughly
Bright substrate and substrate contact, the conduct piece for being built in closing frame are electrically connected with the connection pad of the pad of transparent substrate and substrate respectively,
Closing 3 periphery of frame is provided with sealing 5.
However, existing image sensing chip package usually requires to prepare polymer cofferdam on glass, formed certain high
It spends and is used to seal.But polymer cofferdam has more particle contamination, glue poor sealing effect.
Therefore, it is necessary to a kind of encapsulating structures of image sensing chip based on non-polymer cofferdam.
Summary of the invention
Aiming at the problems existing in the prior art, according to one embodiment of present invention, a kind of encapsulating structure is provided, is wrapped
Include: transparent substrate, the transparent substrate have first surface and the second surface opposite with first surface, the second surface
Periphery is formed with metal and reroutes region, and it includes dielectric layer and inside it or the gold of surface formation that the metal, which reroutes region,
Belong to wiring, one or more first metal interconnection structures are provided on the metal line and one or more second metals are mutual
Link structure；Chip, the chip include front and back, the front of the chip have one or more salient points, functional areas with
And the circuit being electrically connected is formed between the salient point and functional areas, the front of the chip faces the second of the transparent substrate
Positive one or more salient points on surface, the chip mutually link with corresponding first metal in the transparent substrate respectively
Structure electrical connection；Sealing cover, the sealing cover include the first face and second face opposite with the first face, and the first of the sealing cover
Face faces the second surface of the transparent substrate, has the sealing for accommodating the chip in the first face of the sealing cover
Slot, the back side of the chip are attached to the slot bottom of the seal groove, and the sealing cover further includes the side that the seal groove is arranged in
One or more through-holes in second face are extended on wall from first face, are provided with conduct piece in the through-hole, it is described
Conduct piece is electrically connected with the first pad of one or more on the first face of the sealing cover, and the conduct piece with it is described close
Capping the second face on second pad of one or more be electrically connected, one or more of first pads respectively with it is described transparent
Corresponding second metal interconnection structure electrical connection on substrate；And sealing ring, the sealing ring are clipped in the of the sealing cover
On one side between the second face of the transparent substrate, and make the space sealing formed by seal groove and transparent substrate.
According to one embodiment of present invention, encapsulating structure further include be formed in the transparent substrate first surface and/
Or anti-reflection film or antireflection film on second surface.
According to one embodiment of present invention, the conduct piece in the through-hole for solid conduct piece or is coated in through-hole wall
Conductive layer.
According to one embodiment of present invention, sealing ring is formed by one or more layers metal layer, the material of the sealing ring
It is selected from: copper, titanium, silver, gold, tin and its alloy.
According to one embodiment of present invention, have on the second face of the sealing cover and reroute layer, setting in weight cloth
The solder bump on one or more of first pads, and/or first pad on line layer.
According to one embodiment of present invention, have on the first face of the sealing cover and reroute layer, setting in weight cloth
The solder bump on one or more of second pads, and/or second pad on line layer.
According to another embodiment of the invention, a kind of manufacturing method of encapsulating structure is provided, comprising: the first of substrate
Seal groove and hole are formed on face as sealing cover；Conduct piece and the shape on the first face of the substrate are formed in described hole
At one or more first pads；The first sealant for surrounding the seal groove is formed on the first face of the substrate；By core
The back side of piece is attached to the slot bottom of seal groove, wherein the chip includes front and back, the front of the chip has one
Or multiple salient points, functional areas and the circuit being electrically connected is formed between the salient point and functional areas；In a table of transparent substrate
The periphery in face forms metal and reroutes region, and it includes dielectric layer and inside it or surface is formed that the metal, which reroutes region,
Metal line, and one or more first metal interconnection structures and one or more second gold medals are set on the metal line
Belong to interconnection structure, positive one or more salient points of the chip respectively with a phase in first metal interconnection structure
It is corresponding, and one or more of first pads are corresponding with one in second metal interconnection structure respectively；Transparent
The second sealant corresponding with first sealant is formed on the surface of substrate；By the transparent substrate and the sealing
Lid and the chip align and is bonded so that the chip it is positive one or more salient points respectively with corresponding first metal
Interconnection structure forms electrical connection, and one or more of first pads are electrically connected with the formation of corresponding second metal interconnection structure respectively
It connects, and first sealant engages to form sealing structure with second sealant；It is formed in the second face of the sealing cover
Conductive structure.
According to another embodiment of the invention, the substrate is selected from: semiconductor substrate, metal substrate, polymer substrate
Or glass substrate.
According to another embodiment of the invention, this method further includes being formed before conduct piece in described hole described
Insulating layer is formed on the side wall on the surface of substrate, the surface of the seal groove and described hole.
It according to another embodiment of the invention, include passing through adhesive layer by the slot bottom that the back side of chip is attached to seal groove
By the back adhesive of chip to slot bottom.
According to another embodiment of the invention, forming conductive structure in the second face of the sealing cover includes: to described
The second surface of sealing cover carry out it is thinned, to expose the conduct piece in described hole；Insulation is formed on the second surface
Layer；It drills on the insulating layer, exposes the conduct piece in described hole；And it is formed and reroutes structure and salient point.
Image sensing chip is sealed in slide glass and is sealed by metal o-ring by some embodiments of the present invention,
Die stress is small, good reliability, and sealing effect is good.Since the embodiment of the present invention is avoided using polymer cofferdam, particle
Pollution is few, and yield is high.
Detailed description of the invention
For the above and other advantages and features for each embodiment that the present invention is furture elucidated, will be presented with reference to attached drawing
The more specific description of various embodiments of the present invention.It is appreciated that these attached drawings only describe exemplary embodiments of the invention, therefore
It is not to be regarded as being restriction on its scope.In the accompanying drawings, in order to cheer and bright, identical or corresponding component will use identical or class
As mark indicate.
Fig. 1 shows the encapsulating structure of image sensor according to prior art.
Fig. 2 shows the cross sections of the encapsulating structure 200 of the wafer scale image sensing chip of embodiment according to the present invention to show
It is intended to.
Fig. 3 shows the top view of the sealing ring of embodiment according to the present invention.
Fig. 4 A to Fig. 4 I shows the mistake that embodiment according to the present invention forms the encapsulating structure of wafer scale image sensing chip
The diagrammatic cross-section of journey.
Fig. 5 shows the flow chart that embodiment according to the present invention forms the encapsulating structure of wafer scale image sensing chip.
Specific embodiment
In the following description, with reference to each embodiment, present invention is described.However, those skilled in the art will recognize
Know can in the case where none or multiple specific details or with other replacements and/or addition method, material or component
Implement each embodiment together.In other situations, well known structure, material or operation are not shown or are not described in detail in order to avoid making this
The aspects of each embodiment of invention is obscure.Similarly, for purposes of explanation, specific quantity, material and configuration are elaborated, with
Comprehensive understanding to the embodiment of the present invention is just provided.However, the present invention can be implemented in the case where no specific detail.This
Outside, it should be understood that each embodiment shown in the accompanying drawings is illustrative expression and is not drawn necessarily to scale.
In the present specification, the reference of " one embodiment " or " embodiment " is meaned to combine embodiment description
A particular feature, structure, or characteristic is included at least one embodiment of the invention.Occur in everywhere in this specification short
Language " in one embodiment " is not necessarily all referring to the same embodiment.
It should be noted that the embodiment of the present invention is described processing step with particular order, however this is only
Facilitate and distinguish each step, and is not the sequencing for limiting each step, it in different embodiments of the invention, can be according to work
Skill is adjusted to adjust the sequencing of each step.
In encapsulating structure in order to solve the image sensor of the prior art, polymer cofferdam particle contamination is more, and glue is close
The problem of effect difference is sealed, image sensing chip is sealed in slide glass and is sealed by metal o-ring by present invention proposition,
Die stress is small, good reliability, and sealing effect is good.Since the embodiment of the present invention is avoided using polymer cofferdam, particle
Pollution is few, and yield is high.
Fig. 2 shows the cross sections of the encapsulating structure 200 of the wafer scale image sensing chip of embodiment according to the present invention to show
It is intended to.As shown in Fig. 2, the encapsulating structure 200 of image sensing chip include transparent substrate 210, it is image sensor dice 220, close
Capping 230 and sealing ring 240.
Further, as shown in Fig. 2, transparent substrate 210 includes first surface 211 and second table opposite with first surface
Face 212.In a specific embodiment of the present invention, anti-reflection film or anti-can be formed on first surface 211 and/or second surface 212
Reflectance coating, to increase light transmittance and reduce light reflection to prevent strong illumination from image being made white haze, ghost occur.Second table
The periphery in face 212 is formed with metal and reroutes region 213.It includes dielectric layer and inside it or table that metal, which reroutes region 213,
The metal line (not shown) that face is formed, be provided on metal line one or more first metal interconnection structures 214 with
And one or more second metal interconnection structures 215.First metal interconnection structure and the second metal interconnection structure 215 can be weldering
Disk, soldered ball, protrusion or other structures for being used to form electrical connection.First metal interconnection structure 214 and image sensor dice 220
Form electrical connection.Second metal interconnection structure 215 is electrically connected with the metal line formation on sealing cover 230.
Image sensor dice 220 include first surface 221 and second surface 222, the first of image sensor dice 220
Be formed in surface 221 one or more salient points 223, image sensing area 224 and salient point 223 and image sensing area 224 it
Between form the circuit (not shown) of electrical connection.It is formed with image sensor unit in image sensing area 224 and is passed with image
Ambient is received and converted into electricity using the image sensor unit and believed by the associated circuit that sensor cell is connected
Number, and electrical signal is rerouted into the 213, second metal interconnection structure using salient point 223, the first metal interconnection structure 214, metal
215 and sealing cover 230 on conducting wire send other circuits to.
In the present embodiment, for the ease of wiring, image sensing area 224 is located at the middle position of chip, and salient point 223 is located at
The marginal position of chip.In other embodiments, the position in salient point and image sensing area can also flexibly be adjusted according to cabling requirement
It is whole.
Sealing cover 230 includes the first face 231 and the second face 232.Have in the first face 231 of sealing cover 230 for holding
Receive image sensor dice 220 from the first face 231 be recessed seal groove 233, the size of seal groove 233 is according to image sensor
Chip 220 determines.The second surface 222 of image sensor dice 220 is attached to the slot bottom of seal groove 233.In reality of the invention
It applies in example, image sensor dice 220 can be bonded to the slot bottom of seal groove 233 by adhesive layer 234.The side wall of seal groove 233
On be provided with one or more through-holes 235.Conduct piece 236 is provided in through-hole 235, conduct piece can be solid conduct piece or be
Conductive layer coated in through-hole wall.Conduct piece 236 is electrically connected one or more pads on 230 first face 231 of seal cap
One or more pad 237b on 237a and the second face 232.Can have on the first face of sealing cover 230 and reroute layer and set
It sets and is rerouting pad and soldered ball on layer.Have on the second face of sealing cover 230 and reroute layer (not shown), and sets
It sets and is rerouting pad and soldered ball 238 on layer, be used to form the metal interconnection structure connecting with external circuit.Sealing cover 230
It can be formed by following material: semiconductor substrate, for example, silicon substrate, silicon-Germanium substrate, silicon carbide substrates etc.；Metal substrate；Polymerization
Object substrate；Glass substrate etc..On the one or more pad 237a and transparent substrate 210 on 230 first face 231 of sealing cover
Second metal interconnection structure 215 forms electrical connection.The electric signal of image sensor dice 220 is transmitted to by salient point 223 thereon
First metal interconnection structure 214, then it is transmitted to the second metal interconnection structure 215 through the rewiring layer 213 in transparent substrate 210,
It is transmitted to the conduct piece 236 in through-hole 235 by the pad 237a on 230 first face 231 of sealing cover, and then is transmitted to sealing cover
Rewiring layer and soldered ball 238 on 230 second faces 232 realize the letter with external circuit by the soldered ball 238 on the second face 232
Breath exchange.
There is sealing ring 240 between sealing cover 230 and transparent substrate 210.Sealing ring 240 make by seal groove 233 with
Image sensing chip, is thus sealed in confined space by the space sealing that transparent substrate 210 is formed.Sealing ring 240 is settable
In sealing cover 230 and transparent substrate 210 in outermost.Fig. 3 shows the vertical view of the sealing ring 230 of embodiment according to the present invention
Figure.In an embodiment of the present invention, the material of sealing ring 240 can be metal, for example, copper, titanium, silver, gold, tin；Alloy, example
Such as, sn-ag alloy, Tin Silver Copper Alloy, copper-titanium alloy etc..Sealing ring 240 may also include the more metal layers of stacking.Sealing ring
240 play fixing seal, and prevent influence of the external factor such as steam, particle to image sensor dice.
Form the envelope of wafer scale image sensing chip according to one embodiment of present invention below with reference to Fig. 4 and Fig. 5 description
The process of assembling structure.Fig. 4 A to Fig. 4 I shows the encapsulating structure that embodiment according to the present invention forms wafer scale image sensing chip
Process diagrammatic cross-section.Fig. 5 shows the encapsulating structure that embodiment according to the present invention forms wafer scale image sensing chip
Flow chart.
In step 501, sealing cover structure is prepared on substrate.In an embodiment of the present invention, it is used to prepare sealing cover
Substrate can be selected from: semiconductor substrate, for example, silicon substrate, silicon-Germanium substrate, silicon carbide substrates etc.；Metal substrate；Polymer substrate；
Glass substrate etc..Firstly, as shown in Figure 4 A, forming seal groove 402 and hole 403 on the first surface of substrate 401.Hole
403 can be the through-hole through substrate 401 or the blind hole with certain depth.In an embodiment of the present invention, dry method can be passed through
Or the method for wet etching forms seal groove 402 and hole 403.As shown in Figure 4 B, on the surface of substrate 401, seal groove 402
Surface and hole side wall on form insulating layer 404, the material of insulating layer 404 can be silica, silicon nitride, nitrogen oxidation
Silicon or high K dielectric material, the insulating layer 404 can be used for being electrically isolated between conductive layer and substrate 401.If substrate 401
It is insulating substrate, then It is not necessary to form insulating layer 404.
In step 502, as shown in Figure 4 C, conductive structure, and the first face of substrate 401 are formed in the first face of substrate 401
It is upper to form the first sealant 407 for surrounding seal groove 402.In an embodiment of the present invention, conduct piece is formed in hole 403
405 and pad 406 is formed in port, conduct piece can be solid conduct piece or be the conductive layer coated in through-hole wall.May be used also
It is required according to actual wiring, forms wiring layer on the first face of substrate 401.In the embodiment shown in Fig. 4 C, the
One sealant 407 surrounds seal groove 402 and pad 406.However, the scope of the present invention is not limited thereto, for example, the first sealant
407 can be located at the outside of the first sealant 407 close to seal groove, metal interconnection structure.The material of first sealant 407 can be with
Conduct piece 405 and 406 material of pad are identical, are also possible to different materials.
In step 503, by chip formal dress in seal groove.As shown in Figure 4 D, image sensor dice 408 includes the first table
Face 409 and second surface 410, the interior first surface 409 of image sensor dice 408 includes image sensing area and one or more
A salient point 411.In an embodiment of the present invention, the slot of seal groove can be bonded to by 412 image sensor dice 408 of adhesive layer
The designated position at bottom.
In step 504, as shown in Figure 4 E, conductive structure and the second sealant are prepared in transparent substrate 413.In the present invention
Specific embodiment in, anti-reflection film or antireflection film can be formed on the surface of transparent substrate, to increase light transmittance and subtract
Few light reflection is to prevent strong illumination from image being made white haze, ghost occur.Conductive structure 414 in transparent substrate 413 includes being situated between
Matter layer and inside it or the metal line (not shown) that is formed of surface, one or more first is provided on metal line
Metal interconnection structure 415 and one or more second metal interconnection structures 416.First metal interconnection structure and the second metal are mutual
Connection structure can be pad, soldered ball, protrusion or other structures for being used to form electrical connection.First metal interconnection structure 415 and shadow
As the salient point 411 of sensor core on piece forms electrical connection.Second metal interconnection structure 416 and 406 shape of pad on sealing cover 401
At electrical connection.The second sealant 417 in transparent substrate 413 is used for and the first sealant 407 on 401 first surface of sealing cover
Bond together to form sealing structure.It therefore, can be according to size and the position of pad and the first sealant on 401 first surface of sealing cover
It sets, determines conducting wire, the size of pad and the second sealant and position over the transparent substrate.In specific implementation of the invention
In example, soldered ball optionally is formed on the pad of transparent substrate.
Next, in step 505, as illustrated in figure 4f, by transparent substrate 413 and sealing cover 401 and image sensor dice
408 align and are bonded.The first metal interconnection structure on salient point 411 and transparent substrate 413 in image sensor dice 408
415 contrapositions connect and form electrical connection.Pad 406 and the second metal interconnection structure 416 contraposition connection and shape on sealing cover 401
At electrical connection.The first sealant 407 on sealing cover 401 engages with the second sealant in transparent substrate 413 and forms sealing
Structure.
In step 506, is formed on the second surface 418 of sealing cover 401 and reroute layer, pad and/or ball structure.It is first
First, as shown in Figure 4 G, the second surface 418 of sealing cover 401 is carried out it is thinned, to expose through-hole.Next, in second surface
Insulating layer 419 is formed on 418, as shown at figure 4h.Next, drilling on insulating layer 419, expose hole conductive layer.Finally, shape
At structure and salient point is rerouted, as shown in fig. 41.
In some embodiments of the invention, the combination of transparent substrate and image sensor dice, sealing cover and transparent base
The combination of material and the combination of the first sealant and the second sealant can carry out simultaneously.On image sensor dice active surface
Covering transparent substrate can reduce the pollution of the particle in follow-up process, improve process rate, reduce production cost, sealing cover can
Image sensor dice is protected, and conductive channel can be constituted by built-in conduct piece.It is sealed by metal o-ring, chip
Stress is small, good reliability, and sealing effect is good.
Although described above is various embodiments of the present invention, however, it is to be understood that they are intended only as example to present
, and without limitation.For those skilled in the relevant art it is readily apparent that various combinations, modification can be made to it
Without departing from the spirit and scope of the invention with change.Therefore, the width of the invention disclosed herein and range should not be upper
It states disclosed exemplary embodiment to be limited, and should be defined according only to the appended claims and its equivalent replacement.
Claims (11)
1. a kind of encapsulating structure, comprising:
Transparent substrate, the transparent substrate have first surface and the second surface opposite with first surface, the second surface
Periphery be formed with metal and reroute region, it includes dielectric layer and inside it or surface is formed that the metal, which reroutes region,
Metal line is provided with one or more first metal interconnection structures and one or more second metals on the metal line
Interconnection structure；
Chip, the chip include front and back, the front of the chip have one or more salient points, functional areas and
The circuit being electrically connected is formed between the salient point and functional areas, the front of the chip faces the second table of the transparent substrate
Face, positive one or more salient points of the chip respectively with corresponding first metal interconnection structure in the transparent substrate
Electrical connection；
Sealing cover, the sealing cover include the first face and second face opposite with the first face, the first face face of the sealing cover
To the second surface of the transparent substrate, there is the seal groove for accommodating the chip in the first face of the sealing cover,
The back side of the chip is attached to the slot bottom of the seal groove, and the sealing cover further includes being arranged on the side wall of the seal groove
One or more through-holes in second face are extended to from first face, and conduct piece, the conduction are provided in the through-hole
Part is electrically connected with the first pad of one or more on the first face of the sealing cover, and the conduct piece and the sealing cover
The second face on the second pad of one or more electrical connection, one or more of first pads respectively with the transparent substrate
On corresponding second metal interconnection structure electrical connection；And
Sealing ring, the sealing ring is clipped between the first face of the sealing cover and the second face of the transparent substrate, and is made
Obtain the space sealing formed by seal groove and transparent substrate.
2. encapsulating structure as described in claim 1, which is characterized in that further include the first surface for being formed in the transparent substrate
And/or anti-reflection film or antireflection film on second surface.
3. encapsulating structure as described in claim 1, which is characterized in that the conduct piece in the through-hole is solid conduct piece or painting
Overlay on the conductive layer of through-hole wall.
4. encapsulating structure as described in claim 1, which is characterized in that sealing ring is formed by one or more layers metal layer, described
The material of sealing ring is selected from: copper, titanium, silver, gold, tin and its alloy.
5. encapsulating structure as described in claim 1, which is characterized in that have on the second face of the sealing cover and reroute
The solder bump rerouted on one or more of first pads, and/or first pad on layer is arranged in layer.
6. encapsulating structure as described in claim 1, which is characterized in that have on the first face of the sealing cover and reroute
The solder bump rerouted on one or more of second pads, and/or second pad on layer is arranged in layer.
7. a kind of manufacturing method of encapsulating structure, comprising:
Seal groove and hole are formed on the first side of a substrate as sealing cover；
Conduct piece is formed in described hole and one or more first pads are formed on the first face of the substrate；
The first sealant for surrounding the seal groove is formed on the first face of the substrate；
The back side of chip is attached to the slot bottom of seal groove, wherein the chip includes front and back, the front of the chip
Form with one or more salient points, functional areas and between the salient point and functional areas the circuit being electrically connected；
Form metal on the periphery on a surface of transparent substrate and reroute region, the metal reroute region include dielectric layer and
Inside it or the metal line that is formed of surface, and one or more first metal interconnection structures are set on the metal line
And one or more second metal interconnection structures, positive one or more salient points of the chip respectively with first gold medal
One belonged in interconnection structure is corresponding, and one or more of first pads are respectively and in second metal interconnection structure
One it is corresponding；
The second sealant corresponding with first sealant is formed on the surface of transparent substrate；
The transparent substrate is aligned and is bonded with the sealing cover and the chip so that positive one of the chip or
Multiple salient points respectively with corresponding first metal interconnection structure formed be electrically connected, one or more of first pads respectively with it is right
The second metal interconnection structure answered forms electrical connection, and first sealant engages to form sealing knot with second sealant
Structure；
Conductive structure is formed in the second face of the sealing cover.
8. the method for claim 7, which is characterized in that the substrate is selected from: semiconductor substrate, metal substrate, polymerization
Object substrate or glass substrate.
9. the method for claim 7, which is characterized in that further include being formed before conduct piece in described hole described
Insulating layer is formed on the side wall on the surface of substrate, the surface of the seal groove and described hole.
10. the method for claim 7, which is characterized in that the back side of chip is attached to the slot bottom of seal groove including logical
Adhesive layer is crossed by the back adhesive of chip to slot bottom.
11. the method for claim 7, which is characterized in that forming conductive structure in the second face of the sealing cover includes:
The second surface of the sealing cover is carried out it is thinned, to expose the conduct piece in described hole；
Insulating layer is formed on the second surface；
It drills on the insulating layer, exposes the conduct piece in described hole；And
It is formed and reroutes structure and salient point.
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| CN111009542B (en) * | 2019-12-27 | 2023-03-10 | 中芯集成电路（宁波）有限公司 | Packaging method and packaging structure |
| CN111606297B (en) * | 2020-04-28 | 2021-04-16 | 诺思(天津)微系统有限责任公司 | Device structure, method of manufacturing the same, filter, and electronic apparatus |
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| JP4380718B2 (en) * | 2007-03-15 | 2009-12-09 | ソニー株式会社 | Manufacturing method of semiconductor device |
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