CN105097647B - A method of making semiconductor devices - Google Patents
A method of making semiconductor devices Download PDFInfo
- Publication number
- CN105097647B CN105097647B CN201410183949.XA CN201410183949A CN105097647B CN 105097647 B CN105097647 B CN 105097647B CN 201410183949 A CN201410183949 A CN 201410183949A CN 105097647 B CN105097647 B CN 105097647B
- Authority
- CN
- China
- Prior art keywords
- layer
- silicon via
- opening
- silicon
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to a kind of method for making semiconductor devices, metal copper layer is etched back to after through silicon via to expose grinding and/or polishing the TSV device back side, to prevent metallic copper from spreading and improve the reliability of device.Production method according to the present invention improves the reliability of through silicon via using back side wafer grade encapsulation (WLP) technique；Meanwhile the step of not being etched back to silicon wafer after executing grinding and polishing, is to reduce the production cost.
Description
Technical field
The present invention relates to semiconductor fields, in particular it relates to a kind of method for making semiconductor devices.
Background technique
In consumer electronics field, multifunctional equipment is increasingly liked by consumer, compared to the simple equipment of function,
Multifunctional equipment manufacturing process is more complicated, for example needs to integrate the chip of multiple and different functions in circuit version, thus occurs
3D integrated circuit (integrated circuit, IC) technology, 3D integrated circuit (integrated circuit, IC) are determined
Justice is a kind of system-level integrated morphology, and multiple chips are stacked in vertical plane direction, so that space is saved, the side of each chip
Edge point, which can according to need, draws multiple pins, utilizes these pins as needed, and the chip interconnected will be needed to pass through
Metal wire interconnection, but aforesaid way still has many deficiencies, for example stacked chips quantity is more, and the company between chip
Relationship Comparison complexity is connect, then just may require that final wire laying mode will be more chaotic, and can lead using a plurality of metal wire
Volume is caused to increase.
Therefore, through silicon via is mostly used in the 3D integrated circuit (integrated circuit, IC) technology at present
(Through Silicon Via, TSV), through silicon via are a kind of perpendicular interconnections for penetrating Silicon Wafer or chip, TSV can storehouse it is more
Piece chip drills out duck eye (processing procedure can be divided into first drilling and rear two kinds of drilling, Via Fist, Via Last again) in chip, the bottom of from
Portion is packed into metal, is drilled (via) in a manner of etching or laser on Silicon Wafer, then with objects such as conductive materials such as copper, polysilicon, tungsten
Matter is filled up.To realize the interconnection between different silicon wafers.
There is many problems for the preparation method of the current through silicon via, for example, gold caused by being broken due to oxide skin(coating)
Belong to the high risk that copper diffusion phenomena make integrated circuit have reliability failures.
Therefore, it is necessary to a kind of preparation methods of new semiconductor devices through silicon via, to solve the problems of the prior art.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
The present invention is in order to overcome the problems, such as that presently, there are provide a kind of method for making semiconductor devices, comprising: offer is partly led
The front of body substrate, the semiconductor substrate is formed with through silicon via；Using the back of semiconductor substrate described in planarization process treating
To expose the bottom of the through silicon via, the through silicon via includes conductive layer and barrier layer in face；It is etched back to the bottom of the through silicon via
To remove the conductive layer of part；First passivation layer with the first opening is formed on the back side of the semiconductor substrate,
Wherein first opening is located at the top of the conductive layer.
It illustratively, further include forming wiring layer again on first passivation layer after forming first passivation layer
The step of, wherein the wiring layer again fills first passivation layer of first opening and covering part.
It illustratively, further include being formed to have on the back side of the semiconductor substrate after forming the wiring layer again
The step of second passivation layer of the second opening, wherein second opening is located at the top of the wiring layer again.
It illustratively, further include the step for being implanted into solder ball in second opening after forming second passivation layer
Suddenly.
Illustratively, the width of the conductive layer is 20-30 microns.
Illustratively, the width of first opening is 10-20 microns.
Illustratively, the wiring layer again with a thickness of 5-10 microns, the material of the wiring layer again is metallic copper.
Illustratively, the flatening process is grinding and/or polishing.
The present invention provides a kind of methods of new preparation through silicon via, are grinding and polishing the TSV device back side to expose silicon
It is etched back to metal copper layer after through-hole, to prevent metallic copper from spreading and improve the reliability of device.Production side according to the present invention
Method improves the reliability of through silicon via using back side wafer grade encapsulation (WLP) technique；Meanwhile after executing grinding and polishing
The step of not being etched back to silicon wafer is to reduce the production cost.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, device used to explain the present invention and principle.In the accompanying drawings,
Fig. 1 is a kind of process flow chart for making through-silicon via structure；
Fig. 2A -2D is the correlation step device obtained that through-silicon via structure is made according to one embodiment of the present invention
Structural schematic diagram；
Fig. 3 is the process flow chart that through-silicon via structure is made according to one embodiment of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed description will be proposed in following description, to illustrate present invention production half
The method of conductor device.Obviously, execution of the invention is not limited to the specific details that the technical staff of semiconductor field is familiar with.
Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention can also have other realities
Apply mode.
It should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singular
It is intended to include plural form.Additionally, it should be understood that when using term "comprising" and/or " comprising " in the present specification
When, indicate that there are the feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of one or more
Other a features, entirety, step, operation, element, component and/or their combination.
Now, an exemplary embodiment of the present invention is more fully described with reference to the accompanying drawings.However, these exemplary realities
Applying example can be implemented with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.It should
These embodiments that are to provide understood are in order to enable disclosure of the invention is thoroughly and complete, and by these exemplary implementations
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, the thickness of layer and region is exaggerated
Degree, and make that identical element is presented with like reference characters, thus description of them will be omitted
As shown in Figure 1, being a kind of process flow chart for making through-silicon via structure.
In a step 101, through silicon via is formed on silicon wafer front, in one example, production is integrated on silicon
Circuit element forms oxide skin(coating) and dielectric layer on silicon, etches the dielectric layer, the oxide skin(coating) and the silicon wafer
Piece is to form groove, and deposition forms barrier layer in the trench, and it is described to fill that copper metal layer is formed on the barrier layer
Groove, subsequent step further include forming aluminium or copper metal conductive layer.
In a step 102, silicon wafer front be bonded between another chip, in one example, in silicon wafer
Electroless plated metal layer is deposited on copper packing, to form silicon wafer to the bonding pad of another chip, then, is executed thermal diffusion and is bonded work
Skill.
In step 103, to the execution grinding of the silicon wafer back side and polishing process to expose through silicon via, in an example,
Silicon wafer after bonding is inverted, the silicon wafer is handled using grinding back surface and polishing process, it is logical to expose silicon
Hole.
At step 104, the silicon wafer back side is etched back to remove the silicon wafer of part, so that through silicon via is higher than silicon wafer table
Face.
In step 105, spacer material layer is formed on the silicon wafer back side, the material of the spacer material layer can be oxygen
Compound, to prevent the pollution to silicon wafer.
The method of above-mentioned production through silicon via, which is easy to generate, is broken caused metallic copper diffusion phenomena by oxide skin(coating), increases
The high risk of IC reliability failure.
The present invention provides one kind and partly leads to solve the problems, such as current semiconductor devices through silicon via preparation process
The preparation method of body device through silicon via, Fig. 2A -2D are to make the related of through-silicon via structure according to one embodiment of the present invention to walk
The structural schematic diagram of rapid device obtained；Fig. 3 is the technique stream that through-silicon via structure is made according to one embodiment of the present invention
Cheng Tu.
Preparation method of the invention is described in detail below with reference to Fig. 2A -2D and Fig. 3.It should be noted that
The step of silicon wafer is executed before polishing and grinding, be for those skilled in the art it is well known, it is just not superfluous in detail herein
It states.Meanwhile the structure of the chip of the through silicon via of wanted sequencing is only gived in attached drawing 2A-2D, in the integrated of semiconductor devices
It is connected with each other in circuit comprising multiple chips as described in Figure, formation lamination, the silicon is logical through the invention between the chip
Pore structure realizes the connection on circuit, to put it more simply, simply showing the structural representation of the through silicon via in a chip in figure
Figure also includes other essential elements certainly.
Firstly, executing step 301, flatening process is executed to the back side of semiconductor substrate 200, the flatening process is
Grinding and/or polishing, to expose through silicon via 201.
As shown in Figure 2 A, the through silicon via 201 is formed in semiconductor substrate 200, and the semiconductor substrate 200 can be
At least one of material being previously mentioned below: silicon, silicon-on-insulator (SOI) silicon (SSOI) are laminated on insulator, on insulator
SiGe (S-SiGeOI) and germanium on insulator SiClx (SiGeOI) etc. is laminated.Could be formed with other in the substrate has
Source region or active device, details are not described herein.
For the through silicon via 201 among the semiconductor substrate 200, the through silicon via 201 includes centrally located leads
Electric layer 202 and the barrier layer 203 for being looped around 202 outside of conductive layer, wherein the width of the conductive layer 202 can be 20-
30 microns, the conductive layer 202 is formed by metal material, the metal material include one of Pt, Au, Cu, Ti and W or
It is a variety of, polysilicon can also be selected, limitation and a certain kind, not can be realized conducting function, in a reality of the invention
It applies in example as Ni metal, selects Ni metal that can not only reduce cost, and the technique for selecting metallic copper to form the through silicon via
It can be compatible with process simplification with prior art.The barrier layer 203 is to improve and fill metal in through silicon via
Adhesiveness, with a thickness of 300-500 angstroms, including one or more of titanium nitride TiN and titanium Ti, in a tool of the invention
The titanium nitride TiN and titanium Ti of lamination are chosen as to body in embodiment.
Step 302 is executed, is etched back to the bottom of the through silicon via to remove the conductive layer 202 of part, so that after etching
The surface of conductive layer is lower than the surface of semiconductor substrate 200 and barrier layer 203.
As shown in Figure 2 B, the bottom of the through silicon via is etched back to remove the conductive layer 202 of part.Being etched back to technique can
Meet the object height of conductive layer 202.Being etched back to technique can be using wet etching or dry etching, and being etched back to technique has
The high etching selection ratio of conductive layer.
In a specific embodiment of the invention, the material of conductive layer 202 is metallic copper, executes back quarter using wet etching
Etching technique performs etching metallic copper conductive layer using the liquid etchant containing sulfuric acid as an example.
It should be noted that above-mentioned engraving method is only exemplary, limitation and this method, those skilled in the art
Member can also select other common methods.
Step 303 is executed, the passivation with opening 205 is formed on the back side of semiconductor substrate 200 and through silicon via 201
Layer 204.
As shown in Figure 2 C, it is formed with the passivation layer 204 with opening 205 on semiconductor substrate 200, wherein described to open
Mouth 205 is located on the conductive layer 202, and in one example, the opening 205 is located at the middle part of the conductive layer 202, described
The width of opening can be 10-20 microns.
Illustratively, the material of the passivation layer 204 includes photo-sensistive polyimide (PI), benzocyclobutene (BCB), gathers
Benzoxazoles (PBO).
In a specific embodiment of the invention, the material of passivation layer 204 is photoactive material, through exposure and development and is toasted
The passivation layer 204 with opening 205 is formed after solidifying, wherein expose the light shield that uses for define the width of opening 205,
The light shield of length and position.
Step 304 is executed, using WLP process above-mentioned semiconductor device structure.
As shown in Figure 2 D, wiring layer (RDL) 206 is formed again on passivation layer 204, wherein the wiring layer again 206 is filled
The passivation layer 204 of the opening 205 and covering part.Wiring layer is used to be laid out the land positions of chip again again,
So that new welding zone is met the requirement to solder ball minimum spacing, and makes new welding zone according to array arrangement.
Illustratively, the material of the wiring layer again 206 includes metallic copper, and the thickness of the wiring layer again 206 can be
5-10 microns.Wiring layer 206 is responsible for for the semiconductor circuit in semiconductor substrate 200 being connected to external connection (for example, connection again
To solder ball, and then arrive PC plate) metal layer
In a specific embodiment of the invention, first sputtering forms one on a semiconductor substrate before formation copper again wiring layer
Then layer layers of copper or titanium layer form copper wiring layer again using electroplating technology in the layers of copper or titanium layer.
Then, passivation layer 207 is formed on wiring layer 206 again, the passivation layer 207 is for protecting wiring layer 206 again.It adopts
The passivation layer 207 is etched with photoetching process, to form opening in passivation layer 207, and the opening exposes wiring layer again
206, the opening is welding zone.It is equivalent to, forms second passivation layer with opening on the back side of the semiconductor substrate
207, the opening is located at the top of the wiring layer again.
Then, solder ball 208 is implanted into the opening of second passivation layer 207, the material of the solder ball 208 includes
Tin Silver Copper Alloy, the diameter of the solder ball 208 can be 259 microns.
Illustratively, it is initially formed before being implanted into solder ball ball lower metal layer (UBM), using the aperture of mask plate by solder
Ball is placed on UBM layer, and finally the silicon wafer for being formed with solder ball is pushed into reflow ovens and is flowed back.
The present invention provides a kind of methods of new preparation through silicon via, are grinding and polishing the TSV device back side to expose silicon
It is etched back to metal copper layer after through-hole, to prevent metallic copper from spreading and improve the reliability of device.Production side according to the present invention
Method improves the reliability of through silicon via using back side wafer grade encapsulation (WLP) technique；Meanwhile after executing grinding and polishing
The step of not being etched back to silicon wafer is to reduce the production cost.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (8)
1. a kind of method for making semiconductor devices, comprising:
Semiconductor substrate is provided, the front of the semiconductor substrate is formed with through silicon via；
The back side of semiconductor substrate described in planarization process treating is used to expose the bottom of the through silicon via, the through silicon via packet
Include conductive layer and barrier layer；
The bottom of the through silicon via is etched back to remove the conductive layer of part, so that the surface of the conductive layer after etching is lower than
The surface of semiconductor substrate and barrier layer；
First passivation layer with the first opening is formed on the back side of the semiconductor substrate, wherein first opening is located at
The top of the conductive layer.
2. the method according to claim 1, wherein further including after forming first passivation layer described
The step of wiring layer again is formed on first passivation layer, wherein the wiring layer again fills first opening and covering part
First passivation layer.
3. according to the method described in claim 2, it is characterized in that, further including after forming the wiring layer again described half
The step of second passivation layer with the second opening is formed on the back side of conductor substrate, wherein second opening is located at described
The top of wiring layer again.
4. according to the method described in claim 3, it is characterized in that, further including after forming second passivation layer described
The step of being implanted into solder ball in second opening.
5. the method according to claim 1, wherein the width of the conductive layer is 20-30 microns.
6. the method according to claim 1, wherein the width of first opening is 10-20 microns.
7. according to the method described in claim 2, it is characterized in that, the wiring layer again with a thickness of 5-10 microns, it is described again
The material of wiring layer is metallic copper.
8. the method according to claim 1, wherein the flatening process is grinding and/or polishing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410183949.XA CN105097647B (en) | 2014-05-04 | 2014-05-04 | A method of making semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410183949.XA CN105097647B (en) | 2014-05-04 | 2014-05-04 | A method of making semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105097647A CN105097647A (en) | 2015-11-25 |
| CN105097647B true CN105097647B (en) | 2018-12-21 |
Family
ID=54577778
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410183949.XA Active CN105097647B (en) | 2014-05-04 | 2014-05-04 | A method of making semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105097647B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111755384A (en) * | 2020-06-18 | 2020-10-09 | 通富微电子股份有限公司 | Semiconductor device and method of manufacture |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080122116A1 (en) * | 2006-11-23 | 2008-05-29 | Samsung Electronics Co., Ltd. | Method of forming metal layer wiring structure on backside of wafer, metal layer wiring structure formed using the method, method of stacking chip package, and chip package stack structure formed using the method |
| US8390130B1 (en) * | 2011-01-06 | 2013-03-05 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
| CN103000649A (en) * | 2012-11-22 | 2013-03-27 | 北京工业大学 | Packaging structure and manufacture method for complementary metal-oxide-semiconductor transistor (CMOS) image sensors |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101697573B1 (en) * | 2010-11-29 | 2017-01-19 | 삼성전자 주식회사 | Semiconductor device, fabricating method thereof, and semiconductor package comprising the semiconductor device |
-
2014
- 2014-05-04 CN CN201410183949.XA patent/CN105097647B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080122116A1 (en) * | 2006-11-23 | 2008-05-29 | Samsung Electronics Co., Ltd. | Method of forming metal layer wiring structure on backside of wafer, metal layer wiring structure formed using the method, method of stacking chip package, and chip package stack structure formed using the method |
| US8390130B1 (en) * | 2011-01-06 | 2013-03-05 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
| CN103000649A (en) * | 2012-11-22 | 2013-03-27 | 北京工业大学 | Packaging structure and manufacture method for complementary metal-oxide-semiconductor transistor (CMOS) image sensors |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105097647A (en) | 2015-11-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10115672B2 (en) | Double-sided semiconductor package and dual-mold method of making same | |
| US10283375B2 (en) | Integrated circuit package pad and methods of forming | |
| TWI756339B (en) | Semiconductor structure and manufacturing method thereof | |
| CN106328627B (en) | Semiconductor devices of stacking and forming method thereof | |
| US9741696B2 (en) | Thermal vias disposed in a substrate proximate to a well thereof | |
| TWI655690B (en) | Semiconductor device and method of forming a double-sided fan-out wafer level package | |
| US9515006B2 (en) | 3D device packaging using through-substrate posts | |
| TWI727463B (en) | Package and methods of forming the same | |
| KR101299875B1 (en) | Embedded 3D Interposer Structure | |
| US8168529B2 (en) | Forming seal ring in an integrated circuit die | |
| CN106158824B (en) | Ic package and forming method thereof | |
| CN106469701B (en) | Semiconductor device structure and forming method thereof | |
| TWI695432B (en) | Package and method of forming same | |
| KR101706119B1 (en) | Bowl-shaped solder structure | |
| US20150371938A1 (en) | Back-end-of-line stack for a stacked device | |
| KR20150085763A (en) | Packaging methods for semiconductor devices, packaged semiconductor devices, and design methods thereof | |
| US9812430B2 (en) | Package on-package method | |
| CN112447642A (en) | Semiconductor package and method of manufacturing the same | |
| CN105470235A (en) | Interposer and method of manufacturing the same | |
| US20150048496A1 (en) | Fabrication process and structure to form bumps aligned on tsv on chip backside | |
| TW201834174A (en) | Semiconductor system and device package including interconnect structure | |
| US9812414B1 (en) | Chip package and a manufacturing method thereof | |
| CN115411013A (en) | Chip packaging structure, chip packaging device and chip packaging method | |
| CN110931460A (en) | Chip packaging structure and packaging method thereof | |
| CN105097647B (en) | A method of making semiconductor devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |