CN110931460A - Chip packaging structure and packaging method thereof - Google Patents

Chip packaging structure and packaging method thereof Download PDF

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Publication number
CN110931460A
CN110931460A CN201911392601.0A CN201911392601A CN110931460A CN 110931460 A CN110931460 A CN 110931460A CN 201911392601 A CN201911392601 A CN 201911392601A CN 110931460 A CN110931460 A CN 110931460A
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Prior art keywords
layer
chip
metal
silicon
rewiring
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Inventor
任奎丽
陈栋
张黎
陈锦辉
赖志明
张国栋
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Jiangyin Changdian Advanced Packaging Co Ltd
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Jiangyin Changdian Advanced Packaging Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention relates to a chip packaging structure and a chip packaging method, and belongs to the technical field of semiconductor chip packaging. The circuit comprises a chip (10), a silicon through hole (11), a rewiring layer (14), a metal connecting column (21) and a solder ball (24) from top to bottom, and the chip (10) receives signals and transmits the signals downwards; the silicon through hole (11) below the electrode (19) vertically penetrates through the silicon substrate (12) and is fixedly connected with the rewiring layer (14), a metal connecting column (21) is arranged below the rewiring layer (14), and the longitudinal section of the metal connecting column (21) is in a flat-head welding ball shape; the encapsulating material layer (20) encapsulates the metal connecting column (21), and the solder balls (24) are fixedly connected with the lower surface of the metal connecting column (21). The invention provides a packaging structure and a packaging method which can not increase the thickness of a silicon wafer, but also can improve the mechanical strength of a packaged chip.

Description

Chip packaging structure and packaging method thereof
Technical Field
The invention relates to a chip packaging structure and a chip packaging method, and belongs to the technical field of semiconductor chip packaging.
Background
Through Silicon Via (TSV) interconnection technology is currently considered as one of the most advanced technologies in the semiconductor industry, and electrical connections are established from the active side to the back side of the chip using short vertical electrical connections or "through silicon vias" to provide the shortest interconnection path. Through silicon via filling is a difficult process for manufacturing the TSV, and the depth-to-width ratio of the TSV is one of the influencing factors of the difficult process. In a semiconductor product, the depth of a through silicon via is determined by the thickness of a silicon wafer, the width of the TSV must meet the design requirement and cannot be increased at will, the thicker the silicon wafer is, the deeper the through silicon via is, the greater the etching difficulty of the through silicon via is, the more difficult the continuous insulating layer/seed layer/barrier layer is formed on the side wall of the through silicon via, and meanwhile, the easier a hole is formed in the through silicon via filling process, the greater the filling difficulty is. In general, the packaging technology has the following difficulties: firstly, if the thickness of the silicon wafer is thicker, the deeper the silicon through hole is, the more difficult the processes of etching, insulating, seed layer forming, electroplating filling and the like of the silicon through hole are realized in the process, and the cost is higher; secondly, if the thickness of the silicon wafer is thinner, the chip has the problems of insufficient mechanical strength and easy breakage in use.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a packaging structure and a packaging method which can not increase the thickness of a silicon wafer, the realization difficulty of TSV and the processing cost, but also can improve the mechanical strength of a packaged chip.
The invention is realized by the following steps:
the invention relates to a chip packaging structure which comprises a chip, a silicon through hole, a rewiring layer, a metal connecting column and a welding ball from top to bottom, wherein signals received by the chip are transmitted downwards;
the chip comprises a silicon substrate, an electrode and a functional area, wherein the electrode and the functional area are arranged on the front surface of the silicon substrate, the rewiring layer is arranged on the lower surface of the chip, a plurality of silicon through holes for signal transmission are arranged below the electrode, the silicon through holes vertically penetrate through the silicon substrate and are fixedly connected with the rewiring layer, a metal connecting column is arranged below the rewiring layer, and the longitudinal section of the metal connecting column is in a flat-head welding ball shape;
the rewiring layer comprises at least one dielectric layer and at least one rewiring metal graphic layer which are arranged in a staggered mode, the dielectric layer wraps the rewiring metal graphic layer and/or is filled between the adjacent rewiring metal graphic layers, and the rewiring metal graphic layers are selectively electrically connected with each other and are connected with the silicon through holes;
the packaging structure is characterized by further comprising an encapsulating material layer, the encapsulating material layer encapsulates the metal connecting column, the lower surface of the metal connecting column is flush with the back surface of the encapsulating material layer and is exposed out of the lower surface of the metal connecting column, and the solder ball is fixedly connected with the lower surface of the metal connecting column.
Optionally, the cross section of the through silicon via includes but is not limited to a square hole and a circular hole.
Optionally, the number of electrodes is an even number.
The invention relates to a packaging method of a chip packaging structure, which comprises the following implementation steps:
the method comprises the following steps: providing a carrier wafer and a wafer with a functional area on the front surface, wherein the wafer is an aggregate of a plurality of chips, and the wafer and the carrier wafer are bonded by adopting a temporary bonding mode through temporary bonding glue;
step two: thinning the circular sheet by a grinding mode to form a chip with a functional area on the front surface, and thinning the chip to the required thickness;
step three: attaching or coating a mask material on the back of the chip, forming an opening in the mask material by photoetching, forming a silicon through hole array at a corresponding electrode according to a preset design by utilizing a deep silicon etching or laser drilling mode in a silicon substrate, and removing the mask material;
forming an insulating layer on the side wall of the through silicon via and the back of the chip by sputtering and other processes to insulate the through silicon via from the wafer;
step four: re-pasting or coating a mask material on the back surface of the chip, and filling metal in the mask pattern opening by using an electroplating mode to complete the through silicon via process; forming a multilayer rewiring layer and a multilayer rewiring layer opening on the back of the chip;
the rewiring layer comprises at least one dielectric layer and at least one rewiring metal graphic layer which are arranged in a mutually staggered mode, the dielectric layer wraps the rewiring metal graphic layer and/or is filled between the adjacent rewiring metal graphic layers, selective electric connection exists among the rewiring metal graphic layers, and the multilayer rewiring layer is fixedly connected with the metal connecting column through a plurality of layers of rewiring layer openings downwards;
step five: forming a metal connecting column in a welding ball shape at the opening of the multilayer re-wiring layer in a ball planting mode;
step six: coating an encapsulating material on the back of the functional chip arranged on the front surface in an encapsulating mode, and encapsulating the metal connecting column by the encapsulating material to form an encapsulating material layer;
step seven: grinding the encapsulating material layer and the metal connecting column by performing a planarization process of a chemical mechanical polishing step or a grinding step to expose the lower surface of the metal connecting column so that the back surface of the encapsulating material layer is flush with the lower surface of the metal connecting column; and then carrying out plasma treatment on the plane of the wafer, wherein the gas adopted by the plasma treatment is one or more of argon, oxygen and carbon tetrafluoride.
Step eight: forming a solder ball on the lower surface of the metal connecting column in a ball mounting mode to complete chip packaging and form a wafer-level packaging part;
step nine: separating the carrier wafer from the wafer level package by irradiating UV light or laser on the temporary bonding glue;
step ten: the wafer level packages are diced into individual packages using a laser or a blade.
Optionally, the metal connection post is made of one or more of tin, silver and copper.
Optionally, the metal connection stud has a thickness of 50-200 microns.
Optionally, in step four, the process of the redistribution layer further includes the following processes: an electroplating metal seed layer is formed through a sputtering process, the metal seed layer covers the side wall of the silicon through hole, and the back of the chip with the functional region on the front side is convenient for electroplating thickening; forming a through silicon via by electroplating filling; after the electroplating thickening is finished, removing the metal seed layer on the back surface of the chip by technologies such as corrosion and the like, and then carrying out plasma treatment on the wafer plane.
Optionally, the redistribution layer is made of one or more of copper, gold, and silver.
Optionally, the solder ball is made of one or more of tin, silver and copper.
Optionally, the through silicon via filling manner is half filling or solid filling.
Advantageous effects
The chip packaging structure provided by the invention has the advantages that the packaging material layer with the thickness of 50-150 microns is added on the back surface of the silicon wafer in a packaging mode, and the chip packaging structure has the following advantages:
1. the thickness of the silicon wafer is maintained to be 50-150 microns, under the TSV requirement of the same opening size, the depth-to-width ratio of the TSV is reduced, the etching difficulty of the through silicon via 11 is reduced, the continuous insulating layer/metal seed layer/barrier layer can be formed on the side wall of the through silicon via 11, the process difficulty is reduced, and the cost is reduced; the smaller depth-to-width ratio of the TSV is beneficial to filling the through silicon via 11, the formation of holes in the filling process is reduced, the yield is improved, the manufacturing difficulty is reduced, and the cost is reduced. The whole thickness of the wafer is increased through the encapsulating material layer, so that the problems that the mechanical strength is insufficient and the wafer is easy to break in the process of the wafer technology and the subsequent use process of the chip are solved;
2. the packaging method provided by the packaging structure has low process manufacturing difficulty and low cost, and the metal column for transmitting signals is formed before the packaging material layer to form the metal connecting column, so that the process steps are simple and easy to realize.
Drawings
FIG. 1 is a schematic cross-sectional view illustrating a chip package structure according to the present invention;
FIGS. 2A-2I are schematic diagrams of a process flow of the package structure of FIG. 1;
in the figure:
chip 10
Through-silicon via 11
Redistribution layer 14
Electrode 19
Dielectric layer 29
Encapsulating material layer 20
Metal connecting column 25
Back side 22 of encapsulating material layer
Redistribution layer 14
Solder ball 24
Lower surface 26 of the metal connecting post
Carrier wafer 30
The temporary bonding glue 31.
Detailed Description
Examples
Fig. 1 shows a chip package structure according to an embodiment of the present invention, and fig. 1 is a schematic cross-sectional view of the chip package structure according to the embodiment of the present invention.
The chip packaging structure comprises a chip 10, a silicon through hole 11, a re-wiring layer (RDL) 14, an encapsulating material layer 20, a metal connecting column 25 and a solder ball 24 from top to bottom, and signals received by the chip 10 are transmitted downwards to a circuit board such as a PCB.
The front side of the silicon substrate 12 of the chip 10 is provided with electrodes 19 and functional areas (not shown in the figures) which have a reduced thickness in the range of 50-150 μm. The number of the electrodes 19 is an even number, and generally, the electrodes 19 are arranged in an array. Several through-silicon vias 11 for signal transmission are provided in a pre-designed manner below the electrodes 19 in the silicon substrate 12 of the chip 10, and the cross section of the figure shows 2 through-silicon vias 11. The filling material of the through silicon via 11 is one or more of copper, gold and silver, the cross section of the through silicon via 11 includes but is not limited to a square hole and a circular hole, and the filling mode of the through silicon via 11 is semi-filling or solid filling.
The through silicon via 11 penetrates through the silicon substrate 12 from top to bottom and is fixedly connected with a redistribution layer (RDL) 14 on the lower surface of the chip.
The rewiring layer 14 comprises at least one dielectric layer 15 and at least one rewiring metal pattern layer which are arranged in a staggered mode, the dielectric layer wraps the rewiring metal pattern layer and/or is filled between the adjacent rewiring metal pattern layers, and the rewiring metal pattern layers are selectively electrically connected with each other and are connected with the through silicon vias 11 and used for transmitting electric signals. The material of the rewiring metal pattern layer is one or more of copper, gold and silver,
at least one metal connecting column 25 is arranged in the encapsulating material layer 20 according to a pre-designed scheme, and the longitudinal section of the metal connecting column 25 is in a flat-head welding ball shape. The metal connecting post 25 is made of one or more of tin, silver and copper. The height of the metal connection post 25 is 50-150 microns; the metal connecting column 25 is flush with the back of the packaging material layer, the metal connecting column 25 is connected with the solder ball 24, and the solder ball 24 is made of one or more of tin, silver and copper.
The functional region on the front surface of the chip 10 receives signals, and the signals are transmitted to the redistribution layer (RDL) 14 through the electrodes 19 and the through silicon vias 11, the redistribution layer (RDL) 14 is fixedly connected with the metal connecting columns 25 in the encapsulating material layer 20, and the signals of the chip 10 are transmitted downwards through the metal connecting columns 25 through the solder balls 24.
Aiming at the chip packaging structure, the invention provides a packaging method of the chip packaging structure, which comprises the following implementation steps:
the method comprises the following steps: as shown in fig. 2A, a carrier wafer 30 and a wafer with a functional area on the front surface are provided, the wafer is an aggregate of a plurality of chips 10, and the wafer and the carrier wafer 30 are bonded by a temporary bonding manner through a temporary bonding adhesive 31;
step two: as shown in fig. 2B, thinning the circular sheet by grinding to form the chip 10 with the functional region on the front surface, and thinning the chip 10 to a desired thickness, typically 50-150 μm;
step three: as shown in fig. 2C, a mask material is attached or coated on the back surface of the chip, an opening is formed in the mask material by photolithography, an array of through-silicon vias 11 is formed in the silicon substrate 12 at the corresponding electrode 19 by deep silicon etching or laser drilling according to a predetermined design, and the mask material is removed; through-silicon vias 11 include, but are not limited to, square holes, circular holes;
forming an insulating layer on the side wall of the through silicon via 11 and the back surface of the chip by sputtering and other processes to insulate the through silicon via 11 from the wafer (the insulating layer is not shown in the figure);
step four: as shown in fig. 2D, a mask material is attached or coated on the back surface of the chip again, and the metal is filled in the opening of the mask pattern by using an electroplating method, so as to complete the through silicon via 11 process; a multilayer rewiring layer 14 and a multilayer rewiring layer opening 17 are formed on the back of the chip, and the rewiring layer (RDL) 14 is made of one or more of copper, gold and silver;
the rewiring layer 14 comprises at least one dielectric layer 15 and at least one rewiring metal pattern layer which are arranged in a staggered mode, the dielectric layer wraps the rewiring metal pattern layer and/or is filled between the adjacent rewiring metal pattern layers, selective electric connection exists among the rewiring metal pattern layers, and the multilayer rewiring layer 14 is fixedly connected with the metal connecting column 25 downwards through a multilayer rewiring layer opening 17;
specifically, an electroplating metal seed layer is formed through a sputtering process, the metal seed layer covers the side wall of the through silicon via 11, and the back surface of the chip with the functional region on the front surface is convenient for electroplating thickening; forming the through silicon via 11 by electroplating and filling, wherein the filling material can be one or more of gold, silver and copper, and the filling mode can be half filling or full filling; and after the electroplating thickening is finished, removing the metal seed layer on the back surface of the chip by technologies such as corrosion and the like, and then carrying out plasma treatment on the wafer plane, wherein the gas adopted by the plasma treatment is one or more of argon, oxygen and carbon tetrafluoride.
Step five: as shown in fig. 2E, a solder ball-shaped metal connection stud 25 is formed in the opening 17 of the multilayer re-wiring layer by a ball-planting method, and the material of the metal connection stud 25 is one or more of tin, silver and copper;
step six: as shown in fig. 2F, an encapsulating material is coated on the back surface of the front surface of the functional chip, and the metal connection posts 25 are encapsulated by the encapsulating material to form an encapsulating material layer 20;
step seven: as shown in fig. 2G, the encapsulant layer 20 and the metal connection posts 25 are ground by performing a planarization process of a Chemical Mechanical Polishing (CMP) step or a grinding step, exposing the lower surfaces 26 of the metal connection posts and making the backside 22 of the encapsulant layer flush with the lower surfaces 26 of the metal connection posts; and then carrying out plasma treatment on the plane of the wafer, wherein the gas adopted by the plasma treatment is one or more of argon, oxygen and carbon tetrafluoride.
Step eight: as shown in fig. 2H, solder balls 24 are formed on the lower surfaces 26 of the metal connection posts by ball-mounting, so as to complete chip packaging and form a wafer-level package, wherein the solder balls 24 are made of one or more of tin, silver and copper;
step nine: as shown in fig. 2I, the carrier wafer 30 is separated from the wafer level package by irradiating UV light or laser on the temporary bonding paste 31;
step ten: the wafer level packages are diced into individual packages using a laser or a blade.
The above-mentioned embodiments are intended to explain the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A chip packaging structure is characterized by comprising a chip (10), a silicon through hole (11), a rewiring layer (14), a metal connecting column (25) and a solder ball (24) from top to bottom, wherein signals received by the chip (10) are transmitted downwards;
the chip (10) comprises a silicon substrate (12), an electrode (19) and a functional area, wherein the electrode (19) and the functional area are arranged on the front surface of the silicon substrate (12), the rewiring layer (14) is arranged on the lower surface of the chip (10), a plurality of silicon through holes (11) for signal transmission are arranged below the electrode (19), the silicon through holes (11) penetrate through the silicon substrate (12) up and down and are fixedly connected with the rewiring layer (14), a metal connecting column (25) is arranged below the rewiring layer (14), and the longitudinal section of the metal connecting column (25) is in the shape of a flat-head welding sphere;
the rewiring layer (14) comprises at least one dielectric layer (15) and at least one rewiring metal pattern layer which is arranged in a staggered mode, the dielectric layer wraps the rewiring metal pattern layer and/or is filled between the adjacent rewiring metal pattern layers, and the rewiring metal pattern layers are selectively electrically connected with each other and are connected with the through silicon vias (11);
the packaging structure is characterized by further comprising an encapsulating material layer (20), the encapsulating material layer (20) encapsulates the metal connecting columns (25), the lower surfaces of the metal connecting columns (25) are flush with the back surface of the encapsulating material layer (20) and are exposed out of the lower surfaces of the metal connecting columns (25), and the solder balls (24) are fixedly connected with the lower surfaces of the metal connecting columns (25).
2. The package structure according to claim 1, wherein the cross-section of the through-silicon-via (11) includes, but is not limited to, a square hole, a circular hole.
3. The encapsulation structure according to claim 1, characterized in that the number of electrodes (19) is an even number.
4. The packaging method of the packaging structure of the chip comprises the following implementation steps:
the method comprises the following steps: providing a carrier wafer (30) and a wafer with a functional area on the front surface, wherein the wafer is an aggregate of a plurality of chips (10), and bonding the wafer and the carrier wafer (30) through a temporary bonding adhesive (31) in a temporary bonding mode;
step two: thinning the circular sheet by a grinding mode to form a chip (10) with a functional area on the front surface, and thinning the chip (10) to the required thickness;
step three: pasting or coating a mask material on the back surface of the chip, forming an opening in the mask material through photoetching, forming a silicon through hole (11) array at a corresponding electrode (19) in a silicon substrate (12) in a deep silicon etching or laser drilling mode according to the preset design, and removing the mask material;
forming an insulating layer on the side wall of the through silicon via (11) and the back of the chip through sputtering and other processes to insulate the through silicon via (11) from the wafer;
step four: re-pasting or coating a mask material on the back of the chip, and filling metal in the mask pattern opening by using an electroplating mode to finish the through silicon via (11) process; a multilayer rewiring layer (14) and a multilayer rewiring layer opening (17) are formed on the back surface of the chip;
the rewiring layer (14) comprises at least one dielectric layer (15) and at least one rewiring metal graphic layer which are arranged in a mutually staggered mode, the dielectric layer wraps the rewiring metal graphic layer and/or is filled between the adjacent rewiring metal graphic layers, selective electric connection exists among the rewiring metal graphic layers, and the multilayer rewiring layer (14) is fixedly connected with the metal connecting column (25) downwards through a multilayer rewiring layer opening (17);
step five: forming a metal connecting column (25) in a welding ball shape on the opening (17) of the multilayer rewiring layer in a ball planting mode;
step six: coating an encapsulating material on the back surface of the chip with the function on the front surface in an encapsulating mode, and wrapping a metal connecting column (25) with the encapsulating material to form an encapsulating material layer (20);
step seven: grinding the encapsulating layer (20) and the metal connection posts (25) by performing a planarization process of a chemical mechanical polishing step or a grinding step, exposing the lower surfaces (26) of the metal connection posts and making the back surface (22) of the encapsulating layer flush with the lower surfaces (26) of the metal connection posts; performing plasma treatment on the plane of the wafer, wherein the gas adopted by the plasma treatment is one or more of argon, oxygen and carbon tetrafluoride;
step eight: forming solder balls (24) on the lower surfaces (26) of the metal connecting columns in a ball planting mode to finish chip packaging and form a wafer-level packaging piece;
step nine: separating the carrier wafer (30) from the wafer level package by irradiating UV light or laser light on the temporary bonding glue (31);
step ten: the wafer level packages are diced into individual packages using a laser or a blade.
5. The encapsulation method according to claim 4, wherein the metal connection posts (21) are made of one or more of tin, silver and copper.
6. The encapsulation method according to claim 4 or 5, characterized in that the thickness of the metal connection stud (21) is 50-200 microns.
7. The packaging method according to claim 4, wherein in step four, the process of the re-wiring layer (14) further comprises the process of: an electroplating metal seed layer is formed through a sputtering process, the metal seed layer covers the side wall of the silicon through hole (11) and the back of the chip with the functional region on the front side, and electroplating thickening is facilitated; forming a through silicon via (11) by electroplating filling; after the electroplating thickening is finished, removing the metal seed layer on the back surface of the chip by technologies such as corrosion and the like, and then carrying out plasma treatment on the wafer plane.
8. The encapsulation method according to claim 4, wherein the redistribution layer (14) is made of one or more of copper, gold, and silver.
9. The packaging method according to claim 4, wherein the solder balls (24) are made of one or more of tin, silver and copper.
10. The packaging method according to claim 4, wherein the through silicon via (11) is filled in a semi-filled or solid manner.
CN201911392601.0A 2019-12-30 2019-12-30 Chip packaging structure and packaging method thereof Pending CN110931460A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112158793A (en) * 2020-10-28 2021-01-01 深圳市华普微电子有限公司 Sensor, sensor packaging method, wafer and small-size air pressure sensor
CN115799196A (en) * 2023-02-07 2023-03-14 季华实验室 Chip packaging structure and method and electronic equipment
CN116435258A (en) * 2023-06-13 2023-07-14 中诚华隆计算机技术有限公司 Packaging method and packaging structure of chip

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112158793A (en) * 2020-10-28 2021-01-01 深圳市华普微电子有限公司 Sensor, sensor packaging method, wafer and small-size air pressure sensor
CN115799196A (en) * 2023-02-07 2023-03-14 季华实验室 Chip packaging structure and method and electronic equipment
CN116435258A (en) * 2023-06-13 2023-07-14 中诚华隆计算机技术有限公司 Packaging method and packaging structure of chip
CN116435258B (en) * 2023-06-13 2023-09-26 中诚华隆计算机技术有限公司 Packaging method and packaging structure of chip

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