CN110931458A - Chip packaging structure and packaging method thereof - Google Patents
Chip packaging structure and packaging method thereof Download PDFInfo
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- CN110931458A CN110931458A CN201911392580.2A CN201911392580A CN110931458A CN 110931458 A CN110931458 A CN 110931458A CN 201911392580 A CN201911392580 A CN 201911392580A CN 110931458 A CN110931458 A CN 110931458A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 37
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- 239000002184 metal Substances 0.000 claims abstract description 51
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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Abstract
The invention relates to a chip packaging structure and a chip packaging method, and belongs to the technical field of semiconductor chip packaging. The circuit comprises a chip (10), a silicon through hole (11), a rewiring layer (14), a metal connecting column (21) and a solder ball (24) from top to bottom, and the chip (10) receives signals and transmits the signals downwards; the silicon through hole (11) below the electrode (19) vertically penetrates through the silicon substrate (12) and is fixedly connected with the rewiring layer (14), a metal connecting column (21) is arranged below the rewiring layer (14), and the longitudinal section of the metal connecting column (21) is in a trapezoidal shape; the encapsulating material layer (20) encapsulates the rewiring layer (14) and the metal connecting columns (21), and the solder balls (24) are fixedly connected with the lower surfaces of the metal connecting columns (21). The invention provides a packaging structure and a packaging method which can not increase the thickness of a silicon wafer, but also can improve the mechanical strength of a packaged chip.
Description
Technical Field
The invention relates to a chip packaging structure and a chip packaging method, and belongs to the technical field of semiconductor chip packaging.
Background
Through Silicon Via (TSV) interconnection technology is currently considered as one of the most advanced technologies in the semiconductor industry, and electrical connections are established from the active side to the back side of the chip using short vertical electrical connections or "through silicon vias" to provide the shortest interconnection path. Through silicon via filling is a difficult process for manufacturing the TSV, and the depth-to-width ratio of the TSV is one of the influencing factors of the difficult process. In a semiconductor product, the depth of a through silicon via is determined by the thickness of a silicon wafer, the width of the TSV must meet the design requirement and cannot be increased at will, the thicker the silicon wafer is, the deeper the through silicon via is, the greater the etching difficulty of the through silicon via is, the more difficult the continuous insulating layer/seed layer/barrier layer is formed on the side wall of the through silicon via, and meanwhile, the easier a hole is formed in the through silicon via filling process, the greater the filling difficulty is. In general, the packaging technology has the following difficulties: firstly, if the thickness of the silicon wafer is thicker, the deeper the silicon through hole is, the more difficult the processes of etching, insulating, seed layer forming, electroplating filling and the like of the silicon through hole are realized in the process, and the cost is higher; secondly, if the thickness of the silicon wafer is thinner, the chip has the problems of insufficient mechanical strength and easy breakage in use.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a packaging structure and a packaging method which can not increase the thickness of a silicon wafer, the realization difficulty of TSV and the processing cost, but also can improve the mechanical strength of a packaged chip.
The invention is realized by the following steps:
the invention provides a chip packaging structure which comprises a chip, a silicon through hole, a rewiring layer, a metal connecting column and a solder ball from top to bottom, wherein signals received by the chip are transmitted downwards;
the chip comprises a silicon substrate, an electrode and a functional area, wherein the electrode and the functional area are arranged on the front surface of the silicon substrate, the rewiring layer is arranged on the lower surface of the chip, a plurality of silicon through holes for signal transmission are arranged below the electrode, the silicon through holes vertically penetrate through the silicon substrate and are fixedly connected with the rewiring layer, a metal connecting column is arranged below the rewiring layer, and the longitudinal section of the metal connecting column is in a trapezoidal shape;
the packaging structure further comprises a packaging material layer, the packaging material layer packages the rewiring layer and the metal connecting column, the lower surface of the metal connecting column is flush with the back surface of the packaging material layer and is exposed out of the lower surface of the metal connecting column, and the solder ball is fixedly connected with the lower surface of the metal connecting column.
Optionally, the cross section of the through silicon via includes but is not limited to a square hole and a circular hole.
Optionally, the number of electrodes is an even number.
The invention provides a packaging method of a chip packaging structure, which comprises the following implementation steps:
the method comprises the following steps: providing a carrier wafer and a wafer with a functional area on the front surface, wherein the wafer is an aggregate of a plurality of chips 10, and the wafer and the carrier wafer are bonded by adopting a temporary bonding mode through temporary bonding glue;
step two: thinning the circular sheet by a grinding mode to form a chip with a functional area on the front surface, and thinning the chip to the required thickness;
step three: attaching or coating a mask material on the back of the chip, forming an opening in the mask material by photoetching, forming a silicon through hole array at a corresponding electrode according to a preset design by utilizing a deep silicon etching or laser drilling mode in a silicon substrate, and removing the mask material;
forming an insulating layer on the side wall of the through silicon via and the back of the chip by sputtering and other processes to insulate the through silicon via from the wafer;
step four: re-pasting or coating a mask material on the back of the chip, filling metal in the opening of the mask pattern by using an electroplating mode to form a through silicon via, and simultaneously forming a rewiring layer on the back of the chip according to a preset scheme;
an electroplating seed layer is formed through a sputtering process, and the seed layer covers the side wall of the through silicon via and the back of the chip, so that electroplating thickening is facilitated; after the electroplating thickening is finished, removing the seed layer on the back surface of the chip by a corrosion process, and then carrying out plasma treatment on the plane of the wafer;
step five: coating an encapsulating material on the back of the chip in an encapsulating mode to form an encapsulating material layer, and thinning the encapsulating material layer to the required thickness through a chemical mechanical polishing process or a grinding process;
step six: forming a through hole on the encapsulating material layer according to a pre-designed scheme by utilizing a laser drilling mode, and exposing the lower surface of the rewiring layer;
step seven: forming a metal seed layer on the side wall and the bottom of the through hole by a sputtering process;
step eight: filling the through hole in a ball planting mode, forming a metal connecting column fixedly connected with the rewiring layer by the solder and the metal seed layer in the through hole and forming a solder ball below the metal connecting column, finishing chip packaging and forming a wafer-level packaging piece;
step nine: separating the carrier wafer from the wafer level package by irradiating UV light or laser on the temporary bonding glue;
step ten: the wafer level packages are diced into individual packages using a laser or a blade.
Optionally, the metal connection post is made of one or more of tin, silver and copper.
Optionally, the metal connection stud has a thickness of 50-200 microns.
Optionally, the solder ball is made of one or more of tin, silver and copper.
Optionally, the through silicon via filling manner is half filling or solid filling.
Advantageous effects
The chip packaging structure provided by the invention has the advantages that the packaging material layer with the thickness of 50-150 microns is added on the back surface of the silicon wafer in a packaging mode, and the chip packaging structure has the following advantages:
1. the thickness of the silicon chip is maintained to be 50-150 microns, under the TSV requirement of the same opening size, the depth-to-width ratio of the TSV is reduced, the etching difficulty of the through silicon via is reduced, a continuous insulating layer/seed layer/barrier layer is formed on the side wall of the through silicon via, the process difficulty is reduced, and the cost is reduced; the smaller depth-to-width ratio of the TSV is beneficial to filling of the through silicon via, formation of holes in the filling process is reduced, the yield is improved, the manufacturing difficulty is reduced, and the cost is reduced. The whole thickness of the wafer is increased through the encapsulating material layer, so that the problems that the mechanical strength is insufficient and the wafer is easy to break in the process of the wafer technology and the subsequent use process of the chip are solved;
2. the packaging method provided by the packaging structure has low process manufacturing difficulty and low cost, and the metal column for transmitting signals is formed before the packaging material layer to form the metal connecting column, so that the process steps are simple and easy to realize.
Drawings
FIG. 1 is a schematic cross-sectional view illustrating a chip package structure according to the present invention;
FIGS. 2A-2H are schematic diagrams illustrating a process flow of the package structure of FIG. 1;
in the figure:
Through-silicon via 11
Electrode 19
Encapsulating material layer 20
Through hole 27
Carrier wafer 30
The temporary bonding glue 31.
Detailed Description
Examples
Fig. 1 shows a chip package structure according to an embodiment of the present invention, and fig. 1 is a schematic cross-sectional view of the chip package structure according to the embodiment of the present invention. The chip packaging structure comprises a chip 10, a silicon through hole 11, a re-wiring layer (RDL) 14, an encapsulating material layer 20, a metal connecting column 21 and a solder ball 24 from top to bottom, and signals received by the chip 10 are transmitted downwards to a circuit board such as a PCB.
The front side of the silicon substrate 12 of the chip 10 is provided with electrodes 19 and functional areas (not shown in the figures) which have a reduced thickness in the range of 50-150 μm. The number of the electrodes 19 is an even number, and generally, the electrodes 19 are arranged in an array. Several through-silicon vias 11 for signal transmission are provided in a pre-designed manner below the electrodes 19 in the silicon substrate 12 of the chip 10, and the cross section of the figure shows 2 through-silicon vias 11. The filling material of the through silicon via 11 is one or more of copper, gold and silver, the cross section of the through silicon via 11 includes but is not limited to a square hole and a circular hole, and the filling mode of the through silicon via 11 is semi-filling or solid filling.
The through silicon via 11 penetrates through the silicon substrate 12 from top to bottom and is fixedly connected with a redistribution layer (RDL) 14 on the lower surface of the chip.
The redistribution layer (RDL) 14 is made of one or more of copper, gold, and silver, and is connected to the through-silicon via 11 for transmitting electrical signals.
The encapsulating layer 20 encapsulates the redistribution layer 14 and the metal connection posts 21. At least one metal connecting column 21 is arranged in the encapsulating material layer 20 according to a pre-designed scheme, and the longitudinal section of the metal connecting column 21 is in a trapezoid shape. The metal connecting post 21 is made of one or more of tin, silver and copper. The height of the metal connecting column 21 is 50-150 micrometers; the metal connecting column 21 is flush with the back 26 of the encapsulating material layer, the metal connecting column 21 is connected with a solder ball 24, and the solder ball 24 is made of one or more of tin, silver and copper.
The functional region on the front surface of the chip 10 receives signals, and the signals are transmitted to the redistribution layer (RDL) 14 through the electrodes 19 and the through silicon vias 11, the redistribution layer (RDL) 14 is fixedly connected with the metal connection posts 21 in the encapsulating material layer 20, and the signals of the chip are transmitted downwards through the metal connection posts 21 through the solder balls 24.
Aiming at the chip packaging structure, the invention provides a packaging method of the chip packaging structure, which comprises the following implementation steps:
the method comprises the following steps: as shown in fig. 2A, a carrier wafer 30 and a wafer with a functional area on the front surface are provided, the wafer is an aggregate of a plurality of chips 10, and the wafer and the carrier wafer 30 are bonded by a temporary bonding manner through a temporary bonding adhesive 31;
step two: as shown in fig. 2B, thinning the circular sheet by grinding to form the chip 10 with the functional region on the front surface, and thinning the chip 10 to a desired thickness, typically 50-150 μm;
step three: as shown in fig. 2C, a mask material is attached or coated on the back surface of the chip, an opening is formed in the mask material by photolithography, an array of through-silicon vias 11 is formed in the silicon substrate 12 at the corresponding electrode 19 by deep silicon etching or laser drilling according to a predetermined design, and the mask material is removed; (ii) a The cross section of the through silicon via 11 includes but is not limited to a square hole, a circular hole;
forming an insulating layer on the side wall of the through silicon via 11 and the back surface of the chip by sputtering and other processes to insulate the through silicon via 11 from the wafer (the insulating layer is not shown in the figure);
step four: as shown in fig. 2D, a mask material is attached or coated on the back surface of the chip again, metal is filled in the opening of the mask pattern by electroplating to form a through-silicon-via 11, and a redistribution layer 14 is formed on the back surface of the chip according to a preset scheme, wherein the redistribution layer 14 is made of one or more of copper, gold and silver;
specifically, an electroplating seed layer is formed through processes such as sputtering and the like, and the seed layer covers the side wall of the through silicon via 11 and the back of the chip, so that electroplating thickening is facilitated; and after the electroplating thickening is finished, removing the seed layer on the back surface of the chip by technologies such as corrosion and the like, and then carrying out plasma treatment on the wafer plane, wherein the gas adopted by the plasma treatment is one or more of argon, oxygen and carbon tetrafluoride.
Step five: as shown in fig. 2E, an encapsulant layer 20 is formed by applying an encapsulant material to the back surface of the chip by means of encapsulation, and the encapsulant layer is thinned to a desired thickness, typically 50-200 μm, by a Chemical Mechanical Polishing (CMP) step or grinding;
step six: as shown in fig. 2F, a through hole 27 is formed on the upper surface of the encapsulating material layer by laser drilling or the like according to a pre-designed scheme to expose the lower surface of the redistribution layer 14;
step eight: as shown in fig. 2G, the through hole 27 is filled by ball-planting, the solder in the through hole 27 and the metal seed layer form a metal connection post 21 fixedly connected with the redistribution layer 14 and a solder ball 24 below the metal connection post 21, so as to complete chip packaging and form a wafer-level package; the metal connecting column 21 and the solder ball 24 are made of one or more of tin, silver and copper;
step nine: as shown in fig. 2H, the carrier wafer is separated from the wafer level package by irradiating UV light or laser on the temporary bonding paste 31;
step ten: the wafer level packages are diced into individual packages using a laser or a blade.
The above-mentioned embodiments are intended to explain the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A chip package structure is characterized in that,
the circuit comprises a chip (10), a silicon through hole (11), a rewiring layer (14), a metal connecting column (21) and a solder ball (24) from top to bottom, and the chip (10) receives signals and transmits the signals downwards;
the chip (10) comprises a silicon substrate (12), an electrode (19) and a functional area, wherein the electrode (19) and the functional area are arranged on the front surface of the silicon substrate (12), the rewiring layer (14) is arranged on the lower surface of the chip (10), a plurality of silicon through holes (11) for transmitting signals are arranged below the electrode (19), the silicon through holes (11) penetrate through the silicon substrate (12) up and down and are fixedly connected with the rewiring layer (14), a metal connecting column (21) is arranged below the rewiring layer (14), and the longitudinal section of the metal connecting column (21) is in a trapezoidal shape;
the packaging structure is characterized by further comprising a packaging material layer (20), the packaging material layer (20) packages the rewiring layer (14) and the metal connecting columns (21), the lower surfaces of the metal connecting columns (21) are flush with the back surface of the packaging material layer (20) and exposed out of the lower surfaces of the metal connecting columns (21), and the solder balls (24) are fixedly connected with the lower surfaces of the metal connecting columns (21).
2. The package structure according to claim 1, wherein the cross-section of the through-silicon-via (11) includes, but is not limited to, a square hole, a circular hole.
3. The encapsulation structure according to claim 1, characterized in that the number of electrodes (19) is an even number.
4. The packaging method of the packaging structure of the chip comprises the following implementation steps:
the method comprises the following steps: providing a carrier wafer (30) and a wafer with a functional area on the front surface, wherein the wafer is an aggregate of a plurality of chips (10), and bonding the wafer and the carrier wafer (30) through a temporary bonding adhesive (31) in a temporary bonding mode;
step two: thinning the circular sheet by a grinding mode to form a chip (10) with a functional area on the front surface, and thinning the chip (10) to the required thickness;
step three: pasting or coating a mask material on the back surface of the chip, forming an opening in the mask material through photoetching, forming a silicon through hole (11) array at a corresponding electrode (19) in a silicon substrate (12) in a deep silicon etching or laser drilling mode according to the preset design, and removing the mask material;
forming an insulating layer on the side wall of the through silicon via (11) and the back of the chip through sputtering and other processes to insulate the through silicon via (11) from the wafer;
step four: re-pasting or coating a mask material on the back of the chip, filling metal in the opening of the mask pattern by using an electroplating mode to form a through silicon via (11), and simultaneously forming a rewiring layer (14) on the back of the chip according to a preset scheme;
an electroplating seed layer is formed through a sputtering process, and the seed layer covers the side wall of the through silicon via (11) and the back of the chip, so that electroplating thickening is facilitated; after the electroplating thickening is finished, removing the seed layer on the back surface of the chip by a corrosion process, and then carrying out plasma treatment on the plane of the wafer;
step five: coating the encapsulating material on the back surface of the chip in an encapsulating mode to form an encapsulating material layer (20), and thinning the encapsulating material layer (20) to the required thickness through a chemical mechanical polishing process or a grinding process;
step six: forming a through hole (27) in the encapsulating material layer (20) according to a pre-designed scheme by utilizing a laser drilling mode, and exposing the lower surface of the rewiring layer (14);
step seven: forming a metal seed layer on the side wall and the bottom of the through hole (27) through a sputtering process;
step eight: filling the through hole (27) in a ball planting mode, forming a metal connecting column (21) fixedly connected with the rewiring layer (14) and a solder ball (24) below the metal connecting column (21) by the solder and the metal seed layer in the through hole (27), completing chip packaging, and forming a wafer-level packaging piece;
step nine: separating the carrier wafer from the wafer level package by irradiating UV light or laser light on the temporary bonding glue (31);
step ten: the wafer level packages are diced into individual packages using a laser or a blade.
5. The encapsulation method according to claim 4, wherein the metal connection posts (21) are made of one or more of tin, silver and copper.
6. The encapsulation method according to claim 4 or 5, characterized in that the thickness of the metal connection stud (21) is 50-200 microns.
7. The packaging method according to claim 4, wherein the solder balls (24) are made of one or more of tin, silver and copper.
8. The chip packaging method according to claim 4, wherein the through silicon via (11) is filled in a semi-filled or solid manner.
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