CN105097647A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- CN105097647A CN105097647A CN201410183949.XA CN201410183949A CN105097647A CN 105097647 A CN105097647 A CN 105097647A CN 201410183949 A CN201410183949 A CN 201410183949A CN 105097647 A CN105097647 A CN 105097647A
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Abstract
The present invention relates to a method of manufacturing a semiconductor device. The method is characterized by grinding and/or polishing the backside of a through silicon via (TSV) device to expose a silicon through hole, and then back etching a metal copper layer, thereby preventing the metal copper from diffusing and improving the reliability of the device. According to the manufacturing method of the present invention, by a backside wafer level packaging (WLP) technology, the reliability of the silicon through hole is improved, at the same time, a step of back etching a silicon wafer is saved after the grinding and polishing, thereby reducing the manufacturing cost.
Description
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to a kind of method making semiconductor device.
Background technology
At consumer electronics field, multifunctional equipment is more and more subject to liking of consumer, compared to the simple equipment of function, multifunctional equipment manufacturing process is more complicated, such as need the chip of integrated multiple difference in functionality in circuit version, thus there is 3D integrated circuit (integratedcircuit, IC) technology, 3D integrated circuit (integratedcircuit, IC) a kind of system-level integrated morphology is defined as, multiple chip is stacking in vertical plane direction, thus saving space, multiple pin can be drawn as required in the marginal portion of each chip, utilize these pins as required, by interconnected by metal wire for the chip needing to be connected to each other, but still there is a lot of deficiency in aforesaid way, such as stacked chips quantity is more, and the annexation more complicated between chip, so will need to utilize many metal line, final wire laying mode will be more chaotic, and volume can be caused to increase.
Therefore, at present at described 3D integrated circuit (integratedcircuit, IC) silicon through hole (ThroughSiliconVia is mostly adopted in technology, TSV), silicon through hole is a kind of perpendicular interconnection penetrating Silicon Wafer or chip, TSV can storehouse multi-plate chip, (processing procedure can be divided into again first boring and rear boring two kinds to get out duck eye at chip, ViaFist, ViaLast), enter metal from underfill, Silicon Wafer is holed (via) with etching or laser mode, then with electric conducting material as the materials such as copper, polysilicon, tungsten fill up.Thus it is interconnected to realize between different silicon chip.
The preparation method of current described silicon through hole also exists a lot of problem, such as, because the oxide skin(coating) metallic copper diffusion phenomena caused that rupture make integrated circuit have the excessive risk of reliability failures.
Therefore, a kind of preparation method of new semiconductor device silicon through hole is needed, to solve the problems of the prior art.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
The present invention, in order to overcome current existing problems, provides a kind of method making semiconductor device, comprising: provide Semiconductor substrate, and the front of described Semiconductor substrate is formed with silicon through hole; Adopt the back side of Semiconductor substrate described in flatening process process to expose the bottom of described silicon through hole, described silicon through hole comprises conductive layer and barrier layer; Go back to the bottom of the described silicon through hole of etching to remove the described conductive layer of part; The back side of described Semiconductor substrate is formed first passivation layer with the first opening, and wherein said first opening is positioned at the top of described conductive layer.
Exemplarily, be also included in the step forming again wiring layer after forming described first passivation layer on described first passivation layer, wherein, described wiring layer again fills described first passivation layer of described first opening and cover part.
Exemplarily, on the back side of described Semiconductor substrate, after being also included in described in formation again wiring layer, form the step with the second passivation layer of the second opening, wherein, the top of wiring layer again described in described second opening is positioned at.
Exemplarily, in described second opening, implant the step of solder ball after being also included in described second passivation layer of formation.
Exemplarily, the width of described conductive layer is 20-30 micron.
Exemplarily, the width of described first opening is 10-20 micron.
Exemplarily, the thickness of described wiring layer is again 5-10 micron, and the material of described wiring layer is again metallic copper.
Exemplarily, described flatening process is grinding and/or polishing.
The invention provides a kind of method preparing silicon through hole newly, after exposing silicon through hole, return etching metal copper layer in grinding and the polishing TSV device back side, spread to stop metallic copper and improve the reliability of device.According to manufacture method of the present invention, back side wafer level encapsulation (WLP) technique is adopted to improve the reliability of silicon through hole; Meanwhile, after execution grinding and polishing, do not return the step of etched silicon wafer thus reduce cost of manufacture.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
Fig. 1 is a kind of process chart making through-silicon via structure;
The structural representation of the device that Fig. 2 A-2D obtains for the correlation step making through-silicon via structure according to one embodiment of the present invention;
Fig. 3 is the process chart making through-silicon via structure according to one embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed description is proposed, to illustrate that the present invention makes the method for semiconductor device.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should give it is noted that term used here is only to describe specific embodiment, and be not intended to restricted root according to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative be also intended to comprise plural form.In addition, it is to be further understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.Should be understood that, providing these embodiments to be of the present inventionly disclose thorough and complete to make, and the design of these exemplary embodiments fully being conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, exaggerate the thickness in layer and region, and use the element that identical Reference numeral represents identical, thus will omit description of them
As shown in Figure 1, be a kind of process chart making through-silicon via structure.
In a step 101, silicon wafer front is formed silicon through hole, in one example, make integrated circuit component on silicon, form oxide skin(coating) and dielectric layer on silicon, etch described dielectric layer, described oxide skin(coating) and described silicon wafer to form groove, deposition forms barrier layer in the trench, described barrier layer forms copper metal layer to fill described groove, subsequent step also comprises formation aluminium or copper metal conducting layer.
In a step 102, between silicon wafer front and another wafer, carry out bonding, in one example, the copper packing of silicon wafer deposits electroless plated metal layer, to form the pad of silicon wafer to another wafer, then, perform thermal diffusion bonding technology.
In step 103, grinding and glossing are performed to expose silicon through hole to the silicon wafer back side, in an example, the silicon wafer after bonding is inverted, adopts grinding back surface and glossing to process described silicon wafer, to expose silicon through hole.
At step 104, the etched silicon wafer back side is gone back to remove the silicon wafer of part, to make silicon through hole higher than silicon wafer surface.
In step 105, the silicon wafer back side forms spacer material layer, the material of described spacer material layer can be oxide, to prevent the pollution to silicon wafer.
The method of above-mentioned making silicon through hole is easy to produce and rupture the metallic copper diffusion phenomena caused by oxide skin(coating), increases the excessive risk of IC reliability inefficacy.
The present invention is in order to solve Problems existing in current semiconductor device silicon through hole preparation process, provide a kind of preparation method of semiconductor device silicon through hole, the structural representation of the device that Fig. 2 A-2D obtains for the correlation step making through-silicon via structure according to one embodiment of the present invention; Fig. 3 is the process chart making through-silicon via structure according to one embodiment of the present invention.
Below in conjunction with Fig. 2 A-2D and Fig. 3, preparation method of the present invention is described in detail.It should be noted that, performing the step before polishing and grinding to silicon wafer, those skilled in the art is known, is not just described in detail at this.Simultaneously, the structure of the chip of the silicon through hole of wanted sequencing is only gived in accompanying drawing 2A-2D, the multiple chips comprised in the integrated circuit of semiconductor device are as described in Figure interconnected, form lamination, by the connection on through-silicon via structure realizing circuit of the present invention between described chip, in order to simplify, simply show the structural representation of the silicon through hole in a chip in the drawings, certainly also comprise other requisite elements.
First, perform step 301, perform flatening process to the back side of Semiconductor substrate 200, described flatening process is grinding and/or polishing, to expose silicon through hole 201.
As shown in Figure 2 A, described silicon through hole 201 is formed in Semiconductor substrate 200, and described Semiconductor substrate 200 can at least one in following mentioned material: stacked SiGe (S-SiGeOI) and germanium on insulator SiClx (SiGeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.Other active areas or active device can be formed with in described substrate, not repeat them here.
Described silicon through hole 201 is embedded among described Semiconductor substrate 200, described silicon through hole 201 comprises the conductive layer 202 being positioned at center, and the barrier layer 203 be looped around outside conductive layer 202, wherein, the width of described conductive layer 202 can be 20-30 micron, described conductive layer 202 is formed by metal material, described metal material comprises Pt, Au, Cu, one or more in Ti and W, polysilicon can also be selected, do not limit to a certain, conducting function can be realized, be Ni metal in one embodiment of the invention, Ni metal is selected to reduce costs, and select metallic copper to form the technique of described silicon through hole and existing technique can be compatible well, process simplification.Described barrier layer 203 is that its thickness is 300-500 dust in order to improve the adhesiveness of filling metal in silicon through hole, comprises one or more in titanium nitride TiN and titanium Ti, is chosen as titanium nitride TiN and the titanium Ti of lamination in of the present invention one particularly execution mode.
Perform step 302, the bottom returning the described silicon through hole of etching to remove conductive layer 202 partly, to make the surface of the conductive layer after etching lower than the surface on Semiconductor substrate 200 and barrier layer 203.
As shown in Figure 2 B, the bottom that etches described silicon through hole is gone back to remove the conductive layer 202 of part.Return the object height that etching technics can meet conductive layer 202.Return etching technics and can adopt wet etching or dry etching, return the high etching selection ratio that etching technics has conductive layer.
In a specific embodiment of the present invention, the material of conductive layer 202 is metallic copper, adopts wet etching to perform back etching technics, as an example, adopts the liquid etchant containing sulfuric acid to carry out etching metallic copper conductive layer.
It should be noted that above-mentioned engraving method is only exemplary, do not limit to and the method, those skilled in the art can also select other conventional methods.
Perform step 303, the back side of Semiconductor substrate 200 and silicon through hole 201 are formed the passivation layer 204 with opening 205.
As shown in Figure 2 C, the passivation layer 204 with opening 205 is formed with on semiconductor substrate 200, wherein, described opening 205 is positioned on described conductive layer 202, in one example, described opening 205 is positioned at the middle part of described conductive layer 202, and the width of described opening can be 10-20 micron.
Exemplarily, the material of described passivation layer 204 comprises photo-sensistive polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO).
In the present invention one specific embodiment, the material of passivation layer 204 is photoactive material, formed after exposure, development and baking-curing and have the passivation layer 204 of opening 205, wherein, the light shield that exposure adopts is the light shield defining the width of opening 205, length and position.
Perform step 304, adopt WLP PROCESS FOR TREATMENT above-mentioned semiconductor device structure.
As shown in Figure 2 D, passivation layer 204 is formed wiring layer (RDL) 206, wherein, described wiring layer again 206 fills the passivation layer 204 of described opening 205 and cover part again.Wiring layer is used for carrying out layout again to the land positions of wafer again, makes new welding zone meet requirement to solder ball minimum spacing, and makes new welding zone according to array arrangement.
Exemplarily, the material of described wiring layer again 206 comprises metallic copper, and the thickness of described wiring layer again 206 can be 5-10 micron.Wiring layer 206 is responsible for the semiconductor circuit in Semiconductor substrate 200 being connected to the outside metal level connecting (such as, be connected to solder ball, and then arrive PC plate) again
In the present invention one specific embodiment, before formation copper again wiring layer, first sputtering forms one deck layers of copper or titanium layer on a semiconductor substrate, then, adopts electroplating technology in described layers of copper or titanium layer, form copper wiring layer again.
Then, wiring layer 206 again forms passivation layer 207, described passivation layer 207 is for the protection of wiring layer 206 again.Adopt photoetching process to etch described passivation layer 207, to form opening in passivation layer 207, and described opening exposes wiring layer 206 again, and described opening is welding zone.Be equivalent to, the back side of described Semiconductor substrate formed there is the second passivation layer 207 of opening, the top of wiring layer again described in described opening is positioned at.
Then, the opening of described second passivation layer 207 implants solder ball 208, and the material of described solder ball 208 comprises SAC, and the diameter of described solder ball 208 can be 259 microns.
Exemplarily, before implantation solder ball, first form ball lower metal layer (UBM), adopt the perforate of mask plate to be positioned over by solder ball on UBM layer, finally the silicon chip being formed with solder ball is pushed in reflow ovens and reflux.
The invention provides a kind of method preparing silicon through hole newly, after exposing silicon through hole, return etching metal copper layer in grinding and the polishing TSV device back side, spread to stop metallic copper and improve the reliability of device.According to manufacture method of the present invention, back side wafer level encapsulation (WLP) technique is adopted to improve the reliability of silicon through hole; Meanwhile, after execution grinding and polishing, do not return the step of etched silicon wafer thus reduce cost of manufacture.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (8)
1. make a method for semiconductor device, comprising:
There is provided Semiconductor substrate, the front of described Semiconductor substrate is formed with silicon through hole;
Adopt the back side of Semiconductor substrate described in flatening process process to expose the bottom of described silicon through hole, described silicon through hole comprises conductive layer and barrier layer;
Go back to the bottom of the described silicon through hole of etching to remove the described conductive layer of part;
The back side of described Semiconductor substrate is formed first passivation layer with the first opening, and wherein said first opening is positioned at the top of described conductive layer.
2. method according to claim 1, it is characterized in that, also be included in the step forming again wiring layer after forming described first passivation layer on described first passivation layer, wherein, described wiring layer again fills described first passivation layer of described first opening and cover part.
3. method according to claim 2, it is characterized in that, on the back side of described Semiconductor substrate, the step with the second passivation layer of the second opening is formed after being also included in described in formation again wiring layer, wherein, the top of wiring layer again described in described second opening is positioned at.
4. method according to claim 3, is characterized in that, is also included in the step implanting solder ball after forming described second passivation layer in described second opening.
5. method according to claim 1, is characterized in that, the width of described conductive layer is 20-30 micron.
6. method according to claim 1, is characterized in that, the width of described first opening is 10-20 micron.
7. method according to claim 2, is characterized in that, the thickness of described wiring layer is again 5-10 micron, and the material of described wiring layer is again metallic copper.
8. method according to claim 1, is characterized in that, described flatening process is grinding and/or polishing.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410183949.XA CN105097647B (en) | 2014-05-04 | 2014-05-04 | A method of making semiconductor devices |
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| CN201410183949.XA CN105097647B (en) | 2014-05-04 | 2014-05-04 | A method of making semiconductor devices |
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| CN105097647A true CN105097647A (en) | 2015-11-25 |
| CN105097647B CN105097647B (en) | 2018-12-21 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111755384A (en) * | 2020-06-18 | 2020-10-09 | 通富微电子股份有限公司 | Semiconductor device and method of manufacture |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080122116A1 (en) * | 2006-11-23 | 2008-05-29 | Samsung Electronics Co., Ltd. | Method of forming metal layer wiring structure on backside of wafer, metal layer wiring structure formed using the method, method of stacking chip package, and chip package stack structure formed using the method |
| CN102479771A (en) * | 2010-11-29 | 2012-05-30 | 三星电子株式会社 | Semiconductor device, fabricating method thereof and semiconductor package including the semiconductor device |
| US8390130B1 (en) * | 2011-01-06 | 2013-03-05 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
| CN103000649A (en) * | 2012-11-22 | 2013-03-27 | 北京工业大学 | Packaging structure and manufacture method for complementary metal-oxide-semiconductor transistor (CMOS) image sensors |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080122116A1 (en) * | 2006-11-23 | 2008-05-29 | Samsung Electronics Co., Ltd. | Method of forming metal layer wiring structure on backside of wafer, metal layer wiring structure formed using the method, method of stacking chip package, and chip package stack structure formed using the method |
| CN102479771A (en) * | 2010-11-29 | 2012-05-30 | 三星电子株式会社 | Semiconductor device, fabricating method thereof and semiconductor package including the semiconductor device |
| US8390130B1 (en) * | 2011-01-06 | 2013-03-05 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
| CN103000649A (en) * | 2012-11-22 | 2013-03-27 | 北京工业大学 | Packaging structure and manufacture method for complementary metal-oxide-semiconductor transistor (CMOS) image sensors |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111755384A (en) * | 2020-06-18 | 2020-10-09 | 通富微电子股份有限公司 | Semiconductor device and method of manufacture |
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