KR20150137970A - Semiconductor devices and methods of manufacture thereof - Google Patents

Abstract

The present invention relates to a semiconductor device and a manufacturing method thereof. According to some embodiments of the present invention, a semiconductor device includes a first hybrid bonded device including a first device and a second device hybrid bonded to the first device in a face-to-face manner. The first device includes a first substrate having first bonding connectors and a first bonding layer disposed on a surface of the first substrate. A second hybrid bonded device is bonded to the first hybrid bonded device in a back-to-back manner. The second hybrid bonded device includes a third device and a fourth device hybrid bonded to the third device in a face-to-face. The third device includes a second substrate having second bonding connectors and a second bonding layer disposed on a surface of the second substrate. The second bonding connectors of the third device are coupled to the first bonding connectors of the first device, and the second bonding layer of the third device is coupled to the first bonding layer of the first device.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor device,

[Cross reference of related literature]

This application claims the benefit of U.S. Provisional Patent Application No. 62 / 005,784, filed on May 30, 2014, entitled " Multi-Wafer Laminated Device and Method Forming Multi-Wafer Laminated Device " . The present application also claims priority to U.S. Patent Application No. 14 / 229,114, entitled " Bonding Structure for Laminated Semiconductor Devices, " filed March 28, 2014, the disclosure of which is incorporated herein by reference.

[TECHNICAL FIELD]

The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device.

BACKGROUND OF THE INVENTION The semiconductor industry is rapidly growing due to the continuous improvement of the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In recent years, such improvements in integration density have been attributed to the repetitive reduction of the minimum feature size (e.g., the reduction of semiconductor process nodes toward 20- or less nm nodes) that allows more components to be integrated in a given area do. As demand for miniaturization, higher speeds and larger bandwidths, as well as lower power consumption and rotational delay has increased in recent years, there is a growing need for smaller and more creative packaging technologies for semiconductor die.

As semiconductor technology advances, stacked semiconductor devices, such as 3D integrated circuits (3DICs), have emerged as an effective alternative to further reduce the physical size of semiconductor devices. In stacked semiconductor devices, active circuits such as logic, memory, processor circuits, and the like are fabricated on a variety of semiconductor wafers. Two or more semiconductor wafers may be stacked or stacked on top of one another to further reduce the form factor of the semiconductor device.

Two semiconductor wafers may be bonded together via a suitable bonding technique. Commonly used bonding techniques include direct bonding, chemically active bonding, plasma active bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermal compression bonding, reactive bonding, and the like. Electrical connections may be provided between the stacked semiconductor wafers. Laminated semiconductor devices provide higher densities in a smaller form factor, thereby improving performance and reducing power consumption.

It is an object of the present invention to provide an improved semiconductor device and a method of manufacturing a semiconductor device.

The above-mentioned object of the present invention is achieved by the invention disclosed in the claims.

According to the present invention, it is possible to provide a plurality of device stacking methods that are efficient, high throughput and low cost by reducing process time, and can provide more electric joints between devices.

1 to 8 are cross-sectional views illustrating a method of fabricating a semiconductor device at various stages in accordance with some embodiments of the present invention, wherein two wafers, dies, and / or chips are vertically bonded together.
Figures 9 and 10 are cross-sectional views illustrating semiconductor devices according to some embodiments of the present invention including vertically stacked and integrated devices.

BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the invention will be best understood from the following detailed description, taken in conjunction with the accompanying drawings, Depending on industry standard practice, the various drawings are not drawn to scale. Indeed, the dimensions of the various components may be arbitrarily increased or decreased for clarity of explanation.

The following detailed description provides various embodiments or examples for practicing the various elements of the invention. Specific examples of components and devices are provided below for simplicity of the present invention. Of course, such examples are not limited to examples. For example, in the following detailed description, the formation of the first component on or above the second component may be achieved by an embodiment in which the first component and the second component are formed in direct contact, or the first component and the second component May also include embodiments in which additional components are formed between the first component and the second component such that the second component is not directly contacted. Furthermore, the present invention may repeat the reference numerals and / or terms in various instances. Such repetition is merely for simplicity and clarity and does not itself represent the relationship between the various embodiments and / or configurations disclosed.

Also, spatially relative terms such as " below ", " lower ", "above "," upper ", and the like refer to the relationship of one element or element to another element (s) or element (s) May be used herein for the sake of brevity. Spatially relative terms are intended to encompass other orientations of the device during use or operation in addition to the orientations shown in the drawings. Spatial relative terms used herein may be interpreted similarly, since the device may be otherwise oriented (rotated 90 degrees or in other orientations).

Some embodiments of the invention disclosed herein relate to novel semiconductor devices and methods of manufacturing semiconductor devices. A structure and method are disclosed for face-to-face and back-to-back hybrid bonding techniques to achieve multi-wafer lamination. For example, some of the advantages of some embodiments include improved process time efficiency and improved performance of inter-wafer (or inter-die or inter-chip) electrical joints.

1 to 8 are cross-sectional views illustrating a method of fabricating a semiconductor device at various stages in accordance with some embodiments of the present invention, wherein two wafers, dies, and / or chips are vertically bonded together. The bonding is done at the wafer level, and after the first and second wafers are bonded together, they are singulated into individual dies or packages. Alternatively, the bonding may be performed at a die-to-die level or a die-to-wafer level.

Referring to Figure 1, a first device 102 and a second device 104 prior to the bonding process according to various embodiments are shown. The first device 102 includes wafers, dies, chips, etc., and in some embodiments includes a Tier 2 device. In some embodiments, the second device 104 includes a Tier 1 device. The second device 104 also includes wafers, dies, chips, and the like. The first device 102 and the second device 104 will be hybrid-bonded together according to some embodiments to form a first hybrid bonding device 130 (see FIG. 3). Subsequently, the first hybrid bonding device 130 will be bonded to the second hybrid bonding device 130 'in accordance with some embodiments as further described below (see FIG. 9 or 10).

1, the first device 102 includes a substrate 106, which may be a silicon wafer, a silicon on wafer (SOI) substrate, another type of semiconductor substrate, or other support substrate , Quartz, glass, etc., as known in the art), or a combination thereof. An interconnect structure 108 is formed on or over the substrate 106. The interconnect structure 108 is formed of a back-end-of-line (BEOL) and the substrate 106 may be, for example, a front-end-of-line ). ≪ / RTI > The interconnect structure 108 includes a plurality of conductive features disposed in a plurality of insulating materials. The interconnect structure 108 may include an inter-layer dielectric (ILD) and an inter-metallization (IMD) layer. For example, the insulating material can be formed using any suitable method known in the art such as spinning, chemical vapor deposition (CVD) and plasma enhanced CVD (PECVD), phosphosilicate glass (PSG), borophosphosilicate glass K dielectric material such as BPSG, FSG, SiO _x C _y , spin-on glass, spin-on polymer, silicon carbon material, compounds thereof, combinations thereof, combinations thereof, and the like.

The conductive features of the interconnect structure 108 interconnect and interconnect various of the passive and active elements (not shown) formed in and on the substrate 106 with one another. For example, the interconnect structure 108 may include two or more conductive traces vertically interconnected by a bias (not shown) embedded in a dielectric layer formed using a damascene process or a subtractive etch technique. . ≪ / RTI > Although two conductive trace layers are shown in interconnect structure 108 in FIG. 1, one, two, or three layers may be included in interconnect structure 108 of first device 102. Regardless of the number of layers in the interconnect structure 108, the first device 102 includes an upper interconnect layer 110. The top interconnect layer 110 comprises a conductive feature, such as a conductive line or plug, comprising a conductive material such as copper, copper alloy or other metal.

As used herein, the term " top "refers to a layer or other structure at the farthest end of a substrate relative to another layer or structure, and the endmost layer or structure is located at the bottom of the structure when the device is inverted at any instant . The interconnect structure 108 may also include an upper passivation layer or an upper dielectric layer 111 on which the upper interconnect layer 110 is buried. In some embodiments, a portion of the upper passivation layer or upper dielectric layer 111 is formed on top of the upper interconnect layer 110, as shown in FIG. For example, the top interconnect layer 110 includes the top interconnect layer of the interconnect structure 108.

In addition, the second device 104 has a substrate 112 on which an interconnect structure 114 is formed. The interconnect structure 114 has an upper or top interconnect layer 116 and an upper passivation or top dielectric layer 117. The second device 104 may be, but need not be, the same type of device as the first device 102, and may be manufactured using the same process and may include a structure and material similar to the first device 102 You may. Alternatively, the second device 104 may include a different type of device than the first device 102, and the second device 104 may be fabricated using other processes, structures, and materials. In the illustrated embodiment, the second device 104 has only one interconnect layer disposed in the interconnect structure 114. Thus, the top interconnect layer 116 is the only layer shown of the interconnect structure 114. However, the interconnect structure 114 may alternatively include two or more conductive features, and the upper interconnect layer 116 may include, in some embodiments, the uppermost conductive material layer of the interconnect structure 114 You may.

The first device 102 has a first side 118a and a second side 118b opposite the first side 118a. For example, the first side 118a includes the front side or the opposite side of the first device 102, and the second side 118b includes the back side of the first device 102. [ Similarly, the second device 104 has a first side 119a and a second side 119b opposite the first side 119a. For example, the first side 119a includes the front side or the opposite side of the second device 104, and the second side 119b includes the back side of the second device 104. [

2, a plurality of bonding connectors 120 and 122 are formed in the first device 102 and the second device 104, respectively. The bonding connector 120 is coupled to a portion of the upper interconnect layer 110, 116 of the first device 102 and the second device 104, respectively. The bonding connectors 120 and 122 are coupled to the conductive features of the upper interconnect layers 110 and 116, respectively. The bonding connectors 120 and 122 may be formed by patterning the upper insulating material layers 111 and 117 of the interconnect structure 108 and 114, respectively, and filling the pattern with a conductive material. For example, in some embodiments, the pattern of upper insulating material layers 111, 117 includes a first hybrid bond pad pattern.

The bonding connectors 120 and 122 may be formed by patterning the upper insulating material layers 111 and 117 of the interconnection structures 108 and 114 using a lithographic or direct patterning method and patterning the upper insulating material layers 111 and 117 using copper, aluminum, tungsten, Or by forming a plurality of layers of these over a patterned insulating material layer, using a damascene technique. Subsequently, the excess conductive material is removed from the top surface of the insulating material layers 111, 117 using, for example, a chemical mechanical polishing (CMP) process, a grinding process and / or an etching process. In some embodiments, the bonding connectors 120 and 122 include hybrid bond pad (HBP) connectors that are used to bond the first device 102 and the second device 104 together, for example, in a hybrid bonding process. The remaining portions of the uppermost insulating material layers 111 and 117 also function as bonding layers of the first device 102 and the second device 104 in the hybrid bonding process.

Patterning the upper passivation layer or dielectric layers 111 and 117 of the first device 102 and the second device 104 may be performed by patterning the first device 102 and the upper portion of the second device 104, An opening is formed in the passivation layer or the upper dielectric layer (111, 117). Formation of a conductive material over the patterned upper dielectric layer (111, 117) charges the opening with a conductive material. After the excess conductive material is removed from the upper surface of the upper passivation layer or upper dielectric layer 111, 117, the conductor fill opening forms a bonding connector 120, 122 that is aligned and bonded together as described below. The bonding connectors 120 and 122 are electrically connected at the first end to the traces of the upper interconnect layer 110 and 112 and at the second end are substantially coplanar with the respective upper passivation or upper dielectric layers 111 and 117 exist. In some embodiments, the bonding connectors 120, 122 have a width of, for example, from about 0.2 microns to about 3 microns and a height of from about 0.3 microns to about 0.9 microns. Alternatively, the bonding connectors 120, 122 may include other dimensions. The actual dimensions are determined by the process technology node employed, the number of bonding connectors needed, whether the power or signal is transmitted through a particular bonding connector, and other factors that are apparent to the manufacturer.

Also, the bonding connectors 120 and 122 may be formed using a subtractive etching process. For example, the insulating material layer of the interconnect structure 108, 114 may be present in substantially the same plane as the upper interconnect layer 110, 116 with the conductive feature. Conductive materials may be formed over the interconnect structures 108 and 114 and may be patterned using a lithographic process to form the bonding connectors 120 and 122. Subsequently, the first and second devices 102 and 117, which include the upper dielectric layers 111 and 117 and the bonding connectors 120 and 122, respectively, are patterned to form a bonding plane on the insulating material layers 111, 117 may be formed around the patterned conductive material.

Since the bonding connectors 120 and 122 of the first device 102 and the second device 104 include substantially the same pattern in some of the first and second devices 102 and 104, May be bonded together using bonding connectors 120 and 122 to form an electrical connector between the device 102 and the second device 104. For example, the pattern for the bonding connector 120, 122 is aligned in some embodiments.

Figure 3 illustrates the first device 102 and the second device 104 after the hybrid bonding process to form the hybrid bonding device 130 has been performed according to some embodiments. The first device 102 shown as being disposed underneath the second device 104 in Figures 1 and 2 is shown as being located on top of the second device 104 because the first device 102 Is inverted and face-to-face bonded to the second device 104. FIG. 3 illustrates a first device 102 and a second device 104 that are bonded together in a face-to-face configuration using, for example, hybrid bonding. The first side 118a of the first device 102 is bonded to the first side 119a of the second device 104 in a face-to-face configuration.

Bonding of the first device 102 to the second device 104 is accomplished through a joint bonding mechanism which bonds the respective upper passivation layer or upper dielectric layer 111 and 117 together, And aligning and bonding the bonded connector 120 of the aligned first device 102 and the bonded connector 122 of the second device 104 together. For example, in embodiments where both the top passivation or top dielectric layers 111, 117 are both oxide materials, oxide-oxide bonds are formed between the top passivation or top dielectric layers 111, 117. In an embodiment in which both the bonding connectors 120 and 122 are formed of copper, the copper of the bonding connectors 120 and 122 forms a copper-copper bond.

The first device 102 and the second device 104 are connected to a plurality of bonding connectors 108 and 114 disposed in the uppermost interconnection layer of the interconnection structures 108 and 114 of the first device 102 and the second device 104, As shown in FIG. Bonding connectors 120 and 122 may be disposed between the first device 102 and the second device 104 and between the conductive features of the upper interconnect layers 110 and 116 of each interconnect structure 108 and 114, Lt; RTI ID = 0.0 > electrical < / RTI >

After the hybrid bonding process shown in Figure 3, a portion of the substrate 106 of the first device 102 is removed, as shown in Figure 4, Showing a thinning down step. In some embodiments, the substrate 106 may be thinned, for example, to a thickness of about 5 [mu] m to about 50 [mu] m. In another embodiment, the substrate 106 may be thinned to a different thickness.

Next, the opening 124 is etched through the substrate 106 of the first device 102 as shown in FIG. Although three openings 124 are shown, those skilled in the art will appreciate that a number of such openings 124 may be formed in the substrate 106 in some applications. (As shown in FIG. 8A) to the second side 118b (including the rear side) of the first device 102 so that a second hybrid bonding step can be performed on the other device, Openings 124 are formed to form the openings 124 (see FIG. The opening 124 may have a circular, oval, square, rectangular or other shape as viewed from above. For example, the openings 124 may have dimensions similar to those described for the bonding connectors 120, 122.

The openings 124 may be formed using a lithographic process, such as by forming a photoresist layer (not shown) over the substrate 106 and patterning the photoresist layer. Exposing the photoresist layer to light or energy reflected from a lithographic mask having a target pattern thereon or over a lithographic mask, developing the photoresist layer, and developing the photoresist layer using ashing and / The photoresist layer may be patterned by removing exposed or unexposed portions of the photoresist layer (depending on whether the photoresist layer is positive or negative). Subsequently, the patterned photoresist layer is used as an etch mask while a portion of the substrate 106 is removed using an etch process, so that openings 124 are formed. Subsequently, the photoresist layer is removed. Alternatively, the substrate 106 may be patterned using a direct patterning process.

Subsequently, an isolation layer 126 is formed on the patterned substrate 106 of the first device 102, as shown in FIG. An isolation layer 126 comprising a dielectric material such as silicon oxide, silicon nitride, or the like is deposited or deposited on the backside of the substrate 106. The isolation layer 126 is extended and lined with openings 124 in the substrate 106 of the first device 102. For example, the isolation layer 126 electrically isolates the conductive material to be formed in the opening 124 from the surrounding semiconductor material of the substrate 106. For example, the isolation layer 126 may be formed using chemical vapor deposition (CVD) or other methods, and may have a thickness of several micrometers. Alternatively, isolation layer 126 may include other materials, formation methods, and dimensions. In some embodiments, the isolation layer 126 is used as a bonding layer to form an oxide-oxide hybrid bond for another hybrid bonding device 130 '(see FIGS. 9 and 10).

7, openings 127 are subsequently formed in the insulating material of interconnection structure 108 of isolation layer 126 and first device 102 using a lithographic or direct patterning method. A portion of the conductive features of the interconnect structure 108 may be exposed through the openings 127 to form electrical contacts in the conductive features. The openings 127 are disposed below the openings 124 of the substrate 106, respectively.

In some embodiments, forming the openings 124,127 may be accomplished through the metal interconnect layer of the interconnect structure 106 of the first device 102 to the backside 118b of the substrate 106 of the first device 102 Lt; RTI ID = 0.0 > trenches < / RTI > The openings 124 and 127 form a second pattern for the hybrid bond pads on the second side 118b of the first device 102.

Subsequently, a conductive material is filled into the openings 124, 127 over the isolation layer 126 to form the bonding connector 128, as shown in FIG. The conductive material may comprise copper, a copper alloy, another metal, or a plurality of layers or combinations thereof. In an embodiment where the opening includes a trench, a conductive material fills the trench to form a bonding connector 128 on the backside of the first device 102. As deposited, the conductive material may be on the upper surface of isolation layer 126, as indicated by reference numeral 128 '. The excess conductive material is removed using a CMP process, an etching process, a grinding process, or a combination thereof, leaving a conductive material in the opening 124 to form the bonding connector 128. The bonding connector 128 includes a backside bonding connector 128 of the first device 102.

Unlike the bonding connectors 120 and 122 formed on the first side (e.g., the first side 118a and 119a) of the first device 102 and the second device 104, Is formed on the back side of the first device 102, i.e., on the back side of the substrate 106 of the first device 102. The backside bonding connector 128 includes a wafer bonded to a top or top portion of a hybrid bonding device 130 that includes a first device 102 that is a tier 2 device 102 and a second device 104 that is a tier 1 device, Or stacking the chips, thereby enabling another vertical integration.

For example, FIGS. 9 and 10 are cross-sectional views of a semiconductor device 100, 100 'including a plurality of devices 104, 102, 134, 132, 132' vertically stacked together for additional vertical integration. An embodiment in which two hybrid bonding devices 130 and 130 'are vertically stacked and integrated together is shown in FIG. The first hybrid bonding device 130 includes a stacked tier 1 second device 104 and a tier 2 first device 102 as shown in Figure 8 and the first device 102 includes a face- And hybrid-bonded to the second device 104. For example, the first side 118a of the first device 102 is hybrid-bonded to the first side 119a of the second device 104. [ The bonding connectors 122 and 120 are bonded together and the isolation material layers 111 and 117 are bonded together using a hybrid bond.

The second laminating device 130'includes a tier 3 third device 134 and a tier 4 fourth device 132 and the tier 3 third device 134 and the tier 4 fourth device 132 comprise the tier 3 third device 134 and the tier 4 fourth device 132, To-face configuration in a manner similar to that shown and described for the first device 102 and the second device 104 in Figs. The first side 119a 'of the third device 134 is hybrid-bonded to the first side 118a' of the fourth device 132. [ The bonding connectors 120 'and 122' are bonded together and the isolation material layers 111 'and 117' are bonded together using a hybrid bond.

Also as shown in FIG. 9, the hybrid bonding devices 130 and 130 'include a lamination device that is hybrid-bonded together in a back-to-back configuration. The second side 119b 'of the third device 134 is hybrid-bonded to the second side 118b of the first device 102. Each of the bonding connectors 128 and 128'of the first device 102 and the third device 134 are bonded together and bonded to the substrates 106 and 106'of the first device 102 and the third device 134, The insulating material layers 126 and 126 'disposed on top of each other are bonded together using a hybrid bond.

In some embodiments, the contact pad 144 ', which includes aluminum or other material, is proximate to the surface of the substrate 106 of the upper fourth device 132, as shown illogically (e.g., with a dashed line) in FIG. To a hybrid bond pad or bonding connector 128 that is disposed over the substrate. Also as shown, the connector 146 'may be coupled to a respective contact pad 144'. Connector 146 'includes an external connector such as a solder ball, solder bump, conductive pillar, or other material. In some embodiments, the connector 146 'may include a eutectic material configured to reflow when heated to a predetermined temperature. The connector 146 'may be used to couple the semiconductor device 100 to another object such as a printed circuit board (PCB) or other end application.

In some embodiments, the four devices 104, 102, 134, 132 are bonded together using an alternating face-to-face hybrid bond and a back-to-back hybrid bond. In another embodiment, more than four devices 104, 102, 134, 132, 132 ' are bonded together. For example, a fifth device 132 'comprising a tier N device that can be bonded to a fourth device 132 using a back-to-back hybrid bond is shown in FIG. The bonding devices 128 and 128 'of the fourth device 132 and the fifth device 132' are bonded together and the insulating material 126 and 126 'respectively disposed on the substrates 106 and 106' Are bonded together. For example, the insulating material 126, 126 'includes a bonding layer for a hybrid bonding process.

The fact that the first hybrid bonding device 130 is hybrid-bonded to the second hybrid bonding device 130 'in a back-to-back configuration means that the rear surface 118b of the device 102 of the first hybrid bonding device 130 is bonded to the second hybrid bonding device 130' 2 hybrid bonding device 130 'to the backside 119b' of the device 134 of the hybrid bonding device 130 '. This back-to-back bonding is advantageous because the insulating material 126 disposed on the substrate 106 of the backside 118b of the device 102 is insulated from the substrate 106 'of the backside 119b' (E.g., oxide-oxide bonded) to the material 126 'and the backside bonding connector 128 of the backside 118b of the device 102 contacts the backside bonding connector (not shown) of the backside 119b' 128 ') (e.g., copper-copper bonded). Thus, the fully stacked semiconductor device 100 includes a first stacked device 130 having two devices 102, 104 that are hybrid bonded in a face-to-face configuration, and two devices (not shown) that are hybrid- 132, 134, and the two stacking devices 130, 130 'are hybrid-bonded in a back-to-back configuration.

Each of the devices 104, 102, 134, 132 and 132 'is hybrid-bonded to one another such as face to face, back to back, face to face, This pattern may be included to have a set of devices 130, 130 ', two sets of devices 130, 130', or more. For example, the number of vertically stackable devices 104, 102, 134, 132, 132 'is a matter of design choice.

In some embodiments, after the first to fourth devices 104, 102, 134, 132 are hybrid-bonded together, a plurality of additional lamination devices, such as the fifth device 132 ', may be formed or provided. The method of forming the semiconductor device 100 further includes continuously hybrid-bonding each of the plurality of additional lamination devices 132 'to the upper device of the semiconductor device 100, wherein a plurality of additional lamination devices 132' ) Is hybrid-bonded to the fourth device 132, for example.

After two or more devices 104, 102, 134, 132, 132 'are hybrid-bonded together, they can be hybrid-bonded to one or more devices. Alternatively, the devices 104, 102, 134, 132, 132 ' may be sequentially hybrid-bonded to the upper device one at a time.

The stacked devices 104, 102, 134, 132, 132 'are hybrid bonded using an oxide-oxide bond and a copper-copper bond. For example, for the semiconductor device 100 shown in FIG. 9, the hybrid bonding method of some embodiments includes oxide-oxide bonding of the front passivation layers 111 and 117 of the first device 102 and the second device 104, The oxide-oxide bonding of the front passivation layers 111 ', 117' of the third device 134 and the fourth device 132 and the oxide-oxide bonding of the first device 102 and the rear passivation layer 126 of the third device 134 , 126 '). ≪ / RTI > Also, in some embodiments, the hybrid bonding method may include copper-copper bonding of the front bonding connectors 120, 122 of the first device 102 and the second device 104, copper-copper bonding of the third device 134 and the fourth device 132 Copper bonding of the front bonding connectors 120 ', 122' of the first device 102 and copper-copper bonding of the backside bonding connectors 128, 128 'of the first device 102 and the third device 134 .

FIG. 9 shows a configuration having an odd number of stacked devices 104, 102, 134, 132, 132 '. The upper device 132 'is identical to the tier 1 first device 104 in terms of the bonding pattern of the bonding connector 128'. The top or fifth device 132 'is back-to-back bonded to the underlying fourth device 132 and has an exposed front surface 119a'. External electrical connections such as contact pads 144 and external connectors 146 may be included and employed such that they are electrically connected to the upper device 132 'and electrically connected to the remaining lamination devices 132,134, 102,104. In an embodiment in which an odd number of laminating devices 104, 102, 134, 132 and 132 'are included in the semiconductor device 100, the contact pads 144 may be formed on the uppermost interconnection layer Lt; / RTI >

Figure 10 shows a configuration with an even number of stacked devices 104, 102, 134, 132, 132 ', 132 ". Reference numerals are not shown again for all components, and therefore, reference is made to Fig. The top device 132 " includes a tier N device and includes a side surface (e.g., a side surface) of the bonding pattern of the bonding connector 128 ', 128 " (similar to the bonding connector 120, 128 of the first device 102) Is the same as the tier 2 first device 102. The upper device 132 " is face-to-face bonded to the underlying device 132 'including the tier (N-1) device. The rear bonding connector 128 'located at the rear surface 118b " of the upper tier N device 132 " is exposed. Rather than being used for hybrid bonding to adjacent devices of the vertical stack, the back bonding connector 128 'of the upper device 132 " 128 ' and the external connector 146 coupled to the contact pad. Thus, in the embodiment in which the semiconductor device 100 'includes an even number of the laminating devices 104, 102, 134, 132, 132', 132 ", the contact pad 144 May be coupled to a bonding connector 128 'disposed within the substrate of the fifth device 132' '.

In some embodiments, top device 132, 132 'or 132 " includes a backside light intensity sensor (BIS) device and at least one of the other devices 104,102, And the like. The BIS device may include a photoactive region, such as a photodiode formed by implanting impurity ions into the epitaxial layer. The photoactive area may include a PN junction photodiode, a PNP photoresistor, an NPN phototransistor, and the like. The BIS device may comprise a sensor formed in an epitaxial layer on a silicon substrate. In other embodiments, the devices 104, 102, 132, 134, 132 ', 132 " may include logic circuits, analog-to-digital converters, data processing circuits, memory circuits, bias circuits,

Various elements such as a device, a bonding connector and the like are described herein as "first "," second ", "third"

Embodiments of the present invention include a semiconductor device including a stack of vertically stacked wafers, dies, or chips. Further, embodiments of the present invention include a method of manufacturing a semiconductor device.

An advantage of some embodiments of the present invention includes providing a novel method of laminating semiconductor devices in which through vias are not required for a vertical stack. In addition, a hybrid bond pad connector is formed in the interconnection structure of the device and the substrate in a via-via type, and is used to electrically connect the devices. Thus, a plurality of device stacking methods with reduced process time, effective, more throughput and low cost are achieved. More electrical joints between the devices can be achieved. Face-to-face and back-to-back hybrid bonding is used to realize multi-wafer and multi-device lamination. In addition, the structures and methods disclosed herein are readily implemented in the manufacturing process flow.

According to some embodiments, a semiconductor device of the present invention includes a first device including a plurality of first bonding connectors disposed on a surface of a first substrate and a first substrate having a first bonding layer, And a first hybrid bonding device including a second device that is face-hybrid-bonded. Further, the semiconductor device of the present invention includes a second hybrid bonding device that is back-to-back bonded to the first hybrid bonding device, and the second hybrid bonding device includes a third device and a fourth device that is face- Device. The third device includes a plurality of second bonding connectors disposed on a surface of the second substrate and a second substrate having a second bonding layer. The plurality of second bonding connectors of the third device are coupled to the plurality of first bonding connectors of the first device. The second bonding layer of the third device is bonded to the first bonding layer of the first device.

According to another embodiment, a semiconductor device of the present invention includes a first device including a first front bonding connector and a first front bonding layer, a second bonding device disposed vertically on the first device and configured to perform hybrid bonding in a face- Lt; / RTI > The second device includes a second front bonding connector bonded to the first front bonding connector and a second front bonding layer bonded to the first front bonding layer. The second device further includes a first rear bonding connector formed on the substrate of the second device and a first rear bonding layer formed on the rear surface of the substrate of the second device. The semiconductor device of the present invention also includes a third device stacked vertically on the second device and hybrid-bonded to the second device in a back-to-back configuration. The third device includes a second backside connector formed on a substrate of a third device bonded to the first backside bonding connector and a second backside bonding layer bonded to the first backside bonding layer. The third device also includes a third front bonding connector and a third front bonding layer. The semiconductor device of the present invention further includes a fourth device stacked vertically on the third device and hybrid-bonded to the third device in a face-to-face configuration. The fourth device includes a fourth front bonding connector bonded to the third front bonding connector and a fourth front bonding layer bonded to the third front bonding layer.

According to some embodiments, a method of manufacturing a semiconductor device of the present invention includes forming a first laminating device and a second laminating device. Forming a front bonding connector and a front passivation layer on the front side of the first device and the second device, bonding the front passivation layers of the first device and the second device together and bonding the front passivation layers of the first device and the second device Bonding the first device and the second device by bonding the front-side bonding connectors of the first and second devices together. A backside bonding connector and a back passivation layer are formed on the backside of the first device. Forming a front bonding connector and a front passivation layer on the front side of the third device and the fourth device, bonding the front passivation layers of the third device and the fourth device together and bonding the front passivation layers of the third device and the fourth device Bonding the third and fourth devices by bonding the front-side bonding connectors of the first and second devices together. A backside bonding connector and a back passivation layer are formed on the backside of the third device. The method of manufacturing a semiconductor device of the present invention also includes bonding the backside passivation layers of the first device and the third device together and bonding the backside bonding connectors of the first device and the third device together, And hybrid bonding the device.

In order that those skilled in the art will be better able to understand aspects of the present invention, the above described components for some embodiments are disclosed. Those skilled in the art will readily utilize the teachings herein as a basis for designing or modifying other processes and structures to achieve the same objects and / or advantages of the various embodiments disclosed herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present invention and that various modifications, substitutions and alterations can be made within the spirit and scope of the present invention.

102: first device
104: second device
106, 112: substrate
108, 114: interconnect structure
110: upper interconnect layer
116: top interconnect layer
117: upper passivation layer or upper dielectric layer
124, 127: aperture
126: Isolation layer
128: Bonding connector

Claims (10)

1. A semiconductor device comprising:
A first device including a plurality of first bonding connectors disposed on a surface of a first substrate and a first substrate having a first bonding layer and a second substrate bonded to the first device by a face- A first hybrid bonding device comprising a second device, and
And a second substrate having a second bonding layer and a second bonding layer that is back-to-back bonded to the first hybrid bonding device and is disposed on a surface of the second substrate, And a second hybrid bonding device including a fourth device that is face to face hybrid bonded to the third device,
A plurality of second bonding connectors of the third device are coupled to a plurality of first bonding connectors of the first device,
And the second bonding layer of the third device is coupled to the first bonding layer of the first device.
Semiconductor device. The method according to claim 1, wherein the first device and the second device are hybrid-bonded by a plurality of third bonding connectors, the third device and the fourth device are hybrid-bonded by a plurality of fourth bonding connectors, And a third bonding connector is disposed in the uppermost interconnection layer of the first device and the second device and the fourth bonding connector is disposed in the uppermost interconnection layer of the third device and the fourth device. 2. The semiconductor device of claim 1, wherein the fourth device comprises a third substrate comprising a plurality of third bonding connectors disposed proximate the surface of the third substrate. The semiconductor device of claim 1, wherein the plurality of first bonding connectors and the plurality of second bonding connectors include a hybrid bond pad (HBP) connector. 1. A semiconductor device comprising:
A first device including a first front bonding connector and a first front bonding layer;
A second front bonding connector vertically stacked on the first device and hybrid-bonded to the first device in a face-to-face configuration, the second front bonding connector being bonded to the first front bonding connector, A second device including a second front bonding layer, a first rear bonding connector formed on a substrate of the second device, and a first rear bonding layer formed on a rear surface of the substrate,
A third device stacked vertically on the second device and hybrid-bonded to the second device in a back-to-back configuration, the second device being formed on a substrate of the third device bonded to the first backside bonding connector, A third device including a second rear bonding layer bonded to the first rear bonding layer, a third front bonding connector, and a third front bonding layer;
A fourth device stacked vertically on the third device and hybrid-bonded to the third device in a face-to-face configuration, the fourth device comprising: a fourth front bonding connector bonded to the third front bonding connector; And a fourth device including a fourth front bonding layer bonded thereto
Semiconductor device. 6. The semiconductor device of claim 5, wherein the fourth device comprises a third backside connector formed on a substrate of the fourth device, and a third backside bonding layer. 6. The apparatus of claim 5, further comprising: a fourth device hybrid-bonded to the fourth device in a face-to-face configuration and including a contact pad;
And a connector electrically connected to the contact pad. 6. The method of claim 5, wherein the second device is hybrid-bonded to the first device and the third device is hybrid-bonded to the second device, wherein the fourth device is both oxide-oxide bond and copper- Wherein the second device is hybrid-bonded to the third device using the second device. A method of manufacturing a semiconductor device,
Forming a front bonding connector and a front passivation layer on the front side of the first device and the second device; bonding the front passivation layers of the first device and the second device together and bonding the front passivation layer of the first device and the second device, Hybrid bonding the first device and the second device by bonding the connectors together; forming a first laminating device using the step of forming a rear bonding connector and a rear passivation layer on a rear surface of the first device; ,
Forming a front bonding connector and a front passivation layer on the front side of the third device and the fourth device; bonding the front passivation layers of the third device and the fourth device together and bonding the front passivation layers of the third device and the fourth device, Hybrid bonding the third device and the fourth device by bonding the connectors together; forming a second laminating device using the backside bonding connector and the back passivation layer on the backside of the third device; ,
And hybrid bonding the first and second laminating devices by bonding the backside passivation layers of the first and third devices together and bonding the backside bonding connectors of the first device and the third device together
A method of manufacturing a semiconductor device. 10. The method of claim 9, wherein forming the backside bonding connector of the first device or forming the backside bonding connector of the third device comprises:
Etching a trench on the back surface of the substrate of the first device or the third device through the metal interconnect layer of the first device or the third device,
And filling the trench with a conductive material to form a backside bonding connector for the first device or the third device.

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