CN111029321A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN111029321A CN111029321A CN201911145477.8A CN201911145477A CN111029321A CN 111029321 A CN111029321 A CN 111029321A CN 201911145477 A CN201911145477 A CN 201911145477A CN 111029321 A CN111029321 A CN 111029321A
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- substrate
- semiconductor device
- pad
- manufacturing
- straight hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
The invention provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises: the circuit board comprises a first substrate, a second substrate arranged on the first substrate, a bonding pad arranged on the second substrate, and a metal circuit layer connected to the bonding pad; the first substrate is provided with a stepped hole communicated to the pad, an insulating layer is arranged between the metal circuit layer and the pad, and the insulating layer is arranged at the corner position of the bottom in the stepped hole. The semiconductor device of the invention forms the stepped hole communicated with the bonding pad by the way of opening the two parts, and the stepped hole is beneficial to forming a thicker insulating layer at the corner position of the bottom in the stepped hole, thereby having obvious advantages of reducing the pressure of the bonding pad and reducing the wire breaking risk of the metal circuit layer and relieving the pulling stress of the metal circuit layer on the bonding pad.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for manufacturing the same.
Background
At present, in the conventional straight hole process for a semiconductor device, the problem of overlarge stress on a welding pad exists. In addition, due to the structural characteristics of the product itself, the problem of disconnection of the metal wiring layer connected to the pad is also easily caused. Therefore, it is necessary to provide a further solution to the above problems.
Disclosure of Invention
The present invention is directed to a semiconductor device and a method for manufacturing the same, which overcome the shortcomings of the prior art.
In order to solve the technical problems, the technical scheme of the invention is as follows:
a semiconductor device, comprising:
a first substrate,
A second substrate disposed on the first substrate,
A pad disposed on the second substrate,
A metal wiring layer connected to the pad;
the first substrate is provided with a stepped hole communicated to the pad, an insulating layer is arranged between the metal circuit layer and the pad, and the insulating layer is arranged at the corner position of the bottom in the stepped hole.
As an improvement of the semiconductor device of the present invention, the first substrate is a silicon wafer, and the second substrate is a glass plate.
As a modification of the semiconductor device of the present invention, the first substrate and the second substrate are connected by an adhesive.
As an improvement of the semiconductor device of the invention, the insulating layer is SiO formed by deposition2Layer or Si3N4And (3) a layer.
In order to solve the technical problems, the technical scheme of the invention is as follows:
a method of manufacturing a semiconductor device, comprising:
manufacturing a first straight hole corresponding to part of the pad on the first substrate, wherein the bottom of the first straight hole is spaced from the pad opposite to the first straight hole;
continuously manufacturing a second straight hole communicated to the bonding pad at the bottom of the manufactured first straight hole;
depositing an insulating layer on the first substrate, removing the insulating layer deposited on the middle area of the bonding pad, and reserving the deposited layer at the corner position of the hole bottom of the second straight hole;
and manufacturing a metal circuit layer connected to the bonding pad.
As an improvement of the method for manufacturing a semiconductor device of the present invention, the first substrate is a silicon wafer, and the second substrate is a glass plate.
As an improvement of the manufacturing method of the semiconductor device of the present invention, the first substrate and the second substrate are connected by an adhesive.
As an improvement of the manufacturing method of the semiconductor device of the present invention, the insulating layer is SiO2Layer or Si3N4And (3) a layer.
As an improvement of the manufacturing method of the semiconductor device, the first straight hole and the second straight hole are made by etching, and the insulating layer deposited on the middle area of the bonding pad is removed.
As an improvement of the method for manufacturing a semiconductor device of the present invention, the method for manufacturing a semiconductor device further includes: and passivating and filling the first straight hole and the second straight hole, reserving a welding area, and arranging a welding ball in the reserved welding area.
Compared with the prior art, the invention has the beneficial effects that: the semiconductor device of the invention forms the stepped hole communicated with the bonding pad by the way of opening the two parts, and the stepped hole is beneficial to forming a thicker insulating layer at the corner position of the bottom in the stepped hole, thereby having obvious advantages of reducing the pressure of the bonding pad and reducing the wire breaking risk of the metal circuit layer and relieving the pulling stress of the metal circuit layer on the bonding pad.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention;
fig. 2-9 are process flow diagrams illustrating a method of fabricating a semiconductor device according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, a semiconductor device according to an embodiment of the present invention includes: a first substrate 1, a second substrate 2, a pad 3, an insulating layer 4, and a metal wiring layer 5.
Wherein the second substrate 2 is bonded and fixed to one surface of the first substrate 1. In one embodiment, the first substrate 1 is a silicon wafer and the second substrate 2 is a glass wafer. In order to achieve bonding between the two substrates, the first substrate 1 and the second substrate 2 are connected by means of glue. The pads 3 are located between the first substrate 1 and the second substrate 2, and a plurality of the pads 3 may be provided as required.
The first substrate 1 is provided with a stepped hole 11 communicated to the pad 3, and the stepped hole 11 is provided to obtain a straight hole with a smaller hole depth-diameter ratio, that is, the straight hole directly communicated with the pad 3 is a straight hole with a smaller depth and a larger hole diameter. The straight hole having this structural feature advantageously provides a larger space for forming the insulating layer 4 with a greater thickness with respect to the exposed pad 3 area. In one embodiment, the insulating layer 4 is SiO deposited2Layer or Si3N4And (3) a layer.
If the stepped hole 11 is not formed, a straight hole having a suitable hole depth-to-diameter ratio cannot be obtained. Since the depth of the straight hole is constant for communicating with the pad 3, only the diameter of a single straight hole can be adjusted, and the adjustment of the hole depth diameter requires adjustment of both the hole depth and the hole diameter. In this case, in order to pursue a larger space, only deep and wide straight holes can be formed, which is disadvantageous both for the subsequent filling of the passivation substance and for the arrangement of the solder balls, since deep and wide straight holes need to be filled with more passivation substance and no sufficient space is reserved for the arrangement of the solder balls.
And the form of shoulder hole 11, set up a great straight hole of aperture at first, its reference surface that will set up the straight hole is closer to pad 3, has realized the regulation of hole depth, further sets up another straight hole again and communicates to pad 3, has realized the regulation of aperture, and then the accessible adjusts the hole depth ratio of this another straight hole, forms the hole structure that the pad 3 region of relative opening has bigger space.
Above-mentioned insulating layer 4 sets up the corner position of bottom in shoulder hole 11, and because shoulder hole 11's design, the thickness of this insulating layer 4 can realize thickly, and then to reducing pad 3 pressure, reduces 5 broken string risks on metal line layer and has obvious advantage, can alleviate the stress of dragging of metal line layer 5 to pad 3. Further, the metal wiring layer 5 is connected to the region of the opened pad 3.
In addition, the stepped hole 11 is filled with a passivation substance 6, a welding area is reserved on the passivation substance 6, and a solder ball 7 is arranged on the reserved welding area.
Based on the same inventive concept, in order to manufacture the semiconductor device, another embodiment of the present invention also provides a method of manufacturing a semiconductor device.
The method for manufacturing the semiconductor device comprises the following steps:
as shown in fig. 2, the first substrate is fixed to the second substrate. In one embodiment, the first substrate is a silicon wafer, the second substrate is a glass wafer, and the first substrate and the second substrate are connected through an adhesive.
As shown in fig. 3, a first straight hole corresponding to a pad portion is formed in the first substrate, and a gap is reserved between the bottom of the first straight hole and the pad opposite to the first straight hole. Therefore, the reference surface for manufacturing the second straight hole is closer to the bonding pad, and the adjustment of the hole depth is realized. In one embodiment, the first straight hole is made by etching.
As shown in fig. 4, a second straight hole connected to the bonding pad is continuously formed at the bottom of the first straight hole. Therefore, a stepped hole structure communicated with the middle area of the bonding pad is formed, the adjustment of the hole diameter is realized, and in one embodiment, the second straight hole is manufactured in an etching mode.
As shown in fig. 5, an insulating layer is deposited on the first substrate and the insulating layer deposited on the middle area of the pad is removed, while the deposited layer at the corner position of the bottom of the hole of the second straight hole remains. In this way, an insulating layer having a large thickness can be formed at the corner position of the bottom portion in the stepped hole. In one embodiment, the insulating layer deposited on the pad middle area is removed by etching. The insulating layer may be SiO2Layer or Si3N4And (3) a layer.
As shown in fig. 6 and 7, a metal wiring layer connected to the pad is formed. In one embodiment, the metal circuit layer may be formed by plating copper, nickel or gold through an electroplating process.
As shown in fig. 8 and 9, passivation filling is performed in the first straight hole and the second straight hole, a welding area is reserved, and a solder ball is arranged in the reserved welding area.
In summary, the semiconductor device of the present invention forms the step hole communicating with the pad by forming the two holes, and the step hole is favorable for forming a thicker insulating layer at the corner position of the bottom in the step hole, so as to have obvious advantages of reducing the pad pressure and reducing the risk of wire break of the metal circuit layer, and relieve the pull stress of the metal circuit layer on the pad.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (10)
1. A semiconductor device, characterized in that the semiconductor device comprises:
a first substrate,
A second substrate disposed on the first substrate,
A pad disposed on the second substrate,
A metal wiring layer connected to the pad;
the first substrate is provided with a stepped hole communicated to the pad, an insulating layer is arranged between the metal circuit layer and the pad, and the insulating layer is arranged at the corner position of the bottom in the stepped hole.
2. The semiconductor device according to claim 1, wherein the first substrate is a silicon wafer, and the second substrate is a glass wafer.
3. The semiconductor device according to claim 1 or 2, wherein the first substrate and the second substrate are connected by an adhesive.
4. The semiconductor device according to claim 1, wherein the insulating layer is SiO formed by deposition2Layer or Si3N4And (3) a layer.
5. A method for manufacturing a semiconductor device, the method comprising:
manufacturing a first straight hole corresponding to part of the pad on the first substrate, wherein the bottom of the first straight hole is spaced from the pad opposite to the first straight hole;
continuously manufacturing a second straight hole communicated to the bonding pad at the bottom of the manufactured first straight hole;
depositing an insulating layer on the first substrate, removing the insulating layer deposited on the middle area of the bonding pad, and reserving the deposited layer at the corner position of the hole bottom of the second straight hole;
and manufacturing a metal circuit layer connected to the bonding pad.
6. The method for manufacturing a semiconductor device according to claim 5, wherein the first substrate is a silicon wafer, and wherein the second substrate is a glass plate.
7. The method for manufacturing a semiconductor device according to claim 5 or 6, wherein the first substrate and the second substrate are connected by an adhesive.
8. The method for manufacturing a semiconductor device according to claim 5, wherein the insulating layer is SiO2Layer or Si3N4And (3) a layer.
9. The method for manufacturing a semiconductor device according to claim 5, wherein the first straight hole and the second straight hole are formed by etching, and the insulating layer deposited on the pad middle region is removed.
10. The method for manufacturing a semiconductor device according to claim 5, further comprising: and passivating and filling the first straight hole and the second straight hole, reserving a welding area, and arranging a welding ball in the reserved welding area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911145477.8A CN111029321A (en) | 2019-11-21 | 2019-11-21 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911145477.8A CN111029321A (en) | 2019-11-21 | 2019-11-21 | Semiconductor device and method for manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111029321A true CN111029321A (en) | 2020-04-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911145477.8A Pending CN111029321A (en) | 2019-11-21 | 2019-11-21 | Semiconductor device and method for manufacturing the same |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102509718A (en) * | 2011-12-15 | 2012-06-20 | 中国科学院上海微系统与信息技术研究所 | Wafer-level chip size encapsulation technology for GaAs (gallium arsenide) CCD (Charge Coupled Device) image sensor |
| CN102637713A (en) * | 2012-03-31 | 2012-08-15 | 江阴长电先进封装有限公司 | Method for packaging image sensor comprising metal micro-bumps |
| CN103000649A (en) * | 2012-11-22 | 2013-03-27 | 北京工业大学 | Packaging structure and manufacture method for complementary metal-oxide-semiconductor transistor (CMOS) image sensors |
| CN103474365A (en) * | 2013-09-04 | 2013-12-25 | 惠州硕贝德无线科技股份有限公司 | Method for packaging semiconductor |
-
2019
- 2019-11-21 CN CN201911145477.8A patent/CN111029321A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102509718A (en) * | 2011-12-15 | 2012-06-20 | 中国科学院上海微系统与信息技术研究所 | Wafer-level chip size encapsulation technology for GaAs (gallium arsenide) CCD (Charge Coupled Device) image sensor |
| CN102637713A (en) * | 2012-03-31 | 2012-08-15 | 江阴长电先进封装有限公司 | Method for packaging image sensor comprising metal micro-bumps |
| CN103000649A (en) * | 2012-11-22 | 2013-03-27 | 北京工业大学 | Packaging structure and manufacture method for complementary metal-oxide-semiconductor transistor (CMOS) image sensors |
| CN103474365A (en) * | 2013-09-04 | 2013-12-25 | 惠州硕贝德无线科技股份有限公司 | Method for packaging semiconductor |
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Application publication date: 20200417 |