CN210805781U

CN210805781U - Wafer-level packaging structure of photoelectric device

Info

Publication number: CN210805781U
Application number: CN201922258962.8U
Authority: CN
Inventors: 王成迁
Original assignee: CETC 58 Research Institute
Current assignee: CETC 58 Research Institute
Priority date: 2019-12-17
Filing date: 2019-12-17
Publication date: 2020-06-19
Anticipated expiration: 2029-12-17

Abstract

The utility model discloses a photoelectric device wafer level packaging structure belongs to integrated circuit encapsulation field. The wafer-level packaging structure of the photoelectric device comprises a glass cover plate, wherein a cofferdam is manufactured on the glass cover plate, and the cofferdam is bonded with a functional layer on the front surface of a chip wafer through bonding glue; the silicon substrate on the back of the chip wafer is provided with a groove, a copper column is manufactured in the groove and is plastically packaged through a second plastic packaging material, and n layers of rewiring, a solder mask and bumps are sequentially formed on the surface of the second plastic packaging material. The cofferdam is manufactured through primary plastic packaging, the functional layer is interconnected with the back surface of the silicon substrate through secondary plastic packaging, and the rewiring area of the back surface of the silicon substrate is increased. Except one surface of the glass cover plate, other five surfaces of the whole packaging body are wrapped by the plastic packaging material, so that the problem of imaging ghost of the photoelectric device caused by light leakage is solved; the packaging method and the structure are simple, the cost is low, the yield is high, and the packaging method is suitable for large-scale mass production.

Description

Wafer-level packaging structure of photoelectric device

Technical Field

The utility model relates to an integrated circuit packaging technology field, in particular to photoelectric device wafer level packaging structure.

Background

In recent years, with the appearance and development of three-shot, four-shot and even five-shot mobile phone cameras, the packaging requirements of photoelectric devices, especially image sensors, are increasing. At present, how to reduce the packaging cost of the camera module becomes a key point of attention of various large design, packaging and terminal companies. Among many packaging schemes, CSP packaging costs the lowest. However, CSP packaging also has the problems of high difficulty in manufacturing TSV and cofferdam, high cost, ghost image of wafer level packaging products and the like. In addition, as wafer fabrication progresses toward smaller process nodes, the number of I/os of sensor chips of photoelectric devices increases, and how to increase the rewiring area and the rewiring interconnection density also becomes an urgent problem to be solved in CSP packaging.

The patent applications 201310667563.1 and 201910605108.6 describe cofferdam fabrication and ghost image resolution, respectively, but the packaging scheme is relatively complex. The patent with the application number of 201610528310.X introduces a manufacturing method of a TSV of a photoelectric device package, although the rewiring area of the back surface of a silicon substrate can be increased, the scheme needs to be drilled by processes such as laser ablation, the appearance of the TSV is difficult to control, and the subsequent rewiring difficulty is improved.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a photoelectric device wafer level packaging structure to solve the easy light leak of present photoelectric device, thereby lead to the problem of formation of image "ghost".

In order to solve the technical problem, the utility model provides a photoelectric device wafer level packaging structure, include:

the chip wafer comprises a glass cover plate, wherein a cofferdam is manufactured on the glass cover plate and is bonded with a functional layer on the front surface of the chip wafer through bonding glue;

the silicon substrate on the back of the chip wafer is provided with a groove, a copper column is manufactured in the groove and is plastically packaged through a second plastic packaging material, and n layers of rewiring, a solder mask and bumps are sequentially formed on the surface of the second plastic packaging material.

Optionally, a cofferdam is manufactured on the glass cover plate by the following method:

providing a glass cover plate, and manufacturing a mask pattern on the surface of the glass cover plate;

plastically packaging the mask pattern by using a first plastic packaging material, and grinding the mask pattern to a target thickness;

the abrasive pattern is removed to form a bank.

Optionally, the thickness of the mask pattern is greater than that of the bank, and the mask pattern is made of a polymer material or a metal material;

the high polymer material comprises resin and polyimide;

the metal material includes copper and aluminum.

Optionally, the first plastic package material and the second plastic package material are the same plastic package material, and are black resin materials, and the light absorption rate of the black resin materials is greater than 90%.

Optionally, the groove is a V-shaped groove, the depth of the groove is greater than 5 μm, the lower opening of the groove is greater than 5 μm, and the angle of the groove is greater than 90 °.

Optionally, a copper pillar is grown in the groove through a copper pillar bump preparation process, wherein the diameter of the copper pillar is larger than 1 μm, and the height of the copper pillar exceeds the silicon substrate on the back surface of the chip wafer by more than 1 μm.

Optionally, one surface of the adhesive is connected with the functional layer, and the other surface of the adhesive is connected with the cofferdam; the adhesive is black, and the light absorptivity of the adhesive is greater than 90%.

The utility model provides a wafer-level packaging structure of photoelectric device, which comprises a glass cover plate, wherein a cofferdam is manufactured on the glass cover plate, and the cofferdam is bonded with a functional layer on the front side of a chip wafer through bonding glue; the silicon substrate on the back of the chip wafer is provided with a groove, a copper column is manufactured in the groove and is plastically packaged through a second plastic packaging material, and n layers of rewiring, a solder mask and bumps are sequentially formed on the surface of the second plastic packaging material.

The chip wafer is bonded with the glass cover plate through the cofferdam, and the functional layer of the chip is connected with the rewiring layer on the back of the chip through the copper column; the cofferdam is manufactured through primary plastic packaging, the functional layer is interconnected with the back surface of the silicon substrate through secondary plastic packaging, and the rewiring area of the back surface of the silicon substrate is increased. Except one surface of the glass cover plate, other five surfaces of the whole packaging body are wrapped by the plastic packaging material, so that the problem of imaging ghost of the photoelectric device caused by light leakage is solved; the packaging method and the structure are simple, the cost is low, the yield is high, and the packaging method is suitable for large-scale mass production.

Drawings

Fig. 1 is a schematic view of a wafer level package structure of a photoelectric device provided by the present invention;

FIG. 2 is a schematic diagram of a cut to form individual packages;

FIG. 3 is a schematic view of a mask pattern formed on a glass cover plate;

FIG. 4 is a schematic illustration of plastic encapsulation on a glass cover plate with a first molding compound;

FIG. 5 is a schematic view of polishing the first molding compound to a target thickness;

FIG. 6 is a schematic view of a bank formed by removing a mask pattern;

FIG. 7 is a schematic view of bonding a chip wafer on a dam;

FIG. 8 is a schematic view of a silicon substrate with a recess formed on the backside of a chip wafer;

FIG. 9 is a schematic illustration of growing copper pillars in the grooves;

FIG. 10 is a schematic view of the backside of a chip wafer being encapsulated with a second encapsulant;

FIG. 11 is a schematic view of the backside of the wafer with the chip polished until the copper pillars are exposed;

fig. 12 is a schematic diagram of the fabrication of n-layer rewiring.

Detailed Description

The wafer level package structure of the optoelectronic device proposed in the present invention is further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more fully apparent from the following description and appended claims. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.

Example one

The utility model provides a wafer-level packaging structure of photoelectric device, the structure of which is shown in figure 1, comprising a glass cover plate 101, a cofferdam 104 is manufactured on the glass cover plate 101, and the cofferdam 104 is bonded with a functional layer 106 on the front surface of a chip wafer 105 through an adhesive 107; a groove 109 is formed in the silicon substrate on the back surface of the chip wafer 105, a copper column 110 is manufactured in the groove 109 through a copper column bump manufacturing process and is plastically packaged through a second plastic packaging material 111, the diameter of the copper column 110 is larger than 1 micrometer, and the height of the copper column 110 exceeds the silicon substrate on the back surface of the chip wafer 105 by more than 1 micrometer; n layers of rewiring 112, solder resist layers 113 and bumps 114 are sequentially formed on the surface of the second plastic package material 111. The groove 109 is a V-shaped groove, the depth of the groove is larger than 5 microns, the lower opening of the groove is larger than 5 microns, and the angle of the groove is larger than 90 degrees. One side of the adhesive 107 is connected with the functional layer 106, and the other side is connected with the cofferdam 104; the adhesive 107 is black and has a light absorption rate of more than 90%.

A cofferdam 104 is made on said glass cover plate 101 by the following method: providing a glass cover plate 101, and manufacturing a mask pattern 102 on the surface of the glass cover plate; plastically packaging the mask pattern 102 by using a first plastic packaging material 103, and grinding to a target thickness; the abrasive pattern 102 is removed to form a bank 104. The thickness of the mask pattern 102 is greater than that of the bank 104, and the material of the mask pattern 102 is a polymer material or a metal material; the high polymer material comprises resin and polyimide; the metal material includes copper and aluminum. The first molding compound 103 and the second molding compound 111 are the same molding compound, are black resin materials, and have a light absorption rate of more than 90%.

The single packaged chip shown in fig. 2 is obtained by cutting the package structure shown in fig. 1.

The utility model provides a photoelectric device wafer level packaging structure forms through following method preparation:

firstly, providing a glass cover plate 101, and making a mask pattern 102 on the surface of the glass cover plate, as shown in fig. 3; the thickness of the mask pattern 102 is greater than that of the bank 104 to be manufactured, and the material of the mask pattern 102 may be a polymer material such as resin, polyimide, or a metal material such as copper, aluminum;

the mask pattern 102 is plastically packaged by a first plastic package material 103, as shown in fig. 4, the first plastic package material 103 is a black resin material, and the light absorption rate is greater than 90%; then, grinding the first plastic package material 103 to the target thickness of the cofferdam 104 to be manufactured in a grinding way, as shown in fig. 5;

removing the mask pattern 102 by processes such as similar dissolution or etching, and forming a bank 104, as shown in fig. 6;

bonding a functional layer 106 of a chip wafer 105 with the cofferdam 104 through an adhesive 107, wherein one surface of the adhesive 107 is connected with the functional layer 106, and the other surface of the adhesive 107 is connected with the cofferdam 104; as shown in fig. 7; wherein the bonding layer 107 is black, and has a light absorption rate of more than 90%;

the back silicon substrate of the chip wafer 105 is thinned to a target thickness by grinding or etching process, and a V-shaped groove 109 is etched by using a dry etching method, wherein the groove depth of the V-shaped groove is greater than 5 μm, the lower opening of the groove is greater than 5 μm, and the groove angle is greater than 90 degrees, as shown in fig. 8;

as shown in fig. 9, a copper pillar 110 is grown in the V-shaped groove 109 by a copper pillar bump preparation technique, the copper pillar 110 is connected to the functional layer 106, the height of the copper pillar 110 is more than 1 μm higher than the silicon substrate on the back surface of the chip wafer 105, and the diameter of the copper pillar 110 is greater than 1 μm;

filling the V-shaped groove 109 with a second molding compound 111 and completely covering the copper pillar 110, as shown in fig. 10; the second molding compound 111 is a black resin material like the first molding compound 103, and has a light absorption rate of more than 90%; then, the second molding compound 111 is ground to expose the copper pillar 110, and the thickness of the ground second molding compound 111 is more than 1 μm, so that the silicon-based back surface is completely covered by the second molding compound 111, as shown in fig. 11;

as shown in fig. 12, n layers of rewiring 112 are manufactured through photolithography and electroplating processes, so that the functional layer 106 and the back silicon-based interconnection are realized;

finally, as shown in fig. 1, the solder mask layer 113 and the bumps 114 are fabricated to form a wafer-level packaging structure of the optoelectronic device, and the single packaged chip as shown in fig. 2 is formed by cutting.

The above description is only for the preferred embodiment of the present invention and is not intended to limit the scope of the present invention, and any modification and modification made by those skilled in the art according to the above disclosure are all within the scope of the claims.

Claims

1. A wafer level package structure of a photoelectric device is characterized by comprising:

the chip wafer structure comprises a glass cover plate (101), wherein a cofferdam (104) is manufactured on the glass cover plate (101), and the cofferdam (104) is bonded with a functional layer (106) on the front surface of a chip wafer (105) through adhesive glue (107);

the silicon substrate on the back of the chip wafer (105) is provided with a groove (109), a copper column (110) is manufactured in the groove (109) and is plastically packaged by a second plastic packaging material (111), and n layers of rewiring (112), a solder mask layer (113) and bumps (114) are sequentially formed on the surface of the second plastic packaging material (111).

2. The wafer-level package structure of optoelectronic devices according to claim 1, characterized in that a dam (104) is made on the glass cover plate (101) by:

providing a glass cover plate (101), and manufacturing a mask pattern (102) on the surface of the glass cover plate;

plastically packaging the mask pattern (102) by using a first plastic packaging material (103), and grinding to a target thickness;

the mask pattern (102) is removed to form a bank (104).

3. The wafer level package structure of optoelectronic device according to claim 2, wherein the thickness of the mask pattern (102) is greater than the dam (104), the material of the mask pattern (102) is a polymer material or a metal material;

the high polymer material comprises resin and polyimide;

the metal material includes copper and aluminum.

4. The wafer-level package structure of the optoelectronic device according to claim 2, wherein the first molding compound (103) and the second molding compound (111) are the same molding compound, and are black resin materials with light absorptivity greater than 90%.

5. The wafer level package structure of optoelectronic devices according to claim 1, wherein the groove (109) is a V-shaped groove with a groove depth greater than 5 μm, a groove lower opening greater than 5 μm, and a groove angle greater than 90 °.

6. The wafer-level packaging structure of optoelectronic devices according to claim 1, wherein the copper pillars (110) are grown in the grooves (109) by a copper pillar bump fabrication process, the diameter of the copper pillars (110) is greater than 1 μm, and the height thereof exceeds the silicon substrate on the back side of the chip wafer (105) by more than 1 μm.

7. The wafer-level packaging structure of photoelectric devices according to claim 1, wherein one side of the adhesive (107) is connected to the functional layer (106) and the other side is connected to the dam (104); the adhesive (107) is black and has a light absorption rate of more than 90%.