CN106992159A - Double-face adhesive chip electronic component and its method for packing - Google Patents
Double-face adhesive chip electronic component and its method for packing Download PDFInfo
- Publication number
- CN106992159A CN106992159A CN201611118717.1A CN201611118717A CN106992159A CN 106992159 A CN106992159 A CN 106992159A CN 201611118717 A CN201611118717 A CN 201611118717A CN 106992159 A CN106992159 A CN 106992159A
- Authority
- CN
- China
- Prior art keywords
- electrode
- core body
- electronic component
- double
- face adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000853 adhesive Substances 0.000 title claims abstract description 33
- 230000001070 adhesive effect Effects 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 title claims description 24
- 238000012856 packing Methods 0.000 title claims description 15
- 239000011231 conductive filler Substances 0.000 claims abstract description 25
- 230000000994 depressogenic effect Effects 0.000 claims abstract description 24
- 239000011810 insulating material Substances 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 15
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 239000003292 glue Substances 0.000 claims description 8
- 239000011889 copper foil Substances 0.000 claims description 7
- 239000003822 epoxy resin Substances 0.000 claims description 7
- 229920000647 polyepoxide Polymers 0.000 claims description 7
- 238000005538 encapsulation Methods 0.000 claims description 6
- 239000011521 glass Substances 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 4
- 239000006060 molten glass Substances 0.000 claims description 4
- 239000002002 slurry Substances 0.000 claims description 4
- 238000007711 solidification Methods 0.000 claims description 3
- 230000008023 solidification Effects 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920000297 Rayon Polymers 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Adhesives Or Adhesive Processes (AREA)
Abstract
A kind of Double-face adhesive chip electronic component; including a core body; the core body sets first electrode and second electrode respectively with respect to two surfaces; also include one first insulating protection ring; first insulating protection ring is arranged on surface where the first electrode of the core body, and surround the first electrode to form depressed part；At least end face in the both ends of the surface of first insulating protection ring is raised to the electrode surface for being higher by the core body and forms depressed part, and the electrode that the depressed part is used to set conductive filler to ensure the core body can be electrically connected with outside.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of Double-face adhesive chip electronic component and its method for packing
(DMT：Dual-surface Mounting Technology).
Background technology
The electronic component that diode, electric capacity, resistance and inductance etc. have two electrodes is widely used in various electricity
In sub-circuit.Positive and negative electrode is set to be a kind of common electrode setting mode in relative two faces.But due to the chi of this device
Very little usual very little, after being welded on circuit, solder is easy to trickling to the side of electronic component, so as to cause both positive and negative polarity
Between short circuit.There was only the electronic component of several millimeters of small size for width, such case is easier to occur.Therefore, it is right
Solder effluent how is avoided in small size electronic component, is prior art urgent problem to be solved.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of Double-face adhesive chip electronic component and its method for packing,
Solder effluent can be avoided, and then prevents short circuit between the electrode of electronic component.
It is described the invention provides a kind of Double-face adhesive chip electronic component, including a core body in order to solve the above problems
Core body sets first electrode and second electrode, in addition to one first insulating protection ring, first insulation respectively with respect to two surfaces
Protection ring is arranged on surface where the first electrode of the core body, and around the first electrode to form depressed part, it is described recessed
The electrode that the portion of falling into is used to set conductive filler to ensure the core body can be electrically connected with outside.
Optionally, any one of the core body in diode, electric capacity, resistance and inductance
Optionally, the material of first insulating protection ring is one kind in epoxy resin, glass and uv-curable glue.
Optionally, the material of the conductive filler is scolding tin.
Optionally, the conductive filler includes two layers of soldering-tin layer and the copper foil being arranged between two layers of soldering-tin layer.
Optionally, in addition to one second insulating protection ring, second insulating protection ring is arranged on the second of the core body
Surface where electrode, and surround the second electrode to form the depressed part for setting conductive filler.
Optionally, the core body is unencapsulated core body chip, or electrode has been separately positioned on relative two surfaces
Encapsulate chip.
Present invention also offers a kind of method for packing of Double-face adhesive chip electronic component, comprise the following steps：There is provided one
Substrate；At least one core body is set on the surface of the substrate, the core body with respect to two surfaces set respectively first electrode and
Second electrode, the second electrode of the core body and the baseplate-laminating；Gel insulating materials is filled in around the core body, it is described
Gel insulating materials is raised to the first electrode surface for being higher by the core body and depressed part is formed at first electrode；Solidification institute
State gel insulating materials.
Optionally, also comprise the following steps after the step of solidifying the gel insulating materials：Cut the gel
Shape insulating materials.
Optionally, the gel insulating materials is selected from epoxy resin, high temperature molten glass slurry and uv-curable glue
In one kind.
Optionally, the core body is unencapsulated chip, or electrode is separately positioned on the encapsulation on relative two surfaces
Chip.
The present invention proposes a kind of two-sided paster type encapsulation technology (DMT：Dual-surface Mounting
Technology).Employ the mode at least one electrode surface formation depression of core body, it is to avoid the material such as solder is in height
The lower generation lateral flow of temperature causes Double-face adhesive chip electronic component to occur short circuit.The method provided employs substrate surface and filled out
The gel-filled shape insulating materials and mode solidified forms electrode surface and has the Double-face adhesive chip electronic component of depression, except can
To avoid outside solder effluent, the Double-face adhesive chip electronic component appearance and size and shape formed can accomplish accurate control
System.
Brief description of the drawings
It is the electronics of an embodiment of Double-face adhesive chip electronic component of the present invention shown in accompanying drawing 1A and 1B
Component structure schematic diagram.
It is the electronics of an embodiment of Double-face adhesive chip electronic component of the present invention shown in accompanying drawing 2A and 2B
Component structure schematic diagram.
It is the reality of the embodiment of method for packing one of Double-face adhesive chip electronic component of the present invention shown in accompanying drawing 3
Apply step schematic diagram.
It is the specific reality of method for packing one of Double-face adhesive chip electronic component of the present invention shown in accompanying drawing 4A to accompanying drawing 4C
Apply the process schematic representation of mode.
Embodiment
The Double-face adhesive chip electronic component and Double-face adhesive chip electronic member device provided below in conjunction with the accompanying drawings the present invention
The embodiment of the method for packing of part elaborates.
In detailed description below, unified that first electrode is configured into positive pole, second electrode is configured to negative pole.Other
Embodiment in, first electrode can also be configured to negative pole, the second electrode is configured to positive pole.
It is the structural representation of electronic component 10 described in present embodiment shown in refer to the attached drawing 1A, including core body 13
With protection ring 14a.The core body 13 is that any one sets the component of positive and negative electrode in relative two faces, can be selected from two
Any one in pole pipe, electric capacity, resistance and inductance.
In this embodiment, the core body 13 is unencapsulated chip.In other embodiments, institute
It can also be the encapsulation chip that electrode is separately positioned on relative two surfaces to state core body 13.The core body 13 is distinguished with respect to two surfaces
Positive pole 131 and negative pole 132 are set.
First insulating protection ring 14a is arranged on the place surface of first electrode 131 of the core body 13, and around described first
Electrode 131 is to form depressed part 15.In this embodiment, the first insulating protection ring 14a is entirely located in the core
The place surface of first electrode 131 of body 13.And the knot of the electronic component 10 in another embodiment shown in accompanying drawing 1B
In structure schematic diagram, the first insulating protection ring 14b is further wrapped in addition to the place surface of first electrode 131 positioned at the core body 13
Wrap up in the side of core body 13.In this embodiment, the material of the first insulating protection ring 14a is epoxy resin.At it
In his embodiment, the material of the first insulating protection ring 14a can also be glass or uv-curable glue.It is described
First dead ring 14a height is not less than 60 microns, and preferably 80 microns -100 microns to ensure to conductive filler 16
Carrying capacity.
The electrode that the depressed part 15 is used to set conductive filler 16 to ensure the core body 13 can be with corresponding weldering
Charging property is connected.The material of the conductive filler 16 is scolding tin.In order to obtain superior technique effect, the conductive filler
Copper foil 163 is also set up between 16 two layers of soldering-tin layer 161 and 162.The thickness range of the copper foil is 30 microns -50 microns.Copper
The effect of paper tinsel is to buffer the stress between conductive filler and positive pole 131, it is to avoid scolding tin departs from the case of temperature change
Depressed part 15.The insulating protection ring 14a/b of depressed part 15 and first outer rim is can be with along the section perpendicular to page
It is the arbitrary shapes such as circular, rectangle or round rectangle.Because the first insulating protection ring 14a/b is being higher by electronic component 10 just
The surface of pole 131 simultaneously forms depressed part 15, conductive filler 16 can be limited in inside depressed part 15, even if conductive filler 16
Fusing occurs in high temperature environments will not also spill into the side of electronic component 10 and occur electrically to connect with the electrode of opposite side
Connect.
It is the structural representation of another embodiment of electronic component of the present invention shown in refer to the attached drawing 2A.
In present embodiment, electronic component 20 includes a core body 23.First insulating protection ring 241a and the second insulating protection ring
242a is separately positioned on first electrode 231 and the place surface of second electrode 232 of the core body 23, and around the first electrode
231 and second electrode 232 to form depressed part 251 and 252, all there is the depressed part 251 and 252 conductive filler to ensure
The electrode of the core body 23 can be electrically connected with corresponding welding.Depressed part 251 and 252 is along cuing open perpendicular to page
Face can it is each independent be the arbitrary shapes such as circular, rectangle or round rectangle.In this embodiment, described first
Insulating protection ring 241a and the second insulating protection ring 242a are entirely located in the first electrode 231 and second electrode of the core body 23
232 places surface.And in the structural representation of the electronic component 20 of another embodiment shown in accompanying drawing 2B, first
Insulating protection ring 241b and the second insulating protection ring 242b removes the first electrode 231 and second electrode 232 positioned at the core body 23
Outside the surface of place, the side of core body 23 is further wrapped up.Due to depressed part 251 and 252, conductive filler can be limited
Inside depressed part 251 and 252, electronic component will not also be spilt into by occurring fusing in high temperature environments even if conductive filler
20 side.Likewise, the material of the conductive filler can be selected as scolding tin, and two layers of scolding tin of the conductive filler
Copper foil can be similarly set to increase intensity between layer.Conductive fill of the present embodiment to the both sides of electronic component 20
Thing is any limitation as, thus be it is a kind of preferred embodiment.
It is the reality of the embodiment of method for packing one of Double-face adhesive chip electronic component of the present invention shown in accompanying drawing 3
Step schematic diagram is applied, is comprised the following steps：There is provided a substrate by step S30；Step S31, set on the surface of the substrate to
A few core body；Step S32, gel insulating materials is filled in around the core body；Step S33, solidifies the gel insulation
Material.
It is the specific reality of method for packing one of Double-face adhesive chip electronic component of the present invention shown in accompanying drawing 4A to accompanying drawing 4C
Apply the process schematic representation of mode.
Shown in accompanying drawing 4A, with reference to step S30, there is provided a substrate 40.The substrate 40 is used as the carrier of subsequent technique, its material
Material can be the nonmetallic materials such as the metals such as copper, aluminium or glass, monocrystalline silicon.
Shown in accompanying drawing 4B, with reference to step S31, at least one core body 43 is set on the surface of the substrate 40.The core
Body 43 sets first electrode 431 and second electrode 432 respectively with respect to two surfaces, the second electrode 432 of the core body 43 with it is described
Baseplate-laminating.In another embodiment or first electrode 431 is fitted with the substrate 40.In order to increase
Laminating intensity, can also set viscose glue in joint.
Shown in accompanying drawing 4C, with reference to step S32, gel insulating materials 44 is filled in around the core body 43.The gel
Insulating materials 44 is raised to the surface of first electrode 431 for being higher by the core body 43 and depressed part is formed at first electrode 431
451.The depressed part 451 is used to be filled with conductive filler.The gel insulating materials 44 can be selected from
One kind in epoxy resin, high temperature molten glass slurry and uv-curable glue.
Step S33, solidifies the gel insulating materials 44.Should be using not for different gel insulating materials 44
Same curing mode.High temperature curing process for example can be used for epoxy resin, should be by for high temperature molten glass slurry
It is reduced to room temperature and solidified, and should be solidified for uv-curable glue using ultraviolet irradiation.
Above-mentioned steps employ the mode filled in gel insulating materials 44 and solidified in the surface of substrate 40 and form electrode surface
Double-face adhesive chip electronic component with depression 451.The amount of filling in of material is filled in by control, accurately can control to be formed
Electronic component appearance and size.If it is desired to further accurately control the shape and size of electronic component, it can also enter
One step implements cutting step.
Specifically, after above-mentioned steps S33 is finished, it can select to implement the cutting gel insulating materials 44
The step of.The gel insulating materials 44 can be implemented according to predetermined shape and size, such as rectangle or square
Shaping is cut to obtain the electronic component of predetermined shape.If arrangement density of the core body 43 on the surface of substrate 40 is relatively low, Ke Yi
By controlling the amount of filling in the gel insulating materials 44 between adjacent core body is not contacted in step S32, then after solidification may be used
Directly to remove the core body 43 for having surround gel insulating materials 44 on the surface of substrate 40 without implementing cutting step.In cutting
The structure on the surface of substrate 40 can also be carried out to overall reversion before.After reversion scolding tin etc. is coated on the surface of second electrode 432
Material formation electrode, then implements cutting again.In the technique that reverse side coats scolding tin, one layer of copper foil of patch can also be pressed from both sides in scolding tin
To increase intensity.If the chip of encapsulation for being separately positioned on relative two surfaces using electrode also may be used as the core body 13
Directly implement cutting not make back electrode.In the technique of dual coating scolding tin, in order to distinguish positive pole and negative pole, Ke Yi
It is two-sided to add different patterns respectively and distinguished., can be using not especially in the technique using screen-printing deposition scolding tin
Different figures are obtained with the silk screen of spacing, so as to distinguish positive pole and negative pole.
Before cutting it is also an option that the step of implementing to fill conductive filler in depressed part 451.The step can also
Implement after dicing.Material and structure on conductive filler refer to previous embodiment to conductive filler 16
Description.
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, under the premise without departing from the principles of the invention, can also make some improvements and modifications, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (14)
1. a kind of Double-face adhesive chip electronic component, including a core body, the core body set first electrode respectively with respect to two surfaces
And second electrode, it is characterised in that
Also include one first insulating protection ring, first insulating protection ring is arranged on table where the first electrode of the core body
Face, and around the first electrode to form depressed part, the depressed part is used to set conductive filler to ensure the core body
Electrode can with outside be electrically connected with.
2. Double-face adhesive chip electronic component according to claim 1, it is characterised in that the core body is selected from two poles
Any one in pipe, electric capacity, resistance and inductance.
3. Double-face adhesive chip electronic component according to claim 1, it is characterised in that first insulating protection ring
Material is one kind in epoxy resin, glass and uv-curable glue.
4. Double-face adhesive chip electronic component according to claim 1, it is characterised in that the material of the conductive filler
For scolding tin.
5. Double-face adhesive chip electronic component according to claim 1, it is characterised in that the conductive filler includes two
Layer soldering-tin layer and the copper foil being arranged between two layers of soldering-tin layer.
6. Double-face adhesive chip electronic component according to claim 5, it is characterised in that the thickness range of the copper foil is
30 microns -50 microns.
7. Double-face adhesive chip electronic component according to claim 1, it is characterised in that the height of first dead ring
Not less than 60 microns.
8. Double-face adhesive chip electronic component according to claim 1, it is characterised in that also including one second insulation protection
Ring, second insulating protection ring is arranged on surface where the second electrode of the core body, and around the second electrode with shape
Into the depressed part for setting conductive filler.
9. Double-face adhesive chip electronic component according to claim 1, it is characterised in that the core body is unencapsulated crystalline substance
Piece, or electrode are separately positioned on the encapsulation chip on relative two surfaces.
10. a kind of method for packing of Double-face adhesive chip electronic component, it is characterised in that comprise the following steps：
One substrate is provided；
At least one core body is set on the surface of the substrate, and the core body sets first electrode and respectively with respect to two surfaces
Two electrodes, the second electrode of the core body and the baseplate-laminating；
Gel insulating materials is filled in around the core body, the gel insulating materials, which is raised to, is higher by the first of the core body
Electrode surface simultaneously forms depressed part at first electrode；
Solidify the gel insulating materials.
11. the method for packing of Double-face adhesive chip electronic component according to claim 10, it is characterised in that the core body
Any one in diode, electric capacity, resistance and inductance.
12. the method for packing of Double-face adhesive chip electronic component according to claim 10, it is characterised in that in solidification institute
Also comprise the following steps after the step of stating gel insulating materials：Cut the gel insulating materials.
13. the method for packing of Double-face adhesive chip electronic component according to claim 10, it is characterised in that the gel
Shape insulating materials is selected from one kind in epoxy resin, high temperature molten glass slurry and uv-curable glue.
14. the method for packing of Double-face adhesive chip electronic component according to claim 10, it is characterised in that the core body
The encapsulation chip on relative two surfaces is separately positioned on for unencapsulated chip, or electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611118717.1A CN106992159A (en) | 2016-12-07 | 2016-12-07 | Double-face adhesive chip electronic component and its method for packing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611118717.1A CN106992159A (en) | 2016-12-07 | 2016-12-07 | Double-face adhesive chip electronic component and its method for packing |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106992159A true CN106992159A (en) | 2017-07-28 |
Family
ID=59414148
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611118717.1A Pending CN106992159A (en) | 2016-12-07 | 2016-12-07 | Double-face adhesive chip electronic component and its method for packing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106992159A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110176447A (en) * | 2019-05-08 | 2019-08-27 | 上海地肇电子科技有限公司 | Surface-assembled component and its packaging method |
| WO2022110935A1 (en) * | 2020-11-26 | 2022-06-02 | 苏州矽锡谷半导体科技有限公司 | Cutting method for semiconductor chip |
-
2016
- 2016-12-07 CN CN201611118717.1A patent/CN106992159A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110176447A (en) * | 2019-05-08 | 2019-08-27 | 上海地肇电子科技有限公司 | Surface-assembled component and its packaging method |
| WO2022110935A1 (en) * | 2020-11-26 | 2022-06-02 | 苏州矽锡谷半导体科技有限公司 | Cutting method for semiconductor chip |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20170728 |
|
| WD01 | Invention patent application deemed withdrawn after publication |