CN115083903A - Wafer cutting method and single chip package - Google Patents

Wafer cutting method and single chip package Download PDF

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Publication number
CN115083903A
CN115083903A CN202210855891.3A CN202210855891A CN115083903A CN 115083903 A CN115083903 A CN 115083903A CN 202210855891 A CN202210855891 A CN 202210855891A CN 115083903 A CN115083903 A CN 115083903A
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chip
semiconductor wafer
cutting
dicing
wafer
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CN202210855891.3A
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CN115083903B (en
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陈国栋
姚军亭
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Shandong Zhongqing Intelligent Technology Co ltd
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Shandong Zhongqing Intelligent Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Dicing (AREA)

Abstract

The invention relates to a wafer cutting method and a single chip package, and relates to the technical field of semiconductor packaging. In the wafer cutting process, a plurality of separately arranged plastic packaging fixing grooves are formed on the upper surface of each chip area, and a plurality of separately arranged heat diffusion grooves are formed on the upper surface of each chip area, so that at least one heat diffusion groove is arranged between every two adjacent plastic packaging fixing grooves. The setting of above-mentioned structure improves the heat dispersion of single-chip packaging body on the one hand, and on the other hand effectively improves the joint strength between plastic envelope layer and the chip, and then avoids taking place to peel off between plastic envelope layer, heat conduction piece and the chip three.

Description

Wafer cutting method and single chip package
Technical Field
The present invention relates to the field of semiconductor packaging technologies, and in particular, to a wafer dicing method and a single chip package.
Background
In the existing wafer dicing process, the wafer is usually directly diced into separate individual chips, and then each chip is packaged separately. The existing wafer cutting and packaging process is complicated and high in cost. How to improve the cutting and packaging process of the wafer, improve the manufacturing efficiency and reduce the cost is a problem that is continuously concerned by the industry.
Disclosure of Invention
It is therefore an object of the present invention to overcome the above-mentioned drawbacks of the prior art and to provide a method for dicing a wafer and a single chip package.
More specifically, the present invention relates to a method for cutting a wafer, which comprises the following steps:
providing a first semiconductor wafer, wherein the first semiconductor wafer comprises a plurality of chip areas arranged in an array mode, and a cutting area surrounding each chip area.
And carrying out first etching treatment on the first semiconductor wafer so as to form a plurality of separately arranged plastic packaging fixing grooves on the upper surface of each chip area.
And performing second etching treatment on the first semiconductor wafer to form a plurality of separately arranged thermal diffusion grooves on the upper surface of each chip area, so that at least one thermal diffusion groove is arranged between every two adjacent plastic package fixing grooves.
After the second etching treatment, performing first cutting treatment on the first semiconductor wafer to form two hollow parts in the cutting area between two adjacent chip areas, wherein the cutting area between the two hollow parts is not cut to be used as a first fixing part, and the first fixing part is connected with the two adjacent chip areas.
Performing plastic packaging treatment on the first semiconductor wafer to form a plastic packaging layer, wherein the plastic packaging layer wraps each chip area and fills the hollow-out part, the plastic packaging fixing groove and the thermal diffusion groove; and removing the plastic packaging material in the thermal diffusion groove, and then depositing a metal material in the thermal diffusion groove to form a heat conduction block.
And carrying out second cutting treatment on the first semiconductor wafer along the cutting area again to form a plurality of separated single-chip packages.
According to an embodiment of the present invention, before the first etching process is performed on the first semiconductor wafer, the method further includes: providing a bearing substrate, and arranging the first semiconductor wafer on the bearing substrate so that the active surface of the chip area faces the bearing substrate.
According to the embodiment of the invention, after the second cutting treatment is carried out on the first semiconductor wafer, the bearing substrate is removed, so that a plurality of single-chip packages are formed.
According to the embodiment of the invention, the depth of the heat diffusion groove is greater than that of the plastic package fixing groove.
According to the embodiment of the invention, the number of the heat diffusion grooves between two adjacent plastic packaging fixing grooves is not less than two.
According to the embodiment of the invention, when the second cutting processing is performed on the first semiconductor wafer along the cutting area, the molding layer and the first fixing portion are cut, so that the first fixing portion in each single chip package is exposed to the molding layer.
The invention also relates to a single chip packaging body which is formed by cutting the wafer by adopting the cutting method.
Compared with the prior art, the invention has the following beneficial effects:
in the wafer cutting process, a plurality of discrete plastic package fixing grooves are formed in the upper surface of each chip area, and a plurality of discrete heat diffusion grooves are formed in the upper surface of each chip area, so that at least one heat diffusion groove is formed between every two adjacent plastic package fixing grooves.
In the specific cutting process, the first etching treatment and the second etching treatment are firstly carried out and then the first cutting treatment process is carried out, so that the situation that deviation occurs when a plastic package fixing groove and a thermal diffusion groove are formed in a chip area is prevented, and further a chip is damaged is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a first etching process and a second etching process performed on a first semiconductor wafer according to the present invention;
FIG. 2 is a schematic view of a first dicing process performed on a first semiconductor wafer according to the present invention;
FIG. 3 is a schematic structural diagram of a first semiconductor wafer undergoing a plastic package process according to the present invention;
fig. 4 is a schematic structural diagram of a second dicing process performed on a first semiconductor wafer according to the present invention.
Description of reference numerals:
100. a first semiconductor wafer; 101. a chip region; 102. cutting the area; 201. plastic packaging fixing grooves; 202. a thermal diffusion tank; 1021. a first fixed part; 300. a plastic packaging layer; 400. a heat conducting block; 500. a single chip package.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it is to be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The invention provides a method for cutting a wafer, which comprises the following steps:
providing a first semiconductor wafer, wherein the first semiconductor wafer comprises a plurality of chip areas arranged in an array mode, and a cutting area surrounding each chip area.
And carrying out first etching treatment on the first semiconductor wafer so as to form a plurality of separately arranged plastic packaging fixing grooves on the upper surface of each chip area.
And performing second etching treatment on the first semiconductor wafer to form a plurality of separately arranged thermal diffusion grooves on the upper surface of each chip area, so that at least one thermal diffusion groove is arranged between every two adjacent plastic package fixing grooves.
And after the second etching treatment, performing first cutting treatment on the first semiconductor wafer to form two hollow parts in the cutting area between two adjacent chip areas, wherein the cutting area between the two hollow parts is not cut to be used as a first fixing part, and the first fixing part is connected with the two adjacent chip areas.
Performing plastic packaging treatment on the first semiconductor wafer to form a plastic packaging layer, wherein the plastic packaging layer wraps each chip area and fills the hollow-out part, the plastic packaging fixing groove and the thermal diffusion groove; and removing the plastic packaging material in the thermal diffusion groove, and then depositing a metal material in the thermal diffusion groove to form a heat conduction block.
And carrying out second cutting treatment on the first semiconductor wafer along the cutting area again to form a plurality of separated single-chip packages.
Further, before the first etching process is performed on the first semiconductor wafer, the method further includes: providing a bearing substrate, and arranging the first semiconductor wafer on the bearing substrate so that the active surface of the chip area faces the bearing substrate.
Further, after the second cutting treatment is carried out on the first semiconductor wafer, the bearing substrate is removed, so that a plurality of single-chip packaging bodies are formed.
Furthermore, the depth of the heat diffusion groove is greater than that of the plastic package fixing groove.
Furthermore, the number of the heat diffusion grooves between two adjacent plastic package fixing grooves is not less than two.
Further, when the first semiconductor wafer is subjected to second cutting processing along the cutting area, the plastic package layer and the first fixing portion are cut, and then the first fixing portion in each single chip package is exposed to the plastic package layer.
The invention also provides a single chip packaging body which is formed by cutting the wafer by adopting the cutting method.
Please refer to fig. 1 to 4. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1 to 4, the present embodiment provides a method for cutting a wafer, which includes the following steps:
as shown in fig. 1, fig. 1 is a top view, first, a first semiconductor wafer 100 is provided, where the first semiconductor wafer 100 includes a plurality of chip regions 101 arranged in an array, and a cutting region 102 surrounding each of the chip regions 101.
In a specific embodiment, the chip area 101 in the first semiconductor wafer 100 may be a microprocessor, a memory, an application specific integrated circuit, a logic circuit, an analog circuit, an RF circuit, or other semiconductor die.
As shown in fig. 1, a first etching process is performed on the first semiconductor wafer 100 to form a plurality of separately disposed plastic fixing grooves 201 on an upper surface of each chip region 101.
In an embodiment, before performing the first etching process on the first semiconductor wafer 100, the method further includes: providing a carrier substrate, and disposing the first semiconductor wafer 100 on the carrier substrate such that the active surface of the chip region 101 faces the carrier substrate, where the carrier substrate may be one of a copper substrate, a ceramic substrate, a stainless steel substrate, an aluminum substrate, and a rigid plastic substrate, and further may provide sufficient strength.
In a specific embodiment, the first etching treatment specific method may be: coating a photoresist solution on the carrier substrate to enable the photoresist solution to completely cover the first semiconductor wafer 100, then obtaining a cured photoresist mask through an exposure and development process, then forming the plastic package fixing groove 201 through a wet etching process or a dry etching process, and then removing the photoresist mask; the first etching treatment specific method may further be: the first semiconductor wafer 100 is subjected to laser irradiation processing by using a photomask mask, so that the plastic sealing fixing groove 201 is formed on the non-active surface of the first semiconductor wafer 100.
As shown in fig. 1, a second etching process is performed on the first semiconductor wafer 100 to form a plurality of separately arranged thermal diffusion grooves 202 on the upper surface of each chip region 101, so that at least one thermal diffusion groove 202 is arranged between two adjacent plastic package fixing grooves 201.
In a specific embodiment, the second etching treatment specific method may be: coating a photoresist solution on the carrier substrate to enable the photoresist solution to completely cover the first semiconductor wafer 100 and fill the plastic packaging fixing groove 201, further performing an exposure and development process to obtain a cured photoresist mask, and then forming the thermal diffusion groove 202 through a wet etching process or a dry etching process; the second etching treatment specific method may further include: the first semiconductor wafer 100 is subjected to a laser irradiation process using a mask to form the thermal diffusion grooves 202 on the non-active surface of the first semiconductor wafer 100.
In a specific embodiment, the depth of the thermal diffusion groove 202 is greater than the depth of the plastic sealing fixing groove 201, and more specifically, the thermal diffusion groove 202 is 10 to 100 micrometers deeper than the plastic sealing fixing groove 201, so that the rapid heat transfer of the chip region 101 can be ensured.
In other specific embodiments, the number of the heat diffusion grooves 202 between two adjacent plastic fixation grooves 201 is not less than two (not shown), thereby increasing the heat transfer path.
As shown in fig. 2, after the second etching process, a first cutting process is performed on the first semiconductor wafer 100 to form two hollow portions in the cutting region 102 between two adjacent chip regions 101, and the cutting region between the two hollow portions is not cut to be used as a first fixing portion 1021, where the first fixing portion 1021 connects two adjacent chip regions 101.
In an embodiment, a first cutting process is performed on the first semiconductor wafer 100 by using a cutting tool, a thickness of the first fixing portion 1021 is the same as a thickness of the chip regions 101, and a ratio of a width of the first fixing portion 1021 to a side length of each of the chip regions 101 is 0.2-0.4.
As shown in fig. 3, performing a plastic packaging process on the first semiconductor wafer 100 to form a plastic packaging layer 300, where the plastic packaging layer 300 wraps each chip region 101 and fills the hollow portion, the plastic packaging fixing groove 201, and the thermal diffusion groove 202; the molding compound in the thermal diffusion groove 202 is then removed, and a metal material is then deposited in the thermal diffusion groove 202 to form the thermal conductive block 400.
In a specific embodiment, the molding process is compression molding, transfer molding, liquid encapsulant molding or other suitable molding process, and the thickness of the molding layer 300 is greater than the thickness of the chip region 101.
In a specific embodiment, during the process of removing the molding compound in the heat diffusion groove 202, only a portion of the molding compound in the heat diffusion groove 202 is removed, i.e., the bottom surface of the heat diffusion groove 202 is exposed, and the remaining molding compound covers the sidewall of the heat diffusion groove 202.
In a specific embodiment, the heat conduction block 400 is formed by depositing a metal material, which may be one of silver, copper, and aluminum, by a suitable process such as electroplating, electroless plating, chemical vapor deposition, thermal evaporation, magnetron sputtering, and electron beam evaporation.
As shown in fig. 4, a second dicing process is performed on the first semiconductor wafer 100 along the dicing area 102 again to form a plurality of separated single chip packages 500.
In an embodiment, a second cutting process is performed on the first semiconductor wafer 100 by using a cutting tool, and the second cutting process simultaneously cuts the molding layer 300 and the first fixing portion 1021.
In a specific embodiment, after the second dicing process is performed on the first semiconductor wafer 100, the carrier substrate is removed to form a plurality of single chip packages 500.
In an embodiment, when the second dicing process is performed on the first semiconductor wafer 100 along the dicing area, the molding layer 300 and the first fixing portion 1021 are diced, so that the first fixing portion 1021 in each single chip package 500 is exposed to the molding layer 300.
As shown in fig. 4, the invention further provides a single chip package 500, wherein the single chip package 500 is formed by cutting according to the wafer cutting method.
In the wafer cutting process, a plurality of discrete plastic package fixing grooves 201 are formed on the upper surface of each chip area 101, and a plurality of discrete thermal diffusion grooves 202 are formed on the upper surface of each chip area 101, so that at least one thermal diffusion groove 202 is formed between every two adjacent plastic package fixing grooves 201. In a specific cutting process, the first etching treatment and the second etching treatment are firstly carried out, and then the first cutting treatment process is carried out, so that the situation that deviation occurs when the plastic package fixing groove 201 and the thermal diffusion groove 202 are formed on the chip area 101 is avoided, and further the chip is damaged is avoided, and the first fixing part 1021 is arranged between the adjacent chip areas 101 in the first cutting treatment process, so that the stability of the wafer after the cutting treatment is improved, and further the plastic package is facilitated.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (7)

1. A method for cutting a wafer is characterized by comprising the following steps:
providing a first semiconductor wafer (100), wherein the first semiconductor wafer (100) comprises a plurality of chip regions (101) arranged in an array, and a cutting region (102) surrounding each chip region (101);
performing first etching treatment on the first semiconductor wafer (100) to form a plurality of separately arranged plastic packaging fixing grooves (201) on the upper surface of each chip area (101);
performing second etching treatment on the first semiconductor wafer (100) to form a plurality of separately arranged thermal diffusion grooves (202) on the upper surface of each chip area (101), so that at least one thermal diffusion groove (202) is arranged between every two adjacent plastic packaging fixing grooves (201);
after the second etching treatment, performing a first cutting treatment on the first semiconductor wafer (100) to form two hollowed-out parts in the cutting area (102) between two adjacent chip areas (101), wherein the cutting area (102) between the two hollowed-out parts is not cut to be used as a first fixing part (1021), and the first fixing part (1021) is connected with the two adjacent chip areas (101);
performing plastic packaging treatment on the first semiconductor wafer (100) to form a plastic packaging layer (300), wherein the plastic packaging layer (300) wraps each chip region 101 and fills the hollow part, the plastic packaging fixing groove (201) and the thermal diffusion groove (202); removing the plastic packaging material in the thermal diffusion groove (202), and then depositing a metal material in the thermal diffusion groove (202) to form a heat conduction block (400);
the first semiconductor wafer (100) is subjected to a second dicing process again along the dicing area (102) to form a plurality of separated single-chip packages (500).
2. The method for dicing a wafer according to claim 1, wherein before the first etching process is performed on the first semiconductor wafer (100), the method further comprises: providing a carrier substrate, and arranging the first semiconductor wafer (100) on the carrier substrate so that the active surface of the chip region (101) faces the carrier substrate.
3. The method for dicing a wafer according to claim 2, wherein: after the second cutting process is performed on the first semiconductor wafer (100), the carrier substrate is removed to form a plurality of single chip packages (500).
4. The method for dicing a wafer according to claim 1, wherein: the depth of the heat diffusion groove (202) is larger than that of the plastic package fixing groove (201).
5. The method for dicing a wafer according to claim 4, wherein: the number of the heat diffusion grooves (202) between every two adjacent plastic package fixing grooves (201) is not less than two.
6. The method for dicing a wafer according to claim 1, wherein: when the second cutting processing is performed on the first semiconductor wafer (100) along the cutting area (102), the molding compound layer (300) and the first fixing portion (1021) are cut, so that the first fixing portion (1021) in each single chip package (500) is exposed to the molding compound layer (300).
7. A single chip package (500), wherein the single chip package (500) is formed by dicing according to the wafer dicing method of any one of claims 1 to 6.
CN202210855891.3A 2022-07-21 2022-07-21 Wafer cutting method and single chip package Active CN115083903B (en)

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CN116913773A (en) * 2023-09-12 2023-10-20 威海市泓淋电力技术股份有限公司 Semiconductor chip and forming method thereof
CN116913773B (en) * 2023-09-12 2024-01-26 威海市泓淋电力技术股份有限公司 Semiconductor chip and forming method thereof

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