201135854 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明涉及一種半導體封裝方法，尤其涉及一種具有晶 圓尺寸貼片的封裝方法。 【先前技術】 [0002] 半導體製作過程中，通常在一個晶圓上製作多個電路結 構，然後切割晶圓，將晶圓劃分各個晶片，再將各個晶 片通過貼片焊接等封裝工藝連接至基板上，用於各種產 品的生產製作。 如中國專利公開號CN 194580 5A中，披露了一種半導體 封裝方法，其包括以下步驟：首先，提供具有第一表面 以及第二表面的線路基板。接著，線上路基板的第一表 面上形成無溶劑型雙階熱固性化合物。然後，將無溶劑 型雙階熱固性化合物部分固化，以於線路基板的第一表 面上形成無溶劑型B階粘著層。此後，利用B階粘著層將 晶片粘附到線路基板的第一表面上。之後，將晶片電連 接到線路基板，然後形成密封材料以密封住晶片。該發 明也提供一種能應用于上述封裝方法的載體。 又如中國專利公開號CN1 71 3362A中，公開了一種半導體 封裝構造及其製造方法。該半導體封裝構造，主要包含 一基板以及一半導體元件以及覆晶連接的方式設置在基 板上。本發明的半導體封裝構造包含一連接結構設置在 半導體元件與基板之間並且僅沿著半導體元件底面的邊 緣延伸，用以將半導體元件固接在基板，其中該連接結 構由一膠粘劑固化而形成。該連接結構具有固接及支撐 功能，還能減少半導體元件與基板間的應力，使封裝構 099111678 表單編號 A0101 第 4 頁/共 23 頁 0993160223-0 201135854 [0003]BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package method, and more particularly to a package method having a wafer-size patch. [Prior Art] [0002] In the semiconductor manufacturing process, a plurality of circuit structures are usually fabricated on one wafer, then the wafer is diced, the wafer is divided into individual wafers, and each wafer is connected to the substrate by a package process such as patch bonding. It is used in the production of various products. A semiconductor package method is disclosed in the Chinese Patent Publication No. CN 194580 5A, which comprises the steps of first providing a circuit substrate having a first surface and a second surface. Next, a solventless double-step thermosetting compound is formed on the first surface of the line substrate. Then, the solventless double-stage thermosetting compound is partially cured to form a solvent-free B-stage adhesive layer on the first surface of the wiring substrate. Thereafter, the wafer is adhered to the first surface of the wiring substrate by the B-stage adhesive layer. Thereafter, the wafer is electrically connected to the wiring substrate, and then a sealing material is formed to seal the wafer. The invention also provides a carrier that can be applied to the above packaging method. Further, as disclosed in Chinese Patent Publication No. CN1 71 3362A, a semiconductor package structure and a method of manufacturing the same are disclosed. The semiconductor package structure mainly includes a substrate and a semiconductor element and a flip chip connection disposed on the substrate. The semiconductor package structure of the present invention comprises a connection structure disposed between the semiconductor element and the substrate and extending only along the edge of the bottom surface of the semiconductor element for fixing the semiconductor element to the substrate, wherein the connection structure is formed by curing of an adhesive. The connection structure has a fixing and supporting function, and can reduce the stress between the semiconductor component and the substrate, so that the package structure is 099111678. Form No. A0101 Page 4 of 23 0993160223-0 201135854 [0003]
造結構不至受到高應力影響而剝離。該半導體封誓方法 ’將-半導體s件置於-基板上；將半導體元件以覆晶 連接方式連接在基板；將一膠粘劑沿著半導體晶片封事 構造底面邊緣塗布，在半導體元件底面邊緣與基板間形 成至少一膠粘結構；以及固化該膠粘結構，藉此進一步 將半導體元件固定在基板。 上述現有技術的封裝首先在晶圓上切割得到半導體元件 之後，再將各個半導體it件設置在基板上，通過引線引 出半導體元件電極’然、後塑封半導體元件。該封裳一開 始就對晶圓進行切m進料賴元件電極的連接 及封裝，其i序繁多’並且對各個半導體元件的單獨封 裝使封裝㈣積增大’封裝的成本增加；料半導體元 件的電極包覆在封裝内，使得半導體糾的散熱性能變 差。 【發明内容】 本發明的目岐提供-種晶欧相則封裝方法該 封裝方法通過晶圓尺寸的貼片弓丨出晶圓上各個晶片的頂 部電極’ ^後對晶圓尺寸模壓封裝，接著通過晶圓底部 研磨暴露出晶圓晶片的底部電極，最後進行切割，簡化 了封裝的工藝流程，減小了晶片的封裝體積，降低了封 裝成本；晶>1的電極暴露在封裝體外，提高了晶片的散 熱性能’此外，晶圓底部研磨降低了晶片的概底電阻， 貼片式的内部互聯使晶片的性能更加穩定可靠。 為了達到上述目的，本發明的技術方案是：具有晶圓尺 寸貼片的封裝方法，其特點是，包括： 099111678 提供一晶圓 表單編號A0101 所述晶圓具有晶圓頂部及晶圓底部，在所 第 5 頁/共 23 頁 0993160223-0 201135854 述晶圓頂部形成數個晶片，並且在所述晶圓頂部的晶片 之間》又有與晶片對應的凹槽區域，每個晶片的表面設有 數個晶片頂部電極接觸區； 提供-貼片，所賴片設有與晶圓上的各個晶片對應的 區域’在每個區域中，所述貼片具有與所述晶片頂部電 極接觸區㈣賴舰Μ肺，並且㈣㈣還具有 與貼片接觸區連接㈣片連筋，所賴片連筋向下成長 方體凸條； 將貼片接觸區與晶片頂部電極接觸區連接，同時將貼片 連筋設置在晶圓的凹槽區域内； 提供一塑封體塑封晶圓頂部、晶片及貼片。 上述的具有晶圓尺寸貼片的封+ — τ哀方法，其中，還包括減 薄晶圓底部直到晶圓底面盍設罟Α曰 四成叫/、叹置在晶圓的,凹槽區域内的 貼片連筋底面在同一平面。 還包括在 還包括切 至少一個 至少一個 上述的具有晶圓尺寸贴片的封裝方法，其中 晶圓底面製作底部電極接觸區。' 上述的具有晶圓尺寸貼片的封裝:方法其中 割整個塑封晶®，得到各個晶片的塑封體。 上述的具有晶圓尺寸貼片的封裝方法其中， 頂部電極接觸區成型分為若干個分區。 上述的具有晶圓尺寸貼片的封裝方法其中， 貼片接觸區成型分為若干個分區。 099111678 具有晶圓尺寸貼片的封裝方法，复 ，、甲，包括以下步驟： y 1:提供-晶圓’在晶圓上製作多個晶片，所述多個 晶片具有數個頂部電極接觸區及底部電極接觸區； 步驟2 :在晶圓上刻蝕多個凹槽區域； 表單編號Α0101 第6頁/共23頁 0993160223-0 201135854 步驟3:提供一貼片，所述貼片包括多個貼片接觸區及與 貼片接觸區連接的多個貼片連筋，將貼片接觸區與晶片 電極接觸區枯接，同時將貼片連筋設置在晶圓的凹槽區 域内； 步驟4 :塑封體模壓封裝晶圓頂部、晶片及貼片； 步驟5 :對晶圓底部進行減薄，製作晶片底部接觸區的電 極； v驟6 .對塑封多個晶片的整個塑封體進行切割，得到各 個晶片的塑封體。The structure is not stripped by high stress. The semiconductor swearing method 'places the semiconductor s on the substrate; connects the semiconductor element to the substrate in a flip chip connection; applies an adhesive along the edge of the bottom surface of the semiconductor wafer sealing structure, at the bottom edge of the semiconductor element and the substrate Forming at least one adhesive structure therebetween; and curing the adhesive structure, thereby further fixing the semiconductor component to the substrate. In the above-described prior art package, first, after the semiconductor element is diced on the wafer, each semiconductor element is placed on the substrate, and the semiconductor element electrode is led out through the lead, and then the semiconductor element is molded. At the beginning, the package is used to cut and package the wafer to the electrode of the component, and the i-sequence is numerous, and the individual package of each semiconductor component increases the package (four) product. The cost of the package increases. The electrodes are encapsulated in the package, so that the heat dissipation performance of the semiconductor is deteriorated. SUMMARY OF THE INVENTION The object of the present invention is to provide a seed crystal phase-encapsulation method. The package method uses a wafer-sized patch to pull out the top electrode of each wafer on the wafer, and then mold-packages the wafer size, and then The bottom electrode of the wafer wafer is exposed by the bottom grinding of the wafer, and finally the cutting is performed, which simplifies the packaging process, reduces the packaging volume of the wafer, and reduces the packaging cost; the electrode of the crystal > 1 is exposed outside the package, thereby improving The heat dissipation performance of the wafer 'In addition, the bottom grinding of the wafer reduces the basic resistance of the wafer, and the internal interconnection of the chip makes the performance of the wafer more stable and reliable. In order to achieve the above object, the technical solution of the present invention is: a package method having a wafer size patch, which comprises: 099111678 providing a wafer form number A0101, the wafer has a wafer top and a wafer bottom, Page 5 of 23 0993160223-0 201135854 A plurality of wafers are formed on the top of the wafer, and there is a groove area corresponding to the wafer between the wafers at the top of the wafer, and the surface of each wafer is provided with a number of a wafer top electrode contact region; providing a patch, the sheet being provided with a region corresponding to each wafer on the wafer 'in each region, the patch having a contact area with the wafer top electrode (four) Silicosis, and (4) (4) also has a connection with the patch contact area (four) piece of ribs, the ribs and ribs are downwardly grown to the square body ribs; the patch contact area is connected with the wafer top electrode contact area, and the patch is connected with the ribs In the recessed area of the wafer; a plastic encapsulated wafer top, wafer and patch are provided. The above-mentioned method for sealing a wafer with a wafer size patch, wherein the method further comprises thinning the bottom of the wafer until the bottom surface of the wafer is disposed at a thickness of four or less, in the groove region. The patch has a ribbed bottom surface on the same plane. Also included is a method of packaging including at least one of the above-described wafer-size patches, wherein the bottom surface of the wafer is formed with a bottom electrode contact region. The above package having a wafer size patch: a method in which the entire plastic crystal is cut to obtain a molded body of each wafer. In the above packaging method having a wafer size patch, the top electrode contact region is formed into a plurality of sections. In the above packaging method with a wafer size patch, the patch contact region is formed into a plurality of partitions. 099111678 A method for packaging a wafer size patch, a, A, comprising the steps of: y 1: providing - wafer 'making a plurality of wafers on a wafer, the plurality of wafers having a plurality of top electrode contact regions and Bottom electrode contact area; Step 2: Etching multiple groove areas on the wafer; Form No. 1010101 Page 6 of 23 0993160223-0 201135854 Step 3: Provide a patch, the patch includes multiple stickers a chip contact area and a plurality of patch ribs connected to the patch contact area, the patch contact area and the wafer electrode contact area are ablated, and the patch ribs are disposed in the groove area of the wafer; Step 4: The molded body is molded to encapsulate the top of the wafer, the wafer and the patch; Step 5: thinning the bottom of the wafer to form an electrode at the bottom contact area of the wafer; v. 6. Cutting the entire plastic body of the plurality of wafers to obtain each The molded body of the wafer.
上述的具有晶®尺相片的封裝方法，其巾，步驟5還包 括以下步驟： 步驟5. 1 :在晶圓底部進行金屬堆積； 步驟5· 2 :對晶圓底部進行掩膜刻蝕，從而保護晶圓底部 露出的晶片電極。The above-mentioned encapsulation method with a photo-size photo, the towel, step 5 further comprises the following steps: Step 5. 1: metal deposition at the bottom of the wafer; step 5·2: mask etching on the bottom of the wafer, thereby Protect the exposed wafer electrodes at the bottom of the wafer.
上述的具有晶圓尺寸貼片的封裝方法，其申，在步驟3中 ’所述貼片還包括貼片框架，所述貼片框架將貼片區分 為與晶圓上的每個晶片相對應的丨各個區域。 上述的具有晶圓尺寸貼片的封籍法，其中，在步驟^ ’還包括在每個晶片上電鍍形成多個晶片頂部電極接觸 區。 上述的具有晶®尺寸貼片的封裝方法，其中，在步則中 ，所述多個貼片接觸區與多個晶片電極接觸區對庫設置 ，多個貼片接觸區通過導電_材料與其對應的多個晶 片電極接觸祕接在-起，並通過貼片連筋延伸出晶片 頂部接觸區的電極。 099111678 上述的具有晶圓尺寸貼片的封裝方法 表單編號A0101 第7頁/共23頁 其中，在步驟6中 0993160223-0 201135854 ，減薄晶圓底部露出的晶片底部接觸區的電極與貼片連 筋的底面在同一平面上。 上述的具有晶圓尺寸貼片的封裝方法，其中，所述的晶 片為具有頂部接觸區及底部接觸區的功率半導體場效應 電晶體，所述晶片的底部接觸區的電極為漏極，所述晶 片的頂部接觸區的電極分別為源極及柵極，所述源極及 栅極都通過貼片連筋延伸出來，從而使晶片的源極、柵 極及漏極在同一平面上。 上述的具有晶圓尺寸貼片的封裝方法，其中，所述凹槽 區域將多個晶片劃分為各個晶片單元。 本發明具有晶圓尺寸贴片的封裝及其製作方法由於採用 上述技術方案，使之與現有技術相比，具有以下優點和 積極效果： 1、 本發明由於首先在晶圓上對各個晶片進行貼片，然後 進行封裝及晶圓上各個晶片的分割，簡化了工藝步驟， 節省了封裝材料，降低了封裝成本。 2、 本發明由於通過晶圓尺寸的貼片導電連接晶圓上各個 晶片的頂部電極，並通過設置在晶圓凹槽内的貼片連筋 引出晶片的頂部電極^使晶片的電極在晶片尺寸的面積 上共面，減小了晶片封裝的尺寸。 3、 本發明由於最後通過切割或研磨晶圓底部的方式暴露 晶片的電極，一方面，減小了晶圓襯底的厚度，降低了 晶片的襯底電阻，另一方面由於晶片的電極暴露在封裝 體外，提高了晶片的散熱性能。 【實施方式】 本發明提供一種具有晶圓尺寸貼片的封裝，包括一晶圓1 099111678 表單編號A0101 第8頁/共23頁 0993160223-0 [0004] 201135854 、一貼片2及一塑封體3。The above-described packaging method with a wafer size patch, in the step 3, the patch further includes a patch frame, the patch frame distinguishing the patch into each wafer on the wafer The various areas of the 。. The above-described seal method having a wafer size patch, wherein the step further comprises electroplating forming a plurality of wafer top electrode contact regions on each of the wafers. The above package method with a wafer size patch, wherein, in the step, the plurality of patch contact regions and the plurality of wafer electrode contact regions are disposed in a library, and the plurality of patch contact regions are corresponding to the conductive material The plurality of wafer electrode contacts are in contact with each other and extend through the patch ribs out of the electrode at the top contact area of the wafer. 099111678 The above-mentioned package method with wafer size patch Form No. A0101 Page 7 of 23, in step 6 0993160223-0 201135854, thinning the bottom of the wafer exposed at the bottom of the wafer contact area electrode and patch The bottom surfaces of the ribs are on the same plane. The above package method with a wafer size patch, wherein the wafer is a power semiconductor field effect transistor having a top contact region and a bottom contact region, and an electrode of a bottom contact region of the wafer is a drain, The electrodes in the top contact area of the wafer are respectively a source and a gate, and the source and the gate are extended by the patch ribs so that the source, the gate and the drain of the wafer are on the same plane. The above packaging method having a wafer size patch, wherein the groove region divides a plurality of wafers into individual wafer units. The package having the wafer size patch of the present invention and the manufacturing method thereof have the following advantages and positive effects compared with the prior art by adopting the above technical solutions: 1. The present invention firstly applies the respective wafers on the wafer. The film is then packaged and the wafers are divided on the wafer, which simplifies the process steps, saves packaging materials and reduces packaging costs. 2. The present invention electrically connects the top electrode of each wafer on the wafer through a wafer-sized patch, and extracts the top electrode of the wafer through the patch ribs disposed in the groove of the wafer to make the electrode of the wafer in the wafer size. The area is coplanar, reducing the size of the chip package. 3. The present invention exposes the electrodes of the wafer by cutting or grinding the bottom of the wafer. On the one hand, the thickness of the wafer substrate is reduced, the substrate resistance of the wafer is reduced, and on the other hand, the electrodes of the wafer are exposed. The outer surface of the package improves the heat dissipation performance of the wafer. [Embodiment] The present invention provides a package having a wafer size patch, comprising a wafer 1 099111678 Form No. A0101 Page 8 / Total 23 Page 0993160223-0 [0004] 201135854 , a patch 2 and a plastic package 3 .
如第1A、1 β圖所示分別為晶圓的侧視圖及晶圓的頂部正 視圖，晶圓1具有晶圓頂部11及晶圓底部1 2。在晶圓頂部 11製作出數個晶片111，並且晶圓頂部J i的晶片〗i i之間 设有凹槽區域11 2，每一個晶片111對應一個凹槽區域 112，相鄰凹槽區域之間可相隔斷，也可延伸連接。在一 個優選的實施例中，凹槽區域u2在晶片lu之間的縱橫 兩個方向將數個晶片111劃分為各個晶片單元。在另一個 優選的實施例中，凹槽區域112只設在一個方向（未在圖 中顯不）。每個晶片的上表面戮有數個晶片頂部電極接觸 區1111和1112。當頂部電極释觸區面積較大時，還可將 一個頂部電極接觸區成型分為;若干個分區，如第1A、iB 圖所示的源極接觸區1112。優選的晶片的底部可設有晶 片底部電極，也可不設底部電極。在一個優選的實施例 中，晶片111為具有頂部電極及底部電極的功率半導體場 效應電晶體，即晶片頂部電極接觸醛1 1 1 1為半導體場效 應電晶體的柵極，晶片電挺接觸區1112為半導體場效應 電aa體的源極。在另一個優選.的實施例中，晶片1 1 1的所 有電極都位於晶片的頂部。 如第2A及2B圖所示為一貼片2，貼片2包括貼片框架21、 與貼片框架21連接的多個貼片接觸區2 2及與貼片接觸區 連接的多個貼片連筋23。貼片框架21將貼片2區分為與晶 圓上的每個晶片相對應的各個區域。如第2 B圖所示，貼 片連筋23成長方形凸條’並且貼片連筋23具有貼片連筋 底平面231 ’該貼片連筋底平面231與貼片接觸區所在的 平面平行’並且每個貼片連筋23的貼片連筋底平面231在 099111678 0993160223-0 表單編號A0101 第g頁/共23頁 201135854 同一平面。當貼片接觸區面積較大時，還可將一個貼片 接觸區成型分為若干個分區，每個分區可連接到同一貼 片連筋，如第2A及2B圖所示。在每個區域中，如第3八及 3B圖所示，多個貼片接觸區22與多個晶片電極接觸區 1111、1112通過導電材料對應粘接設置，所用的導電材 料如銀漿、錫焊膏等。多個貼片連筋23與貼片電極接觸 區1111、1112對應連接，並且設置在凹槽區域112内。 在一個優選的實施例中，貼片所需連接的晶片為具有頂 部電極及底部電極的功率半導體場效應電晶體，晶片電 極接觸區1111為半導體場效應電晶體的栅極，晶片電極 接觸區1112為半導體場效應電晶體的源極。由於貼片連 筋23與貼片電極接觸區22連接，貼片電極接觸區22與晶 片的栅極及源極連接，因而貼片連筋23分別引出晶片的 頂部接觸區的栅極及源極，即晶片的柵極及源極暴露在 與貼片連筋23底部的同一個平面上，並設置在凹槽區域 112 内。 如第4圖所示，一塑封體3塑封晶圓}頂部、晶片及貼片2 ，塑封體填充貼片2與晶片及晶圓頂部之間的空隙並進 行晶圓模壓，從而形成晶圓尺寸的整個封裝體。由於實 際應用中需要得到單個封裝晶片，還需對整個封襞體進 行晶圓底部研磨露出晶片電極以及封裝體的切割，如第5 、6、7及8圖所示，具體將在下述製作方法中詳細描述。 本發明提供一種具有晶圓尺寸貼片封裝的製作方法，靖 參見第1圖至第9圖所示，包括以下步驟： 099111678 提供一晶圓1，在晶圓！上製作多個晶片ln，在—個優選 實施例中，多個晶片111為具有頂部電極及底部電極的功 表單編號A0101 第10頁/共23頁 0993160223-0 201135854 率半導體％效應電晶體，晶片的底部電極為漏極，晶片 的頂。p電極分別為源極及柵極。首先在晶圓丨上刻蚀多個 凹槽區域112，每-個晶片111對應-個凹槽區域112。As shown in Figs. 1A and 1β, respectively, a side view of the wafer and a top view of the wafer, the wafer 1 having a wafer top 11 and a wafer bottom 12 . A plurality of wafers 111 are formed on the top 11 of the wafer, and a groove region 11 2 is disposed between the wafers ii of the wafer tops J i , and each of the wafers 111 corresponds to a groove region 112 between adjacent groove regions Can be separated or extended. In a preferred embodiment, the recessed regions u2 divide the plurality of wafers 111 into individual wafer units in both the longitudinal and transverse directions between the wafers lu. In another preferred embodiment, the recessed regions 112 are disposed in only one direction (not shown in the figures). The upper surface of each wafer has a plurality of wafer top electrode contact regions 1111 and 1112. When the area of the top electrode release area is large, a top electrode contact area can be formed into a plurality of partitions, such as the source contact area 1112 shown in Figs. 1A and 1B. The bottom of the preferred wafer may be provided with a wafer bottom electrode or no bottom electrode. In a preferred embodiment, the wafer 111 is a power semiconductor field effect transistor having a top electrode and a bottom electrode, that is, the top electrode of the wafer contacts the aldehyde 1 1 1 1 as the gate of the semiconductor field effect transistor, and the wafer is electrically contacted. 1112 is the source of the semiconductor field effect electrical aa body. In another preferred embodiment, all of the electrodes of wafer 11 are located at the top of the wafer. As shown in FIGS. 2A and 2B, a patch 2 includes a patch frame 21, a plurality of patch contact regions 2 2 connected to the patch frame 21, and a plurality of patches connected to the patch contact regions. Connected to the ribs 23. The patch frame 21 divides the patch 2 into respective regions corresponding to each wafer on the wafer. As shown in FIG. 2B, the patch ribs 23 are formed into rectangular ridges 'and the patch ribs 23 have a patch rib bottom plane 231 'the patch rib bottom plane 231 is parallel to the plane of the patch contact area 'And each patch rib 23 patch rib bottom plane 231 at 099111678 0993160223-0 Form No. A0101 page g / 23 pages 201135854 the same plane. When the contact area of the patch is large, a patch contact area can be formed into a plurality of partitions, and each partition can be connected to the same patch, as shown in Figures 2A and 2B. In each of the regions, as shown in FIGS. 3 and 3B, a plurality of patch contact regions 22 and a plurality of wafer electrode contact regions 1111 and 1112 are bonded by a conductive material, and a conductive material such as silver paste or tin is used. Solder paste, etc. A plurality of patch ribs 23 are connected to the patch electrode contact regions 1111, 1112 and are disposed in the recess region 112. In a preferred embodiment, the wafer to be connected to the patch is a power semiconductor field effect transistor having a top electrode and a bottom electrode, the wafer electrode contact region 1111 is the gate of the semiconductor field effect transistor, and the wafer electrode contact region 1112 It is the source of the semiconductor field effect transistor. Since the patch rib 23 is connected to the patch electrode contact region 22, the patch electrode contact region 22 is connected to the gate and the source of the wafer, so that the patch ribs 23 respectively lead to the gate and source of the top contact region of the wafer. That is, the gate and source of the wafer are exposed on the same plane as the bottom of the patch rib 23, and are disposed in the recessed area 112. As shown in Fig. 4, a plastic package 3 is used to mold the wafer} top, wafer and patch 2, and the plastic body fills the gap between the chip 2 and the top of the wafer and the wafer and is subjected to wafer molding to form a wafer size. The entire package. Since a single package wafer is required in practical applications, the entire package body needs to be polished at the bottom of the wafer to expose the wafer electrode and the package body, as shown in Figures 5, 6, 7, and 8, which will be specifically described below. Described in detail. The invention provides a method for fabricating a wafer size patch package, as shown in Figures 1 to 9, comprising the following steps: 099111678 Providing a wafer 1 on a wafer! A plurality of wafers ln are fabricated thereon. In a preferred embodiment, the plurality of wafers 111 are power sheet numbers having a top electrode and a bottom electrode. A0101 Page 10 / Total 23 pages 0993160223-0 201135854 Rate semiconductor % effect transistor, wafer The bottom electrode is the drain, the top of the wafer. The p electrodes are a source and a gate, respectively. First, a plurality of groove regions 112 are etched on the wafer stack, and each wafer 111 corresponds to a groove region 112.
099111678 在個優相實施例中，所述凹槽區域112在晶片⑴之 間的縱h兩個方向延伸連接將多個晶片i i i劃分為各個晶 片然後，在每個晶片的晶片頂部接觸區上進行Ni/Au電 鍛，電鍍出多個W電極接觸區1111、1112，並將觸區 面積較大的頂部電極接觸區成型分為若干個分區。當然 也可以在職多個凹槽區域112之前就進行Ni/Au電鍛， 甚至晶圓1本身提供時就帶有晶片電桎雜區11 11、 1112而省略這一步驟。接著，在多個晶片電極接觸區 1111 1112上塗覆導電材料，如：级漿，焊錫膏等。然 後提供貼片2，貼片2包括貼片框架21、多個貼片接觸 區22及與貼片接觸區22連接的多個貼片連筋以，貼片框 架21方便貼片與晶片的對準，該貼片框架21將貼片區分 為與晶圓上的每個晶片相對惠的各個區域。反過來也可 將導電材料預先塗覆或印製在貼片接觸區22上。在各個 區域内，將貼片接觸區2 2與表面塗看導電材料的晶片電 極接觸區1111、1112難，同時將貼片連筋23成長方形 凸條設置在凹槽區域112内。貼片連筋23的底平面與貼片 接觸區所在的平面平行。由於貼片連筋23與貼片接觸區 22導電連接，而貼片接觸區22與晶片電極接觸區、 1112粘接，因此貼片連筋23將晶片的電極接觸區lln、 1112延伸至同一個平面並設置在凹槽區域112内。接著在 晶圓頂部11塑封晶片及貼片，進行晶圓模壓封裝。塑封 之後，對晶圓底部12進行減薄，例如研磨，或進行切割 0993160223-0 表單編號A0101 第11頁/共23頁 201135854 ’直到晶圓底部12露出的晶片底部接觸區的電極111 3與 貼片連筋23的底面在同一平面上。對晶圓底部的研磨或 切割一方面露出了晶片底部的電極；另一方面得到了如 〇. 15min、〇. 1龍甚至更薄的晶片，因此減小了襯底電阻 ’從而獲得更好的產品性能。在一個優選的實施例中， 由於晶片為具有頂部接觸區及底部接觸區的功率半導體 場效應電晶體’晶片的底部接觸區的電極η丨3為漏極， 而貼片連筋23的底面設有延伸出來的柵極及源極，因此 ，该晶片的源極、栅極及漏極在晶圓底部的同一個平面 内。然後在在晶圓底部12進行金屬堆積，並對晶圓底部 進行掩膜刻蝕，從而保護晶圓底部露出的晶片底部接觸 區的電極。當進行封裝的晶片所有電.極都位於晶片的頂 部時，製作晶片底部接觸區的電極步驟可以省略。最後 ，對塑封多個晶片的整個塑封體進行切割，得到各個晶 片的塑封體，每個晶片的塑封體底面分別設有源極、栅 極及漏極，該電極可連接至基板，通過基板散熱增強 了晶片的散熱性能。 本發明具有晶®尺寸貼片難在晶圓上預留出溝槽區域 用以區分各個晶片’通過晶圓尺寸的貼片進行互聯，並 將晶片的電極通過貼片延伸至溝槽内，先整體封裝再進 行單個晶片的封裝切割，其簡化了卫藝流程，節省了封 裝材料，並且由於整個封裝體内的各個晶片封裝之間的 空間更為緊密，從而減小了單個晶片封裝的體積。 當然’必須_到’上述介紹是錢本發明優選實施例 的說明，只要不偏離隨後所附申請專利範圍所顯示的精 神和範圍，本發明還存在著許多修改。 月 表單編號Α0101 第12頁/共23頁 °993160223-0 201135854 本發明決不是僅局限於上述說明或關所顯示的細節和 方法。本發明能夠擁有其他的實施例，並可採用多種方 式予以實施。另外，大家還必須認識到，這裏所使用的 措辭和術語以及文摘只是為了實現介紹的目的，決不是 僅僅局限於此。 Ο [0005] Ο 正因為如此，本領域的技術人員將會理解，本發明所基 於的觀點可隨時用來作為實施本發明的幾種目標而設計 其他結構、方法和系統。所以，至關重要的是所附的 申請專利範圍將被視為包括了所有這些等價的建構，只 要它們不偏離本發明的精神和範圍。 【圖式簡單說明】 參考所附附圖，以更加充分的描述本潑明的實施例。然 而，所附附圖僅用於說明和闡述，並不構成對本發明範 圍的限制》 第1Α圖為本發明晶圓結構的側視圖。 .； ..... ：, 第1Β圖為本發明晶圓結構的正面視圖。 第2Α圖為本發明貼片結構的上表面視圖。 第2Β圖為本發明貼片結構的下袅面視圖。 第3Α圖為本發明中將貼片設置在晶圓頂部的上表面視圖 第3Β圖為本發明中將貼片設置在晶圓頂部的側視圖。 第4圖為本發明塑封晶圓頂部的晶片及貼片的側視圖。 第5圖為本發明經晶圓底部研磨後的塑封體的側視圖。 第6圖為本發明經晶圓底部研磨後的塑封體下表面視圖。 第7圖為本發明經切割後得到的單個晶片的封裝結構上表 面視圖。 099111678 表單編號Α0101 第13頁/共23頁 0993160223-0 201135854 第8圖為本發明經切割後得到的單個晶片的封裝結構下表 面視圖。 第9圖為本發明製作方法的流程圖。 【主要元件符號說明】 [0006] 1 :晶圓 2 :貼片 3 :塑封體 II ·晶圓頂部 1 2 :晶圓底部 21 :貼片框架 22 :貼片接觸區 2 3 :貼片連筋 III :晶片 112 :凹槽區域 231 :貼片連筋底平面 1111 :晶片頂部電極接觸區 1112 :晶片電極接觸區 111 3 :電極 099111678 表單編號A0101 第14頁/共23頁 0993160223-0099111678 In a preferred embodiment, the recessed regions 112 are extended in two directions between the wafers (1) to divide the plurality of wafers iii into individual wafers and then on the wafer top contact area of each wafer. Ni/Au electric forging, electroplating a plurality of W electrode contact regions 1111, 1112, and forming a top electrode contact region having a large contact area into a plurality of sections. It is of course also possible to carry out Ni/Au electric forging before the plurality of groove regions 112 are employed, even if the wafer 1 itself is provided with the wafer electric doping regions 11 11 , 1112 and this step is omitted. Next, a plurality of wafer electrode contact regions 1111 to 1112 are coated with a conductive material such as a grade paste, a solder paste or the like. Then, a patch 2 is provided. The patch 2 includes a patch frame 21, a plurality of patch contact regions 22, and a plurality of patch ribs connected to the patch contact regions 22, and the patch frame 21 facilitates the pair of patches and wafers. Precisely, the patch frame 21 distinguishes the patches into regions that are comparable to each wafer on the wafer. Conversely, the conductive material may be pre-coated or printed on the patch contact area 22. In each of the regions, the patch contact region 2 2 is difficult to apply to the wafer electrode contact regions 1111, 1112 of the conductive material, and the patch ribs 23 are formed into rectangular ridges in the recess region 112. The bottom plane of the patch tie 23 is parallel to the plane in which the patch contact area is located. Since the patch ribs 23 are electrically connected to the patch contact regions 22, and the patch contact regions 22 are bonded to the wafer electrode contact regions, 1112, the patch ribs 23 extend the electrode contact regions 11n, 1112 of the wafer to the same The plane is disposed within the recessed area 112. The wafer and the chip are then molded on the top 11 of the wafer for wafer molding. After molding, the bottom 12 of the wafer is thinned, for example, ground, or cut. 0993160223-0 Form No. A0101 Page 11 of 23 201135854 'The electrode 111 3 with the bottom contact area of the wafer exposed at the bottom of the wafer 12 The bottom surfaces of the sheet ribs 23 are on the same plane. Grinding or cutting the bottom of the wafer reveals the electrode at the bottom of the wafer on the one hand; on the other hand, a wafer such as 〇15min, 〇.1 dragon or even thinner is obtained, thus reducing the substrate resistance' and thus obtaining better Product performance. In a preferred embodiment, since the wafer is the bottom contact region of the power semiconductor field effect transistor 'wafer having the top contact region and the bottom contact region, the electrode η 丨 3 is the drain, and the bottom surface of the patch rib 23 is provided. There are extended gates and sources, so the source, gate and drain of the wafer are in the same plane at the bottom of the wafer. Metal deposition is then performed at the bottom 12 of the wafer, and a mask etch is performed on the bottom of the wafer to protect the electrodes at the bottom contact area of the wafer exposed at the bottom of the wafer. When all of the electrodes of the packaged wafer are located at the top of the wafer, the step of fabricating the electrode at the bottom contact area of the wafer may be omitted. Finally, the entire plastic body of the plurality of wafers is cut to obtain a molded body of each of the wafers, and the bottom surface of the molded body of each of the wafers is respectively provided with a source, a gate and a drain, and the electrode can be connected to the substrate and radiated through the substrate. The heat dissipation performance of the wafer is enhanced. The present invention has a Crystal® size patch which is difficult to reserve a trench region on the wafer for distinguishing the individual wafers from being interconnected by wafer size patches and extending the electrodes of the wafer through the patches into the trenches. The overall package then performs a package cut of a single wafer, which simplifies the process flow, saves packaging material, and reduces the size of a single wafer package due to the tighter space between individual wafer packages throughout the package. Of course, the above description is a description of the preferred embodiment of the present invention, and many modifications are possible in the present invention without departing from the spirit and scope of the appended claims. Month Form No. 1010101 Page 12 of 23 °993160223-0 201135854 The present invention is by no means limited to the details and methods shown above. The invention is capable of other embodiments and of various embodiments. In addition, you must also understand that the words and terms used herein and the abstracts are for the purpose of illustration only and are by no means limited. 0005 [0005] As such, those skilled in the art will appreciate that the present invention may be readily utilized to design other structures, methods, and systems. Therefore, it is essential that the scope of the appended claims be construed as including all such equivalents, and that they do not depart from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS The embodiments of the present invention will be described more fully with reference to the accompanying drawings. The drawings are for illustration and illustration only and are not intended to be limiting of the scope of the invention. FIG. 1 is a side view of the wafer structure of the present invention. . . . . : The first diagram is a front view of the wafer structure of the present invention. Figure 2 is a top plan view of the patch structure of the present invention. Figure 2 is a bottom plan view of the patch structure of the present invention. Fig. 3 is a view showing the upper surface of the wafer at the top of the wafer in the present invention. Fig. 3 is a side view showing the patch at the top of the wafer in the present invention. Figure 4 is a side elevational view of the wafer and patch on top of the plastic wafer of the present invention. Figure 5 is a side view of the molded body after the bottom of the wafer is ground according to the present invention. Figure 6 is a view of the lower surface of the molded body after the bottom of the wafer is ground according to the present invention. Figure 7 is a top plan view showing the package structure of a single wafer obtained after cutting according to the present invention. 099111678 Form No. Α0101 Page 13 of 23 0993160223-0 201135854 Fig. 8 is a bottom view of the package structure of a single wafer obtained after cutting according to the present invention. Figure 9 is a flow chart of the manufacturing method of the present invention. [Main component symbol description] [0006] 1 : Wafer 2 : Patch 3 : Plastic package II · Wafer top 1 2 : Wafer bottom 21 : Patch frame 22 : Patch contact area 2 3 : Patch connection III: Wafer 112: Groove area 231: Patch rib bottom plane 1111: Wafer top electrode contact area 1112: Wafer electrode contact area 111 3: Electrode 099111678 Form No. A0101 Page 14 of 23 0993160223-0