CN213936190U - Package structure for stacked wafers - Google Patents

Abstract

The utility model relates to a pile up packaging structure of wafer belongs to semiconductor chip packaging technology field. The wafer stacking body C2, the wafer A1 and the electrical connection layer (150) are arranged above the wafer A1 and connected through the electrical connection layer (150), the wafer stacking body C1 comprises a plurality of layers of functional wafers, the sizes of the wafers are gradually reduced from bottom to top, stepped side walls are formed on the four sides of the wafers, a dielectric layer III (300) is coated on the front face of the wafer stacking body C2 and the stepped side walls of the wafer stacking body C2, a dielectric layer III opening (301) is formed, a metal seed layer (310) and a metal bump (360) are arranged in the dielectric layer III opening (301), and the metal bump (360) is connected with a metal interconnection layer (120) of an adjacent wafer through the metal seed layer (310). The utility model provides a packaging structure of multilayer pile up wafer and manufacturing method thereof.

Description

Package structure for stacked wafers

Technical Field

The utility model relates to a pile up packaging structure of wafer belongs to semiconductor chip packaging technology field.

Background

With the development of the semiconductor industry, the performance of electronic products is required to be improved. With the rapid rise of chip manufacturing cost, the approach of improving product performance begins to incline from the micro-scale of chip line nodes to the packaging field.

To reduce the area and power consumption of the package while meeting the trend of low cost and full integration of integrated circuits, more packages are required to stack chips rather than traditional tiling, i.e., to let the chips "stand up" rather than "spread apart". The stacking of the chips can integrate various types of chips such as logic chips, memory chips, RF chips, and the like to form heterogeneous core particles (heterograins), thereby significantly reducing power consumption, saving space, shortening signal exchange time, and meeting the development trend of future packaging. A typical example is the Fiji GPU display core chip of the ultra wei semiconductor corporation (AMD), and the package is formed by stacking a high bandwidth video memory (HBM) and a logic chip and then performing 2.5D package with the GPU chip, but there is a clear route in the industry to stack all the chips to form a true 3D package.

Wafer Level Packaging (WLP) is a typical low cost, high efficiency packaging approach. For a metal bump layout area with a higher metal bump or a metal bump layout area with a higher density, there is a higher risk of debonding failure, there are more heterogeneous integration layers, and once failure may cause a larger yield loss.

Therefore, the growth of the pins of the stacked wafer can be realized by utilizing the traditional wafer-level bump production line, and the method is low in cost and can ensure the yield output. However, the edge portion of the multi-layer stacked wafer has a large profile variation, which causes difficulty and insufficient feasibility in manufacturing the conventional WLP production line.

Disclosure of Invention

Therefore, there is a need to provide a new package structure, which restrains the edge and thickness of the stacked wafer to form a specific shape during the manufacturing process, and ensures that the edge shape does not affect the bump manufacturing process during the bump manufacturing process.

The purpose of the utility model is realized like this:

the utility model relates to a stacked wafer packaging structure, which comprises a wafer stacked body C2, a bearing wafer A1 and an electrical connection layer, wherein the wafer stacked body C2 is arranged above the bearing wafer A1 and is connected with the bearing wafer A1 through the electrical connection layer, the wafer stacked body C1 comprises a plurality of layers of functional wafers,

the wafer comprises a silicon substrate, a through silicon via, a dielectric layer I and a metal interconnection layer, wherein the through silicon via penetrates through the silicon substrate from top to bottom, the dielectric layer I is arranged above the silicon substrate, and the metal interconnection layer is exposed through an opening of the dielectric layer I;

from bottom to top, the sizes of the wafers are reduced layer by layer, a step-shaped side wall is formed on the periphery of the wafers, a bearing wafer A1 is arranged above the bearing wafer, the front surface of the wafer stacking body C2 is coated with a dielectric layer III and a dielectric layer III opening is formed, the dielectric layer III is coated on the step-shaped side wall of the wafer stacking body C2 downwards, a metal seed layer and a metal bump are arranged in the dielectric layer III opening, and the metal bump is connected with a metal interconnection layer of an adjacent wafer through the metal seed layer.

Further, the outer circle dimension distance difference Δ 1 between the wafer B1 and the wafer a1 is not more than 2.5 mm, and the outer circle dimension distance difference Δ 1 between the wafer B1 and the wafer a1 is minimal to ensure that the metal contacts 401 of the electroplating fixture are effectively and electrically interconnected.

Further, the ratio of the outer ring size distance difference delta 2 between the wafer B2 and the wafer B1 to the thickness t2 of the wafer B2 is not lower than 2: 1.

Further, the ratio of the outer ring size distance difference delta 3 between the wafer B3 and the wafer B2 to the thickness t3 of the wafer B3 is not lower than 2: 1.

Further, the ratio of the outer ring size distance difference delta 4 between the wafer B4 and the wafer B3 to the thickness t4 of the wafer B4 is not lower than 2: 1.

Advantageous effects

1. In the manufacturing process, defining the position difference of the upper wafer and the lower wafer and the ratio of the thickness of the single-layer wafer to the thickness of the photoresist to ensure the coverage of the photoresist;

2. and the diameter difference between the upper wafer and the lower wafer is defined on the premise that the centers of the second layer of wafer and the bottom layer of wafer are overlapped, so that the position difference of the edge is formed, and the sealing performance and the effectiveness of the electrical interconnection of the contacts of the electroplating clamp are ensured.

Drawings

Fig. 1 is a schematic cross-sectional view of a stacked wafer package structure according to the present invention;

FIG. 2 is an enlarged, fragmentary, schematic cross-sectional view of FIG. 1;

FIGS. 3A to 3R are schematic cross-sectional views illustrating a packaging method of a stacked wafer package structure according to the present invention;

in the figure:

through-silicon-via 101

Dielectric layer I110

Conductive layer 120

Electrical connection layer 150

Bonding pad 151

Carrier 200

Bonding layer 201

Wafer A1

Wafer B1

Wafer B2

Wafer B3

Wafer B4

Dielectric layer III 300

Dielectric III opening 301

Metal seed layer 310

Photoresist layer 320

Photoresist layer opening 323

Anti-seepage ring 304

Metal bump 360

Plating jig metal contact 401

The plating jig seals layer 402.

Detailed Description

The following describes in detail embodiments of the present invention with reference to the accompanying drawings.

The utility model relates to a stacked wafer's packaging structure, as shown in FIG. 1 and FIG. 2, it includes wafer stack C2, wafer A1, electrical connection layer 150, is equipped with pad 151 in the electrical connection layer 150. Wafer a1 carries wafer stack C2.

The wafer stack C2 is disposed above the carrier wafer a1 and connected by the electrical connection layer 150, and the wafer stack C1 includes several layers of functional wafers, as shown in fig. 1, which is illustrated by wafer B1, wafer B2, wafer B3, and wafer B4.

Each functional wafer comprises a silicon substrate 100, a through silicon via 101, a dielectric layer I110 and a metal interconnection layer 120, wherein the through silicon via 101 penetrates through the silicon substrate 100 from top to bottom, the dielectric layer I110 is arranged above the silicon substrate 100, and a top layer 121 of the metal interconnection layer 120 is exposed through an opening of the dielectric layer I110;

from below, the wafer size of wafer stack C2 decreases from top to bottom, with a stepped sidewall formed around the perimeter, and above carrier wafer a1, the front side of wafer stack C2 is coated with dielectric layer iii 300 and forms dielectric layer iii opening 301, and dielectric layer iii 300 coats the stepped sidewall of wafer stack C2 downward, as shown in fig. 1. A metal seed layer 310 and a metal bump 360 are arranged in the dielectric layer III opening 301, and the metal bump 360 is connected with the metal interconnection layer 120 of the adjacent wafer through the metal seed layer 310.

Specifically, the outer ring dimension spacing difference Δ 1 between the wafer B1 and the wafer a1 is not greater than 2.5 mm, the outer ring dimension spacing difference Δ 1 between the wafer B1 and the wafer a1 is the smallest, and effective electrical interconnection of the metal contacts 401 of the electroplating fixture is guaranteed, the ratio of the outer ring dimension spacing difference Δ 2 between the wafer B2 and the wafer B1 to the thickness t2 of the wafer B2 is not lower than 2:1, the ratio of the outer ring dimension spacing difference Δ 3 between the wafer B3 and the wafer B2 to the thickness t3 of the wafer B3 is not lower than 2:1, and the ratio of the outer ring dimension spacing difference Δ 4 between the wafer B4 and the wafer B3 to the thickness t4 of the wafer B4 is not lower than 2: 1.

Specifically, the ratio of the sum of the lengths of the trimmed edge of the wafer B1, the wafer B2, the wafer B3 and the wafer B4 from the edge of the wafer a1 to the total thickness of the wafers B1, B2, B3 and B4 is not less than 2: 1. The length of the trimmed edge of wafer B1, wafer B2, wafer B3, and wafer B4 from the edge of wafer a1 is no more than 2.5 mm and the minimum is to ensure effective electrical interconnection of the plating jig metal contacts 401.

The utility model relates to a packaging method of packaging structure of stacked wafers, which is schematically illustrated in FIGS. 3A to 3P and schematically illustrated by wafer A1, wafer B1, wafer B2, wafer B3 and wafer B4. The process comprises the following steps:

step one, referring to fig. 3A, providing a wafer a1, a wafer B1, a wafer B2, a wafer B3, a wafer B4, a wafer B1, a wafer B2, a wafer B3, and a wafer B4, completing a through silicon via 101, a dielectric layer i 110, and a metal interconnection layer 120 on a silicon substrate 100, depositing metal inside the through silicon via 101, and connecting the through silicon via to the metal interconnection layer 120, exposing the dielectric layer i 110 from a top layer 121 of the metal interconnection layer 120, wherein the wafer B1 is a wafer on a most basic layer of a package, and is interconnected with other wafers in the future, and the wafer B4 is a wafer on which a metal bump 360 is finally grown.

Step two, referring to fig. 3B and fig. 3C, trimming the edges of wafer B1, wafer B2, wafer B3 and wafer B4, after the trimming length, wafer B1 > wafer B2 > wafer B3 > wafer B4 (the thickness of each wafer includes the thickness of the top layer of the metal interconnection layer), as shown in fig. 3B, defining: the difference between the outer circle dimension spacing of the wafer B1 and the wafer a1 is Δ 1, the difference between the outer circle dimension spacing of the wafer B2 and the wafer B1 is Δ 2, the difference between the outer circle dimension spacing of the wafer B3 and the wafer B2 is Δ 3, the difference between the outer circle dimension spacing of the wafer B4 and the wafer B3 is Δ 4, and the trimming length is defined as follows: the outer circle dimension spacing difference delta 1 between the wafer B1 and the wafer A1 is not more than 2.5 mm, the outer circle dimension spacing difference delta 1 between the wafer B1 and the wafer A1 is minimum, and the ratio of the outer circle dimension spacing difference delta 1 between the wafer B1 and the wafer A1 to the thickness t1 of the wafer B1 is not less than 2: 1. The plating jig metal contact 401 is pressed on the metal seed layer 310 to conduct electricity, and the plating jig sealing layer 402 abuts against the sealing ring to prevent the plating solution from permeating.

As shown in fig. 3C, the ratio of the outer circle dimension spacing difference Δ 2 between the wafer B2 and the wafer B1 to the thickness t2 of the wafer B2 itself is not less than 2:1, correspondingly, the ratio of the outer circle dimension spacing difference Δ 3 between the wafer B3 and the wafer B2 to the thickness t3 of the wafer B3 itself is not less than 2:1, and the ratio of the outer circle dimension spacing difference Δ 4 between the wafer B4 and the wafer B3 to the thickness t4 of the wafer B4 itself is not less than 2: 1.

Step three, referring to fig. 3D, providing a carrier 200, and bonding the upper surface of the wafer B1 with the carrier 200 through an adhesive 201;

step four, referring to fig. 3E, the silicon substrate 100 of the wafer B1 is thinned through a thinning process such as mechanical grinding or chemical etching, so as to expose the upper surface of the through-silicon via 101. The thinned wafer B1 edge becomes a full wafer with a reduced diameter due to the trimming process in step one.

Step five, referring to fig. 3F, the wafer B1 forms a dielectric layer 130 on the through-silicon via 101 by a coating or chemical deposition process and forms a dielectric layer opening 131, wherein the dielectric layer opening 131 exposes the upper surface of the through-silicon via 101. The dielectric layer i 110 includes polyimide, a novolac-based organic material, but it is also possible to use an inorganic material such as silicon oxide or silicon nitride.

Sixthly, referring to fig. 3G, a conductive layer 120 is formed in the dielectric layer opening 131 through one or a combination of evaporation, electroplating or chemical plating, the conductive layer 120 is connected to the through-silicon-via 101, and the conductive layer 120 includes common aluminum, copper, tin, nickel or noble metal, so as to be subsequently interconnected with the wafer B2;

seventhly, referring to fig. 3H, the wafer B1 is interconnected with the wafer B2, and the top layer of the metal interconnection layer of the wafer B2 is connected with the conductive layer 120 of the wafer B1; referring to fig. 3I, the steps are repeated, a wafer B3 is stacked with a wafer B2, a wafer B4 is stacked with a wafer B3, layer-by-layer interconnection is completed, a wafer stack C1 is formed, stepped sidewalls are formed around the wafer stack C1, the same thinning process is performed on the wafer B2, the wafer B3 and the wafer B4, respective dielectric layers are formed by a coating or chemical deposition process, and respective conductive layers are formed finally;

step eight, referring to fig. 3J, after the required number of stacked layers is met, debonding and removing the carrier plate 200;

step nine, referring to fig. 3K, bonding the wafer B1 of the wafer stack C1 and the wafer a1 at the bottom layer face to face, that is, the top layer 121 of the protruding metal interconnection layer 120 of the wafer B1 and the pad 151 (pad) of the wafer a1 at the bottom layer are interconnected to form a wafer stack C2, and after the trimming length, the wafer a1 is larger than the wafer B1 larger than the wafer B2 larger than the wafer B3 larger than the wafer B4, and the periphery of the wafer stack C2 forms a stepped side wall; because the thickness of wafer stack C2 may exceed the actual production capacity of the wafer packaging line, the backside of wafer a1 is also ground down to meet the tool operation thickness limitation;

step ten, referring to fig. 3L, dielectric layer iii 300 is coated on the front surface and the stepped sidewalls of wafer stack C2, dielectric layer iii 300 covers the front surface of wafer B4 and the stepped sidewalls of wafer stack C2, and dielectric layer opening 301 exposes the top layer of the metal interconnect layer of wafer B4. Because the glue layer of the dielectric layer iii 300 is very thin, the step-shaped sidewall is difficult to completely cover in practical operation.

Step eleven, referring to fig. 3M, forming a metal seed layer 310 on the front surface of the wafer stack C2 and the stepped side walls around the front surface by using a magnetron sputtering or evaporation method, and simultaneously covering the metal seed layer 310 on the top layer of the metal interconnection layer of B4;

step twelve, referring to fig. 3N, continuing to coat the photoresist on the metal seed layer 310, wherein the setting of the thickness T of the photoresist layer 320 is a key factor. Generally, the thickness T of the photoresist layer 320 needs to be not less than 50% of the thickness of the thickest wafer among the wafers B1, B2, B3 and B4, i.e., T ≧ 0.5 max { wafer B1, B2, B3 and B4 };

referring to fig. 3N, in the process, the photoresist layer 320 on the front side of wafer B4 exposes a photoresist layer opening 323. The edge processing mode comprises the following steps: the anti-seepage ring 321 is firstly completed on the edge of the wafer B4 in a shading or exposure mode, and then the photoresist on the edge is developed in an exposure or shading mode. The treatment mode is shading or exposure depending on whether the photoresist material belongs to a positive photoresist material or a negative photoresist material, and if the photoresist material belongs to the positive photoresist material, a shading mode is adopted; if the photoresist material belongs to a negative photoresist material, an exposure mode is adopted. However, for laminated photoresist, the method can also be realized by laser ablation or the like;

step thirteen, referring to fig. 3O and fig. 3P, a metal bump 360 is formed by using an electroplating process, the useless photoresist is removed, and the useless metal seed layer 310 is etched away, so that the metal bump 360 is manufactured. The material forming the metal bump 360 includes, but is not limited to, gold, tin, silver, copper, nickel, etc. conductive materials that can be realized by plating.

And after the steps are completed, continuously completing the subsequent packaging steps. It should be further noted that the number of stacked wafers is not limited to five layers in this embodiment, and a stack of multiple layers of wafers may be provided within a permissible range.

In the second step, trimming and trimming the edges of the wafer B1, the wafer B2, the wafer B3 and the wafer B4, the silicon substrate 100 is cut from top to bottom only to be flush with the bottom of the through-silicon-via 101, so as to save cutting man-hour, reduce the loss of a cutting tool and reduce the production cost, as shown in fig. 3Q; in the subsequent third and fourth steps, the silicon substrate 100 of the remaining wafer B1 is thinned by a thinning process such as mechanical grinding or chemical etching until the upper surface of the through-silicon-via 101 is exposed, and trimming of the edges of the wafer B1, the wafer B2, the wafer B3, and the wafer B4 is completed, as shown in fig. 3R. In the second step, the edge cutting is performed in advance, so that the sharp angle of the wafer can be prevented from being formed after the grinding.

In step seven, the wafer B1, the wafer B2, the wafer B3 and the wafer B4 are sequentially stacked, and when they are connected to each other, a gap still exists between the top layers of the metal interconnection layers, which needs to be filled with an organic resin (not shown in the figure) such as epoxy resin, phenolic resin and the like, and the thickness of the organic resin is equal to that of the top layer of the metal interconnection layers, and the presence of the organic resin is beneficial to dispersing stress among the wafers and reinforcing the whole package structure.

The above-mentioned embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above description is only a detailed description of the present invention, and is not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (6)

1. A stacked wafer package structure, comprising a wafer stack C2, a wafer A1, an electrical connection layer (150), wherein the wafer stack C2 is disposed above a carrier wafer A1 and connected by the electrical connection layer (150), the wafer stack C1 comprises a wafer B1, a wafer B2, a wafer B3 and a wafer B4,

the wafer comprises a silicon substrate (100), a through silicon via (101), a dielectric layer I (110) and a metal interconnection layer (120), wherein the through silicon via (101) penetrates through the silicon substrate (100) from top to bottom, the dielectric layer I (110) is arranged above the silicon substrate (100) and the metal interconnection layer (120) is exposed through an opening of the dielectric layer I (110);

the wafer sizes are reduced layer by layer from bottom to top, a step-shaped side wall is formed on the periphery of the wafer, a carrier wafer A1 is arranged above the wafer stacking body C2, the front surface of the wafer stacking body C2 is coated with a dielectric layer III (300) and forms a dielectric layer III opening (301), the dielectric layer III (300) coats the step-shaped side wall of the wafer stacking body C2 downwards, a metal seed layer (310) and a metal bump (360) are arranged in the dielectric layer III opening (301), and the metal bump (360) is connected with a metal interconnection layer (120) of an adjacent wafer through the metal seed layer (310).

2. The package structure of claim 1, wherein the outer dimension distance difference Δ 1 between wafer B1 and wafer a1 is no greater than 2.5 mm and the outer dimension distance difference Δ 1 between wafer B1 and wafer a1 is minimal to ensure effective electrical interconnection of the plating jig metal contacts (401).

3. The package structure of claim 2, wherein a ratio of an outer ring dimension spacing difference Δ 2 between wafer B2 and wafer B1 to a thickness t2 of wafer B2 itself is not less than 2: 1.

4. The package structure of claim 3, wherein a ratio of an outer ring dimension spacing difference Δ 3 between wafer B3 and wafer B2 to a thickness t3 of wafer B3 itself is not less than 2: 1.

5. The package structure of claim 4, wherein a ratio of an outer ring dimension spacing difference Δ 4 between wafer B4 and wafer B3 to a thickness t4 of wafer B4 itself is not less than 2: 1.

6. The package structure of claim 1, wherein the wafers are filled with an organic resin having a thickness equal to a thickness of a top layer of the metal interconnect layer.

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