CN115642142A

CN115642142A - Chip stacking packaging structure and packaging method

Info

Publication number: CN115642142A
Application number: CN202211282467.0A
Authority: CN
Inventors: 邓鑫; 韦亚
Original assignee: Shenzhen Goodix Technology Co Ltd
Current assignee: Shenzhen Goodix Technology Co Ltd
Priority date: 2022-10-19
Filing date: 2022-10-19
Publication date: 2023-01-24

Abstract

The application belongs to the technical field of chip packaging, and particularly relates to a chip stacking and packaging structure and a chip stacking and packaging method. The packaging structure aims to solve the problems that the existing stacking packaging structure and process are complex and the chip transmission distance is large. According to the chip stacking and packaging structure, the second chip is arranged on the first chip, so that the second chip and the first chip are stacked; the electrical connection between the second chip and the first chip is realized by arranging a metal interconnection layer; and the lateral surface slope of second chip sets up, so make the metal interconnection layer partly stable in structure reliable and stable follow the shape and attach to the slope lateral surface, need not to set up intermediate interconnection layer between first chip and second chip, also need not to set up electrically conductive through-hole in second chip inside, do benefit to and simplify production processes, reduce cost, do benefit to and shorten the transmission distance between first chip and the second chip, reduce the circuit impedance between first chip and the second chip, make the encapsulation integrated level higher, improve product property ability.

Description

Chip stacking packaging structure and packaging method

Technical Field

The present disclosure relates to the field of chip packaging technologies, and in particular, to a chip stacking and packaging structure and a chip stacking and packaging method.

Background

With the increasing requirements for high performance, high transmission rate, small size, high reliability and ultra-low power consumption in chips and electronic products, higher requirements are also put forward on the structure of chip packaging.

In the related art, for the wafer level chip stacking and packaging scheme, an intermediate interconnection layer is usually added between two packaged chips, and an electrical connection structure is disposed in the intermediate interconnection layer to achieve vertical electrical interconnection between the upper and lower chips.

However, the addition of the intermediate interconnection layer not only makes the packaging process complicated and the packaging cost high, but also increases the transmission distance between the upper and lower chips, which affects the product performance.

Disclosure of Invention

The application provides a chip stacking and packaging structure and a chip stacking and packaging method, which aim to solve the technical problems of complex structure and process and large chip transmission distance of the conventional stacking and packaging structure.

In order to solve the technical problem, the following technical scheme is adopted in the application:

a first aspect of the present application provides a chip stack package structure,

the first chip is provided with a first surface and a second surface which are opposite along the thickness direction of the first chip;

the second chip is provided with a third surface and a fourth surface which are opposite to each other along the thickness direction perpendicular to the second chip, and the third surface is arranged on the first surface; the second chip also has an inclined outer side surface connected between the third surface and the fourth surface; and the metal interconnection layer is electrically connected between the first chip and the second chip, and part of the metal interconnection layer covers the inclined outer side surface along with the shape.

Compared with the prior art, the chip stack package structure provided by the first aspect of the present application has the following advantages:

according to the chip stacking and packaging structure, the second chip is arranged on the first chip, so that the second chip and the first chip are stacked; the electrical connection between the second chip and the first chip is realized by arranging a metal interconnection layer; and the lateral surface slope of second chip sets up, so make the metal interconnection layer partly stable in structure reliable and stable directly or indirectly attach to on the slope lateral surface along with the shape, need not additionally to set up electrically conductive through-hole and well medium interconnection layer, do benefit to and simplify production processes, reduce cost, do benefit to and shorten the transmission distance between first chip and the second chip, reduce the circuit impedance between first chip and the second chip, make the encapsulation integrated level higher, improve product property ability. Moreover, the metal interconnection layer is arranged on the surfaces of the first chip and the second chip stacking structure, so that the packaging structure and the packaging process are simplified; the thickness of the first chip and the second chip stacking structure is not increased, and the thickness of the packaging structure is reduced.

As an improvement of the above package structure of the present application, a first pin is disposed on the first chip, and a second pin is disposed on the second chip; the metal interconnection layer is electrically connected between the first pin and the second pin.

As an improvement of the above package structure of the present application, the first lead is disposed on the first surface.

As an improvement of the above package structure of the present application, the first lead is disposed on the second surface; a first through silicon via is arranged on the first chip, and at least part of the first pin is positioned in the first through silicon via; the metal interconnection layer is electrically connected with the first pin through the first silicon through hole.

As an improvement of the above package structure of the present application, the second pin is disposed on the fourth surface.

As an improvement of the above package structure of the present application, the second pin is disposed on the third surface; a second through silicon via is arranged on the second chip, and at least part of the second pin is positioned in the second through silicon via; the metal interconnection layer is electrically connected with the second pin through the second silicon through hole.

As an improvement of the above package structure of the present application, the first pin is located outside a projection of the second chip on the first surface.

As an improvement of the foregoing package structure of the present application, the first lead is located within a coverage of a projection of the second chip on the first surface; the chip stack packaging structure further comprises a metal lead-out layer, wherein a first end of the metal lead-out layer is electrically connected with the first pin, and a second end of the metal lead-out layer extends to the outer side of the projection of the second chip on the first surface; the metal interconnection layer is electrically connected between the second end of the metal lead-out layer and the second pin.

As an improvement of the above-mentioned package structure of the present application, the package structure further includes a first insulating layer, where the first insulating layer covers the metal lead-out layer and the rest of the first surface where the metal lead-out layer is not disposed; a fourth opening used for exposing the metal lead-out layer is arranged on the first insulating layer and is positioned on the outer side of the projection of the second chip on the first surface; the metal interconnection layer is electrically connected with the metal lead-out layer exposed by the fourth opening.

As an improvement of the above package structure of the present application, the package structure further includes a second insulating layer, and the second insulating layer covers a surface of the first chip facing the second chip along with the shape of the first chip; the second insulating layer is provided with a first opening used for exposing the first pin so as to enable the first pin to be electrically connected with the metal interconnection layer; the third surface is disposed on the second insulating layer.

As an improvement of the above package structure of the present application, a first adhesive layer is disposed between the third surface and the second insulating layer, and the first adhesive layer is configured to adhere the second chip and the second insulating layer.

As an improvement of the above-mentioned package structure of the present application, the package structure further includes a third insulating layer, where the third insulating layer covers the inclined outer side surface and a surface of the second chip departing from the first chip; the third insulating layer is provided with a second opening used for exposing the second pin so as to enable the second pin to be electrically connected with the metal interconnection layer.

As an improvement of the above-mentioned package structure of the present application, the package structure further includes a third chip, the third chip is disposed on the first surface, and an outer side surface of the third chip is disposed in an inclined manner, and an included angle between the outer side surface of the third chip and the first surface is an acute angle; the third chip is electrically connected with the first chip through the metal interconnection layer.

As an improvement of the above-mentioned packaging structure of the present application, the packaging structure further includes a fourth chip, the fourth chip is disposed on the fourth surface, an outer side surface of the fourth chip is disposed in an inclined manner, and an included angle between the outer side surface of the fourth chip and the fourth surface is an acute angle; at least one of the second chip and the first chip is electrically connected with the fourth chip through the metal interconnection layer.

As an improvement of the foregoing package structure of the present application, the metal interconnection layer is formed with a pad on the fourth surface of the second chip or the second surface of the first chip is provided with a pad.

As an improvement of the above-mentioned packaging structure of this application, be equipped with the electric contact lug on the pad, the electric contact lug protrusion in the surface of pad.

As an improvement of the above package structure of the present application, an under ball metal layer is disposed between the pad and the electrical contact bump.

As an improvement of the above package structure of the present application, the package structure further includes a fourth insulating layer, where a third opening for exposing the pad is formed on the fourth insulating layer; when the bonding pad is formed on the fourth surface of the second chip, the fourth insulating layer covers the metal interconnection layer and the rest surfaces without the metal interconnection layer; when the bonding pad is arranged on the second surface of the first chip, the fourth insulating layer covers the second surface.

As an improvement of the above package structure of the present application, the package structure further includes a first material supply wafer, and the first material supply wafer is provided with a plurality of first chips.

As an improvement of the above package structure of the present application, the package structure further includes a carrier, and the second surface of the first chip is attached to the carrier; when the carrier is a transparent carrier, the first chip is an optical sensing type chip, and a sensing area of the optical sensing type chip is located on the second surface of the first chip.

A second aspect of the present application provides a chip stack packaging method, which includes:

a second aspect of the present application provides a chip stack packaging method, including:

arranging a second chip on the first surface of the first chip, wherein the outer side surface of the second chip is an inclined surface, and the included angle between the outer side surface of the second chip and the first surface is an acute angle;

and forming a metal interconnection layer on the first chip and the second chip, wherein the metal interconnection layer is electrically connected between the first chip and the second chip, and part of the metal interconnection layer covers the outer side surface of the second chip in a conformal manner.

According to the method, the outer side face of the second chip is processed to form the inclined outer side face, the second chip is arranged on the first surface of the first chip, the first chip and the second chip are electrically connected through the metal interconnection layer, part of the metal interconnection layer is stable and reliable in structure and attached to the inclined outer side face in a shape following mode, a conductive through hole and an intermediate interconnection layer are not needed to be additionally arranged, the production process is simplified, the cost is reduced, the transmission distance between the first chip and the second chip is shortened, the packaging integration level is higher, the line impedance between the first chip and the second chip is reduced, and the product performance is improved.

As an improvement of the above packaging method of the present application, before disposing the second chip on the first surface of the first chip, the method further includes:

and forming a first pin on the first chip and a second pin on the second chip so that the metal interconnection layer is electrically connected between the first pin and the second pin.

As an improvement of the foregoing packaging method of the present application, the forming a metal interconnection layer on the first chip and the second chip specifically includes:

forming a first through silicon via on the first chip to expose at least part of the first pin, wherein the first pin is arranged on a side of the first chip, which faces away from the first surface;

forming the metal interconnection layer between the first lead and the second lead.

As an improvement of the above packaging method of the present application, the forming of the metal interconnection layer includes:

forming a second through silicon via on the second chip to expose at least part of the second pin, wherein the second pin is arranged on one surface of the second chip, which is far away from the first surface;

and forming a second insulating layer on one surface of the first chip facing the second chip, wherein the second insulating layer is provided with a first opening for exposing the first pin.

As an improvement of the foregoing packaging method of the present application, the disposing a second chip on the first surface of the first chip specifically includes:

and attaching the second chip to the first surface of the first chip.

As an improvement of the foregoing packaging method of the present application, before forming the metal interconnection layer on the first chip and the second chip, the method further includes:

forming a third insulating layer on one side of the second chip, which is far away from the first surface, and the outer side surface; and a second opening used for exposing the second pin is arranged on the third insulating layer.

As an improvement of the foregoing packaging method of the present application, after the forming the metal interconnection layer, the method further includes:

and forming a bonding pad on one surface of the second chip, which is far away from the first surface, and contacting and connecting the bonding pad and the metal interconnection layer.

As an improvement of the above-mentioned packaging method of the present application, the method further includes:

forming a fourth insulating layer, wherein the fourth insulating layer covers one surface of the second chip, which is far away from the first surface, the metal interconnection layer, the rest surfaces of the outer side surface of the second chip, on which the metal interconnection layer is not arranged, and the rest surfaces of the first surface, on which the metal interconnection layer is not arranged; and a third opening for exposing the bonding pad is arranged on the fourth insulating layer.

forming a fifth insulating layer, wherein the fifth insulating layer covers one surface of the second chip, which is far away from the first surface, the metal interconnection layer, the rest surfaces of the outer side surface of the second chip, on which the metal interconnection layer is not arranged, and the rest surfaces of the first surface, on which the metal interconnection layer is not arranged;

turning over the first chip provided with the second chip;

and forming a bonding pad on one side of the first chip, which is opposite to the first surface, and contacting and connecting the bonding pad and the metal interconnection layer.

providing a carrier, and attaching one surface of the first chip, which is far away from the first surface, to the carrier;

and grinding and thinning the first incoming wafer containing a plurality of the first chips to a target thickness.

As an improvement of the foregoing packaging method of the present application, after forming the metal interconnection layer, the method further includes:

and cutting the first incoming material wafer and the carrier to form a single chip stacking packaging structure.

In addition to the technical problems solved by the present application, the technical features constituting the technical solutions, and the advantages brought by the technical features of the technical solutions, other technical problems solved by the chip stack package structure and the chip stack package method provided by the present application, other technical features included in the technical solutions, and advantages brought by the technical features will be further described in detail in the detailed description of the embodiments.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments of the present application or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only a part of the embodiments of the present application, and the drawings and the description are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application for a person skilled in the art by referring to a specific embodiment, and other drawings can be obtained from the drawings without inventive efforts for the person skilled in the art.

FIG. 1 is a diagram of a chip stack package structure in the related art;

fig. 2 is a schematic diagram of a chip stack package structure according to an embodiment of the present disclosure;

fig. 3 is a schematic view of a chip stack package structure according to a second embodiment of the present application;

fig. 4 is a schematic diagram of a chip stack package structure according to a third embodiment of the present application;

fig. 5 is a schematic view of a chip stack package structure according to a fourth embodiment of the present application;

fig. 6 is a schematic diagram of a chip stack package structure according to a fifth embodiment of the present application;

fig. 7 is a schematic diagram of a chip stack package structure according to a sixth embodiment of the present application;

fig. 8 is a schematic view of a chip stack package structure according to a seventh embodiment of the present application;

fig. 9 is a schematic diagram of a chip stack package structure according to an eighth embodiment of the present application;

fig. 10 is a schematic diagram of a chip stack package structure according to a ninth embodiment of the disclosure;

fig. 11 is a schematic view of a chip stack package structure according to a tenth embodiment of the present application;

fig. 12a to 12l are flow charts of a chip stack packaging method according to an embodiment of the present disclosure;

fig. 13a to fig. 13b are flow charts illustrating a process of forming a first through silicon via according to an embodiment of the present disclosure.

Description of reference numerals:

10: an intermediate interconnect layer; 11: an electrical connection structure;

100: a first chip; 101: a first through-silicon-via; 102: a trench; 103: a through hole; 110: a first pin; 120: a second insulating layer; 130: a metal extraction layer; 140: a first insulating layer; 150: an insulating cover layer;

200: a second chip; 210: a second pin; 220: a third insulating layer; 230: a first adhesive layer; 230a: a second adhesive layer; 230b: a third adhesive layer; 240: a fifth insulating layer;

300: a metal interconnection layer; 310: a pad; 311: an electrical contact bump; 312: an under-ball metal layer; 313: a sixth insulating layer; 314: a metal connection layer; 320: a fourth insulating layer;

400: a third chip; 500: a fourth chip; 600: and (3) a carrier.

Detailed Description

The continuous high-speed development of Integrated Circuits (ICs) continuously leads to the revolution of products in various fields, and puts higher demands on the structure of chip packaging. Advanced packaging schemes for integrated circuits are currently moving toward small size, high density, and multiple functionality.

For the chip-level packaging scheme, upper and lower chips are basically stacked, and are respectively bonded to a packaging substrate through Wires (WB), and finally, solder balls are integrally molded and implanted. The lead bonding process and the plastic package process occupy a certain space, so that the packaging area and the packaging thickness are large.

Further, wafer level packaging schemes have been developed, which typically require vertical electrical interconnection of upper and lower chips via an intermediate interconnect layer, although the package area is somewhat reduced. Referring to fig. 1 in particular, an intermediate interconnection layer 10 is disposed between a first chip 100 and a second chip 200, a through hole is disposed on the intermediate interconnection layer 10, and an electrical connection structure 11 is disposed on the through hole and two side surfaces of the intermediate interconnection layer 10, so as to achieve vertical electrical interconnection between the first chip 100 and the second chip 200. However, the addition of the intermediate interconnection layer not only makes the packaging process complicated and the packaging cost high, but also increases the transmission distance between the upper and lower layers of chips, which affects the product performance.

In view of this, an embodiment of the present application provides a chip stacking and packaging structure, where the second chip is disposed on the first chip, and the outer side surface of the second chip is an inclined outer side surface, so that the metal interconnection layer can be attached to the inclined outer side surface, thereby implementing electrical connection between the first chip and the second chip, and no intermediate interconnection layer is required to be disposed, which is beneficial to reducing cost, shortening transmission distance between the first chip and the second chip, and is beneficial to reducing line impedance between the first chip and the second chip, and improving product performance.

Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application.

Example one

With reference to fig. 2, an embodiment of the present application provides a chip stack package structure, which includes a first chip 100, a second chip 200, and a metal interconnection layer 300.

The first chip 100 has a first surface and a second surface opposite to each other in a direction perpendicular to a thickness direction of the first chip 100. It is understood that the first surface refers to a surface of a side of the first chip 100 facing the second chip 200, and the second surface refers to a surface of a side of the first chip 100 facing away from the second chip 200. In the orientation shown in fig. 2, the first surface is the upper surface of the first chip 100 and the second surface is the lower surface of the first chip 100.

The first chip 100 has a second chip 200 disposed on a first surface thereof, and the second chip 200 has a third surface and a fourth surface opposite to each other in a thickness direction perpendicular to the second chip 200. It is understood that the third surface refers to a surface of a side of the second chip 200 facing the first chip 100, and the fourth surface refers to a surface of a side of the second chip 200 facing away from the first chip 100. In the orientation shown in fig. 2, the third surface is the lower surface of the second chip 200, and the fourth surface is the upper surface of the second chip 200.

The third surface of the second chip 200 is disposed on the first surface of the first chip 100. In the embodiment of the present application, the third surface of the second chip 200 is attached to the first surface of the first chip 100, and illustratively, the first adhesive layer 230 is disposed between the third surface of the second chip 200 and the first surface of the first chip 100, so as to fix the second chip 200 to the first chip 100. The first adhesive layer 230 may be disposed on the third surface of the second chip 200, and when the bonding is needed, the second chip 200 is bonded to the first chip 100 through the first adhesive layer 230 after the release film on the surface of the first adhesive layer 230 is removed.

The second chip 200 further has an inclined outer side surface connected between the third surface and the fourth surface, and an included angle between the inclined outer side surface and the third surface is an acute angle, so that the surface area of the third surface of the second chip 200 is larger than that of the fourth surface. Illustratively, the inclined outer side surface forms an angle of 70 degrees with the third surface. In the structure shown in fig. 2, the cross section of the second chip 200 may be formed in an isosceles trapezoid shape having a small top and a large bottom. The inclined outer side of the second chip 200 is provided to facilitate the attachment of a third insulating layer 220 and a metal interconnection layer 300, which will be described later.

It is understood that the side of the second chip 200 between the third surface and the fourth surface has four sides, and the four sides are all arranged as inclined outer sides, so that the second chip 200 is a trapezoidal stage.

It should be noted that the cross-sectional shape of the second chip 200 is not limited to the isosceles trapezoid shown in fig. 2, and the cross-sectional shape of the second chip 200 may also be a non-isosceles trapezoid as long as the outer side surface of the second chip 200 is an inclined outer side surface to facilitate the attachment of the third insulating layer 220 and the metal interconnection layer 300, which will be described later.

In order to realize the electrical connection between the first chip 100 and the second chip 200, the package structure of the embodiment of the application is provided with a metal interconnection layer 300 electrically connected between the first chip 100 and the second chip 200, and a portion of the metal interconnection layer 300 covers the inclined outer side surface along the shape, specifically, the metal interconnection layer 300 may cover the inclined outer side surface directly along the shape, or the metal interconnection layer 300 may cover the inclined outer side surface indirectly through an intermediate layer, for example, a third insulation layer 220 described later. By the arrangement, the metal interconnection layer 300 can be better attached to the inclined outer side surface, and a conductive through hole is not required to be additionally arranged, so that the packaging structure and the packaging process are simplified.

Note that the "conformal covering" means that a portion of the metal interconnection layer 300 conforms to the shape of the inclined outer side surface, that is, the portion of the metal interconnection layer 300 is inclined and parallel to the inclined outer side surface.

Alternatively, the metal interconnection layer 300 may be a metal layer formed by a metal plating process such as sputtering, electroplating, evaporation, etc. The material of the metal interconnection layer 300 may be aluminum, copper, nickel, silver, gold, titanium, or a combination thereof.

In the above solution, stacking of the second chip 200 and the first chip 100 is realized by disposing the second chip 200 on the first chip 100; the electrical connection between the second chip 200 and the first chip 100 is realized by arranging a metal interconnection layer 300; and the outer side surface of the second chip 200 is obliquely arranged to form an oblique outer side surface, so that part of the structure of the metal interconnection layer 300 is stably and reliably attached to the oblique outer side surface along with the shape, a conductive through hole and an intermediate interconnection layer are not required to be additionally arranged, the cost is reduced, the transmission distance between the first chip 100 and the second chip 200 is shortened, the line impedance between the first chip 100 and the second chip 200 is reduced, and the product performance is improved. Moreover, the metal interconnection layer 300 is disposed on the surface of the stacked structure of the first chip 100 and the second chip 200, which is beneficial to simplifying the package structure and the package process; the thickness of the stacked structure of the first chip 100 and the second chip 200 is not increased, which is beneficial to reducing the thickness of the packaging structure.

With reference to fig. 2, in order to facilitate the electrical connection between the metal interconnection layer 300 and the first chip 100, the first chip 100 is provided with first leads 110; in order to facilitate the electrical connection between the metal interconnection layer 300 and the second chip 200, the second chip 200 is provided with a second pin 210. The metal interconnection layer 300 is electrically connected between the first lead 110 and the second lead 210, thereby achieving electrical connection between the first chip 100 and the second chip 200.

In order to electrically connect the metal interconnection layer 300 to the first lead 110 and avoid contact with other positions of the first chip 100 for insulation protection, as shown in fig. 2, the package structure of the embodiment of the present invention further includes a second insulation layer 120, and the second insulation layer 120 covers a side of the first chip 100 facing the second chip 200, it can be understood that, in some possible implementations, the second insulation layer 120 covers not only the first surface of the first chip 100, but also, as shown in fig. 2, when the first lead 110 is disposed on a second surface away from the second chip 200, the first chip 100 is provided with a first through silicon via exposing the first lead 110, and the second insulation layer 120 can also cover a side surface of the first through silicon via to avoid contact between the metal interconnection layer 300 and the first chip 100.

Of course, the second insulating layer 120 is provided with a first opening for exposing the first lead 110, so that the metal interconnection layer 300 can be electrically connected to the first lead 110. Furthermore, the third surface of the second chip 200 is disposed on the second insulating layer 120, and the first adhesive layer 230 is disposed between the third surface of the second chip 200 and the second insulating layer 120 for adhering the second chip 200 and the second insulating layer 120, so that the second chip 200 is prevented from directly contacting the first chip 100 while the second chip 200 is fixed on the first chip 100.

The material of the second insulating layer 120 may be an inorganic insulating material or an organic insulating material, and the second insulating layer 120 has characteristics such as a high dielectric constant. The thickness of the second insulating layer 120 is typically between several micrometers and several tens of micrometers, for example, the thickness of the second insulating layer 120 is 10 micrometers.

Similarly, in order to electrically connect the metal interconnection layer 300 and the second leads 210 and avoid contact with other positions of the second chip 200 for insulation protection, as shown in fig. 2, the package structure of the embodiment of the present invention further includes a third insulation layer 220, and the third insulation layer 220 covers the inclined outer side surface along with the shape and the side of the second chip 200 departing from the first chip 100. It is understood that, in some possible embodiments, the third insulating layer 220 covers not only the fourth surface of the second chip 200, as shown in fig. 4, when the second pins 210 are disposed on the third surface of the second chip 200 facing the first chip 100, the second chip 200 is provided with second through-silicon vias exposing the second pins 210, and the third insulating layer 220 can also cover side surfaces of the second through-silicon vias, so as to prevent the metal interconnection layer 300 from contacting the second chip 200. The third insulating layer 220 covers the inclined outer side surface in a conformal manner, so that the third insulating layer 220 is arranged more firmly, and the part of the third insulating layer 220 opposite to the inclined outer side surface is also an inclined surface, thereby being beneficial to the arrangement of the metal interconnection layer 300.

Of course, the third insulating layer 220 may be provided with a second opening for exposing the second lead 210, so that the metal interconnection layer 300 can be electrically connected to the second lead 210.

The material of the third insulating layer 220 may be the same as that of the second insulating layer 120, and is not described herein again, so that the process is simplified and the production efficiency is improved.

Thus, referring to fig. 2, one end of the metal interconnection layer 300 is electrically connected to the first lead 110, and at least a portion of the metal interconnection layer 300 covers the second insulating layer 120, which is favorable for ensuring the reliability of the electrical connection between the metal interconnection layer 300 and the first lead 110; at least part of the metal interconnection layer 300 covers the inclined surface of the third insulating layer 220, opposite to the inclined outer side surface of the second chip 200, so that the metal interconnection layer 300 can be better attached and wired; at least a portion of the metal interconnection layer 300 covers the upper surface of the third insulating layer 220, and is opposite to the fourth surface of the second chip 200, so that the stability and reliability of the electrical connection between the metal interconnection layer 300 and the second lead 210 can be ensured.

The electrical connection between the first chip 100 and the second chip 200 in the package structure is described above, and the package structure is further electrically connected to an external device. For this purpose, the package structure of the embodiment of the present application further includes a pad 310, specifically referring to fig. 2, the pad 310 is used for electrically connecting with an external device, and the pad 310 is electrically connected with the metal interconnection layer 300, so as to electrically connect the first chip 100 and the second chip 200 with the external device.

In the embodiment of the present application, when the metal interconnection Layer 300 is manufactured by using a Redistribution Layer (RDL) process, the bonding pad 310 is formed at the same time, which is beneficial to simplifying the process and improving the production efficiency.

In conjunction with fig. 2, in some embodiments, the pads 310 are disposed on the fourth surface of the second chip 200, and in the orientation shown in fig. 2, the pads 310 are disposed on the upper surface of the entire package structure. With such an arrangement, the bonding pads 310 of the whole package structure do not need to be turned over, which is beneficial to simplifying the packaging process. In this embodiment, since at least a portion of the metal interconnection layer 300 is located on the fourth surface of the second chip 200, when the metal interconnection layer 300 is formed by using RDL, the pad 310 is formed at the same time, so that the pad 310 is in contact with the metal interconnection layer 300 to achieve electrical connection, and the process is simple.

In other embodiments, in conjunction with fig. 3, the bonding pads 310 are disposed on the second surface of the first chip 100, and in the orientation shown in fig. 3, the bonding pads 310 are disposed on the lower surface of the entire package structure. By such an arrangement, the first chip 100 can be directly electrically connected to an external device, and is suitable for device connection requirements of different electronic devices. In this embodiment, the pad 310 and the metal interconnection layer 300 are respectively located on opposite surfaces of the package structure, and therefore, the package structure of the embodiment of the present application further includes a metal connection layer 314 to electrically connect the metal interconnection layer 300 and the pad 310. Specifically, the sixth insulating layer 313 is disposed on the second surface of the first chip 100 to prevent the metal connection layer 314 from contacting other positions of the first chip 100 for insulation protection; and a fifth opening for exposing the first pin 110 is disposed on the sixth insulating layer 313, the metal connection layer 314 and the pad 310 are both disposed on a surface of the sixth insulating layer 313 away from the first chip 100, and the metal connection layer 314 is electrically connected to the pad 310 and the first pin 110, so that the metal interconnection layer 300 is electrically connected to the pad 310. The metal connection layer 314 and the bonding pad 310 of the present embodiment are both formed by using an RDL process, and the bonding pad 310 is formed simultaneously when the metal connection layer 314 is formed by using the RDL process.

It should be noted that, in some alternative embodiments, the pad 310 may be directly electrically connected to the second lead 210, for example, the right pad 310 and the second lead 210 in fig. 2; in some alternative embodiments, the pad 310 may be electrically connected to the first lead 110, for example, the pad 310 on the left side in fig. 2 is electrically connected to the first lead 110 through the metal interconnection layer 300 at other positions in the fourth surface.

After forming the bonding pads 310 electrically connected to an external device, an insulating layer is required to encapsulate the rest of the chip to form a complete package structure. Therefore, the package structure according to the embodiment of the present invention further includes a fourth insulating layer 320, the fourth insulating layer 320 covers the surface where the pad 310 is disposed, and a third opening for exposing the pad 310 is disposed on the fourth insulating layer 320.

Referring to fig. 2, the fourth insulating layer 320 covers not only the fourth surface on which the bonding pads 310 are disposed, but also the metal interconnection layer 300, the rest of the inclined outer side surfaces of the second chip 200 on which the metal interconnection layer 300 is not disposed, and the rest of the first surface of the first chip 100 on which the metal interconnection layer 300 is not disposed, so as to prevent the first chip 100, the second chip 200, and the metal interconnection layer 300 from being exposed.

Referring to fig. 3, the fourth insulating layer 320 covers the second surface of the first chip 100 at intervals, and specifically, the fourth insulating layer 320 covers not only the sixth insulating layer 313 provided with the bonding pads 310, but also the metal connection layer 314, so as to prevent the first chip 100 and the metal connection layer 314 from being exposed. As shown in fig. 3, the fifth insulating layer 240 covers the fourth surface of the second chip 200, the metal interconnection layer 300, and the rest surfaces of the second chip 200, on which the metal interconnection layer 300 is not disposed, on the inclined outer side surface, and the rest surfaces of the first surface of the first chip 100, on which the metal interconnection layer 300 is not disposed, so as to prevent the first chip 100, the second chip 200, and the metal interconnection layer 300 from being exposed.

In order to further improve the reliability of electrical connection between an external device and the bonding pad 310, in the embodiment of the present application, the bonding pad 310 is provided with an electrical contact bump 311, and the electrical contact bump 311 protrudes from the surface of the bonding pad 310. Referring to fig. 2, the electrical contact bumps 311 protrude from the second surface of the second chip 200; referring to fig. 3, the electrical contact bumps 311 protrude from the second surface of the first chip 100.

Alternatively, the electrical contact bumps 311 may be solder balls, and the solder balls are used as pads for electrical connection with an external device, so as to improve the reliability of the electrical connection. The solder balls can be made of tin metal and other materials. The electrical contact bumps 311 may also be pillars, such as copper pillars, with a tin layer disposed on the copper pillars to improve soldering performance.

In some possible implementations, with reference to fig. 3, an Under Ball Metallurgy (UBM) 312 is disposed between the electrical contact bump 311 and the pad 310 to relieve stress.

As can be seen from the above description, the first chip 100 has a first surface and a second surface opposite to each other, and the first chip 100 is provided with the first leads 110 for electrically connecting with the metal interconnection layer 300. The first leads 110 may be disposed on the first surface or the second surface according to actual product requirements. Referring to fig. 2 to 4 again, the first leads 110 are disposed on the second surface of the first chip 100, at this time, the first chip 100 is disposed with a first through silicon via, and at least a portion of the first leads 110 is located in the first through silicon via, so that the first leads 110 are exposed; thus, the metal interconnection layer 300 is electrically connected to the first lead 110 through the first through-silicon via, that is, a portion of the metal interconnection layer 300 is filled in the first through-silicon via and electrically connected to the first lead 110; with reference to fig. 5 and fig. 6, the first leads 110 are disposed on the first surface of the first chip 100, and at this time, a through silicon via does not need to be disposed on the first chip 100, which is beneficial to simplifying the packaging process.

As can be seen from the above description, the second chip 200 has a third surface and a fourth surface opposite to each other, and the second chip 200 is provided with the second pins 210 for electrically connecting with the metal interconnection layer 300. The second pins 210 may be disposed on the third surface or the fourth surface according to actual product requirements. With reference to fig. 2 and 5, the second pins 210 are disposed on the fourth surface of the second chip 200, and at this time, a through-silicon via does not need to be disposed on the second chip 200, which is beneficial to simplifying the packaging process; with reference to fig. 4 and fig. 6, the second leads 210 are disposed on the third surface of the second chip 200, at this time, the second chip 200 is disposed with a second through silicon via, and at least a portion of the second leads 210 is located in the second through silicon via, so that the second leads 210 are exposed; thus, the metal interconnection layer 300 is electrically connected to the second lead 210 through the second through-silicon via, that is, a portion of the metal interconnection layer 300 is filled in the second through-silicon via and electrically connected to the second lead 210.

Thus, there are four cases regarding the combination of the arrangement positions of the first pins 110 and the second pins 210, which are: as shown in fig. 2 and 3, the first leads 110 are disposed on the second surface of the first chip 100, and the second leads 210 are disposed on the fourth surface of the second chip 200; as shown in fig. 4, the first leads 110 are disposed on the second surface of the first chip 100, and the second leads 210 are disposed on the third surface of the second chip 200; as shown in fig. 5, the first leads 110 are disposed on the first surface of the first chip 100, and the second leads 210 are disposed on the fourth surface of the second chip 200; as shown in fig. 6, the first leads 110 are disposed on the first surface of the first chip 100, and the second leads 210 are disposed on the third surface of the second chip 200.

In the solution shown in fig. 5, since the first lead 110 and the second lead 210 are both disposed on the upper surface of the chip, the distance of the metal interconnection layer 300 between the first lead 110 and the second lead 210 is the shortest; and no through silicon via is required to be processed, and the structure and the process are simple.

The arrangement positions of the first leads 110 and the second leads 210 are described above, and the relative positions of the first leads 110 of the first chip 100 and the second chip 200 are described below with reference to fig. 6 and 7.

Referring to fig. 6, the first leads 110 are located at an edge of the first chip 100, and the first leads 110 are located outside the projection of the second chip 200 on the first surface, so that the first leads 110 are located on the first chip 100 at a portion other than the inclined outer side of the second chip 200, and the arrangement is such that the first leads 110 are located outside the second chip 200, which facilitates the arrangement of the metal interconnection layer 300 between the first leads 110 and the second leads 210, and is beneficial to improving the convenience of the packaging process.

In some other embodiments, referring to fig. 7, the first leads 110 are located in the middle region of the first chip 100, and the first leads 110 are located in the coverage of the projection of the second chip 200 on the first surface, so that the first leads 110 are located on the opposite portion between the second chip 200 and the first chip 100, and do not occupy the outer space of the first chip 100. It is understood that the middle region of the first chip 100 may be a Non-Circuit Under Pad (Non-CUP) structure, which facilitates the processing of through silicon vias.

The chip stack package structure of the present embodiment further includes a metal lead-out layer 130 for leading out the first lead 110 to an edge position of the first chip 100. Specifically, a first end of the metal lead-out layer 130 is electrically connected to the first pin 110, and a second end of the metal lead-out layer 130 extends to an outer side of a projection of the second chip 200 on the first surface, so that the metal interconnection layer 300 is electrically connected to the metal lead-out layer 130. At this time, the metal interconnection layer 300 is electrically connected between the second end of the metal lead-out layer 130 and the second pin 210, thereby achieving the electrical connection between the first pin 110 and the second pin 210.

The metal extraction layer 130 is formed by an RDL process, and the metal extraction layer 130 is disposed on the second insulating layer 120. It is understood that, in order to avoid the metal extraction layer 130 from contacting the first chip 100, an edge of the metal extraction layer 130 and an edge of the second insulation layer 120 may be provided with a space.

In order to avoid multiple position contact connection between the metal lead-out layer 130 and the metal interconnection layer 300, the package structure of this embodiment further includes a first insulating layer 140, the first insulating layer 140 covers the metal lead-out layer 130 and the rest of the first surface where the metal lead-out layer 130 is not disposed, as shown in fig. 7, the first insulating layer 140 covers the rest of the surfaces of the metal lead-out layer 130 and the second insulating layer 120 where the metal lead-out layer 130 is not disposed. In this way, a relatively flat layer is formed on the surface of the metal lead-out layer 130 away from the first chip 100, which facilitates the adhesion of the second chip 200 and the arrangement of the metal interconnection layer 300.

Of course, in order to electrically connect the metal lead-out layer 130 and the metal interconnection layer 300, a fourth opening for exposing the metal lead-out layer 130 is disposed on the first insulating layer 140, so that the metal interconnection layer 300 is electrically connected with the metal lead-out layer 130 exposed by the fourth opening. The fourth opening is located outside the projection of the second chip 200 on the first surface, so that the electrical connection position of the first pin 110 and the second pin 210 is led out to the outside of the projection of the second chip 200 on the first surface, which facilitates the arrangement of the metal interconnection layer 300.

Alternatively, in some possible implementations, the first insulating layer 140 is not provided in the package structure, the second chip 200 is directly attached to the metal lead layer 130, and the metal interconnection layer 300 is disposed, and the first chip 100 and the second chip 200 are insulated by using the first adhesive layer 230, which is beneficial to reducing the thickness dimension of the package structure.

In the above description of the embodiment, only one second chip 200 is provided on one first chip 100, but this is not a limitation on the number of second chips 200.

With reference to fig. 8, in some possible implementations, the chip stack package structure further includes a third chip 400, where the third chip 400 and the second chip 200 are disposed on the first surface of the first chip 100 together, for example, the third chip 400 and the second chip 200 may be disposed on the first surface of the first chip 100 side by side, and an outer side of the third chip 400 is disposed obliquely, and an included angle between the outer side of the third chip 400 and the first surface is an acute angle; the third chip 400 is electrically connected to the first chip 100 through the metal interconnection layer 300. Optionally, a space is provided between the third chip 400 and the second chip 200, so as to facilitate the arrangement of the metal interconnection layer 300.

The third chip 400 and the second chip 200 may be of the same type or different types, for example, the third chip 400 and the second chip 200 may both be processing chips; for another example, the second chip 200 is a processing chip and the third chip 400 is a memory chip. The third chip 400 is similar to the second chip 200 in shape, and the outer side surface thereof is disposed obliquely, so as to facilitate the arrangement of the metal interconnection layer 300. Moreover, the attaching manner and the arrangement manner of the insulating layer of the third chip 400 are the same as those of the second chip 200, and are not described herein again.

It is understood that one third chip 400 may be provided, or two, three, etc. third chips may be provided. It should be further noted that the arrangement of the leads on the third chip 400 can be as described above, as shown in fig. 8, where the leads are disposed on the surface of the third chip 400 facing away from the first chip 100; alternatively, the leads thereof may also be disposed on the surface of the third chip 400 facing the first chip 100. The third chip 400 may be as shown in fig. 8, and the projection of the third chip 400 on the first surface of the first chip 100 is located inside the first pins 110, or the first pins 110 are located inside the projection of the third chip 400 on the first surface, and in particular, the arrangement of the second chip 200 shown in fig. 7 may be referred to.

Referring to fig. 8, the second chip 200 is adhered to the first chip 100 by the first adhesive layer 230, and the third chip 400 is adhered to the first chip 100 by the second adhesive layer 230 a. The first adhesive layer 230 is adhered to the second chip 200, and the second adhesive layer 230a is adhered to the third chip 400, and the specific materials of the first adhesive layer 230 and the second adhesive layer 230a may be different due to the different types, adhesive performance requirements, and the like of the second chip 200 and the third chip 400.

The present implementation improves the integration level of the chips in the package structure by disposing a plurality of chips on the first surface of the first chip 100. Of course, in other possible implementations, a plurality of chips may be stacked on the first chip 100 to improve the integration of the chips.

Specifically referring to fig. 9, the chip stacking and packaging structure of this implementation further includes a fourth chip 500, where the fourth chip 500 is disposed on a fourth surface of the second chip 200, an outer side surface of the fourth chip 500 is disposed in an inclined manner, and an included angle between the outer side surface of the fourth chip 500 and the fourth surface is an acute angle; at least one of the second chip 200 and the first chip 100 is electrically connected to the fourth chip 500 through the metal interconnection layer 300.

The type of the fourth chip 500 may be the same as or different from that of the second chip 200, for example, the fourth chip 500 and the second chip 200 may both be processing chips; for another example, the second chip 200 is an induction chip, and the fourth chip 500 is a memory chip. The fourth chip 500 is similar to the second chip 200 in shape, and the outer side surface thereof is disposed obliquely, so as to facilitate the arrangement of the metal interconnection layer 300. Moreover, the attaching manner and the arrangement manner of the insulating layer of the fourth chip 500 are the same as those of the second chip 200, and are not described herein again.

It is understood that one fourth chip 500 may be provided, or two, three, etc. multiple fourth chips 500 may be provided, and the multiple fourth chips 500 are stacked on the fourth surface. It should be further noted that the arrangement of the pins on the fourth chip 500 may be as described above, as shown in fig. 9, where the pins are disposed on the surface of the fourth chip 500 facing away from the second chip 200; alternatively, the leads may be disposed on the surface of the fourth chip 500 facing the second chip 200, and in this case, through-silicon vias are disposed on the fourth chip 500 to expose the leads. The fourth chip 500 may be as shown in fig. 9, and a projection of the fourth chip 500 on the fourth surface of the second chip 200 is located inside the second pins 210, or the second pins 210 are located inside a projection of the fourth chip 500 on the fourth surface, and specifically, refer to the arrangement of the second chip 200 shown in fig. 7.

On the first chip 100 a plurality of chips are arranged stacked, the pads 310 and the electrical contact bumps 311 being arranged on the topmost chip or on the second surface of the first chip 100, see in particular fig. 3.

Referring to fig. 9, the second chip 200 is adhered to the first chip 100 by the first adhesive layer 230, and the fourth chip 500 is adhered to the second chip 200 by the third adhesive layer 230 b. The first adhesive layer 230 is adhered to the second chip 200, and the third adhesive layer 230b is adhered to the fourth chip 500, and the specific materials of the first adhesive layer 230 and the third adhesive layer 230b may be different due to the different types, adhesive performance requirements, and the like of the second chip 200 and the fourth chip 500.

Finally, it is described that the package structure of the embodiment of the present application is applied to wafer-level chip package, and specifically, the package structure further includes a first incoming wafer, the first incoming wafer is provided with a plurality of first chips 100, and the plurality of first chips 100 on the first incoming wafer are provided with the above package structure, so that a wafer-level package processing process is integrally adopted, which is beneficial to improving production efficiency. And after the packaging is finished, cutting to form a plurality of packaging structures.

The first incoming wafer is generally attached to the carrier 600, which facilitates the implementation of the package structure, specifically referring to fig. 2 to 9. The carrier 600 may be a silicon wafer, a transparent carrier (e.g., a glass sheet, etc.), a metal plate, etc. In some possible embodiments, for example when carrier 600 is a transparent glass sheet, first chip 100 may be an optical sensing type chip, and the sensing region is located at the second surface of first chip 100. Optionally, the carrier 600 and the first incoming wafer have the same size, and the carrier 600 and the first incoming wafer may be attached by an organic adhesive.

According to some actual product requirements, the package structure may also be formed by cutting the first incoming wafer after removing the carrier 600, and as shown in fig. 10 and 11. In some possible embodiments, as shown in fig. 10 and 11, the first lead 110 is disposed on the second surface of the first chip 100, and after the carrier is removed, the first lead 110 is exposed, for this reason, the package structure of this embodiment further includes an insulating cover 150, and the insulating cover 150 covers the first lead 110 to protect the first lead 110 in an insulating manner. The insulating cover layer 150 may be formed in a packaging process, and the insulating cover layer 150 may also be a Passivation layer (Passivation) of the first incoming wafer itself. In other possible embodiments, it can be understood that, when the first lead 110 is disposed on the first surface of the first chip 100, since the first lead 110 is in contact with the metal interconnection layer 300, the insulating cover layer 150 is not required to cover the first lead 110.

Example two

Fig. 12a to 12l are flowcharts of a chip stack packaging method according to an embodiment of the present disclosure. In the embodiment of the present application, a packaging method of the structure in fig. 2 is taken as an example to illustrate a chip stack packaging method provided in the embodiment of the present application.

With reference to fig. 12a to fig. 12l, the chip stack package method provided in the embodiment of the present application is applied to the chip stack package structure provided in the foregoing embodiment, and the method includes:

step S101: a first chip 100 and a second chip 200 are provided.

Referring to fig. 12a, the first chip 100 is from a first incoming wafer having a plurality of first chips 100. The first leads 110 are formed during a first incoming wafer fabrication process. The initial thickness of the first incoming wafer is up to 700 μm.

As shown in fig. 12b, the second die 200 is from a second incoming wafer having a plurality of second dies 200. The second leads 210 may be formed in a second incoming wafer fabrication process. The initial thickness of the second starting wafer may be, for example, 700 μm. Referring to fig. 12c, the back surface of the second incoming wafer is ground, thinned and polished to reduce the thickness of the second incoming wafer to a target thickness, and a first adhesive layer 230 is attached to the bottom of the second incoming wafer, where the first adhesive layer 230 is used to adhere the second chip 200 to the first chip 100 of the first incoming wafer. Typically, the target thickness may range from 50 to 70 μm to be suitable for subsequent processing.

In step S102, the outer surface of the second chip 200 is processed to form an inclined outer surface 201.

With reference to fig. 12d, the method specifically includes: the second wafer is cut by a tool knife to form the second chip 200, so that the edge of the second chip 200 has a certain inclination angle to form an inclined outer side surface 201, thereby facilitating the subsequent attachment of the packaging lamination. Wherein the tool knife may comprise a trapezoidal knife, or the tool knife may comprise a trapezoidal knife and a conventional wafer cutter. Alternatively, the inclined outer side 201 may be formed by etching, laser machining, or a combination thereof.

Step S103, referring to fig. 12e, a first incoming wafer is bonded to the carrier 600, and the first incoming wafer including the plurality of first chips 100 is ground and thinned to a target thickness. For example, a first incoming wafer is attached to carrier 600 by an adhesive. The carrier 600 may be a silicon wafer, a transparent carrier (e.g., a glass sheet, etc.), a metal plate, etc. Optionally, the carrier 600 has the same size as the first incoming wafer to better support the first incoming wafer. Grinding, thinning and polishing the back surface of the first incoming wafer, i.e., the top surface in fig. 12e, to thin the first incoming wafer to a target thickness, optionally, the target thickness is 40-90 μm, so as to be suitable for subsequent processing.

Since the first lead 110 of the first chip 100 is attached to the carrier 600, in order to expose the first lead 110, a through silicon via is disposed on the first chip 100 according to the embodiment of the present disclosure. Refer specifically to step S104.

In step S104, referring to fig. 12f, a first through silicon via 101 is processed and formed on the first chip 100 of the first incoming wafer to expose at least a portion of the first lead 110. The first leads 110 are disposed on a surface of the first chip 100 facing away from the first surface. The first through-silicon-via 101 may be formed by etching, laser processing, or the like. The side surface of the first through-silicon-via 101 is an inclined sidewall, so that the cross-sectional area of the end of the first through-silicon-via 101 close to the first pin 110 is smaller, and the cross-sectional area of the end of the first through-silicon-via 101 close to the top surface of the first chip 100 is larger, thereby facilitating the attachment of the metal interconnection layer. Of course, the side surface of the first through-silicon via 101 may also be a vertical sidewall, so that the aperture of the first through-silicon via 101 is smaller, and the volume occupied by the first chip 100 is also smaller. The cross section of the first through-silicon via 101 is a section formed by cutting the first through-silicon via 101 in a plane parallel to the surface of the first chip 100.

In some alternative implementations, the first through silicon via 101 may also be formed in the following manner, with particular reference to fig. 13a to 13b. As shown in fig. 13a, a trapezoidal Trench 102 (Trench) is processed on the first chip 100 of the first incoming wafer, and the first pin 110 is opposite to the Trench 102. As shown in fig. 13b, a through hole 103 is processed on the groove 102 so that the first lead 110 is exposed.

Step S105, with reference to fig. 12g, a second insulating layer 120 is formed on a surface of the first chip 100 facing the second chip, wherein the second insulating layer 120 is provided with a first opening for exposing the first lead 110. The second insulating layer 120 may be formed by wafer-level injection Molding (Molding), spraying, and the like, and then subjected to baking, stress relieving, and the like, so as to form the second insulating layer 120 on a side of the first chip 100 facing the second chip 200. When the first lead 110 is disposed on the first surface of the first chip 100, the structure of fig. 5 may be specifically referred to, and at this time, the second insulating layer 120 may also be implemented by a spin Coating (Coating) process. It can be understood that, with reference to fig. 12g, when the first through silicon via 101 is disposed on the first chip 100, the second insulating layer 120 covers not only the surface of the first chip 100 away from the carrier 600, but also the sidewall of the first through silicon via 101, so as to avoid the contact between the subsequent metal interconnection layer and the first chip 100 except for the first pin 110, thereby achieving insulation protection.

Step S106, in conjunction with fig. 12h, the second chip 200 is disposed on the first surface of the first chip 100, i.e. the second chip 200 is disposed on the top surface of the first chip 100 facing away from the carrier 600. At this time, an included angle between the inclined outer side surface of the second chip 200 and the first surface of the first chip 100 is an acute angle. Specifically, the release film of the first adhesive layer 230 is removed from the single second chip 200 cut in step S102, and then the single second chip 200 is attached to the first chips 100 of the first incoming wafer through a Die Attach (DA) process, so that the second chips 200 correspond to all the first chips 100 on the first incoming wafer one to one.

Step S107, forming a third insulating layer 220 on one side of the second chip 200 departing from the first surface of the first chip 100 and the inclined outer side surface; the third insulating layer 220 is provided with a second opening for exposing the second lead 210. Referring to fig. 12i, the third insulating layer 220 covers the top surface and the inclined outer side of the second chip 200, and the third insulating layer 220 can be better attached to the inclined outer side due to the inclined outer side. The forming process of the third insulating layer 220 may be the same as the forming process of the second insulating layer 120 in step S105, and is not repeated herein. It should be noted that, in some possible embodiments, a portion of the third insulating layer 220 covers the inclined outer side surface, and the third insulating layer 220 cannot be formed by a spin-coating process.

Step S108 is to form a metal interconnection layer 300 on the first chip 100 and the second chip 200, wherein the metal interconnection layer 300 is electrically connected between the first chip 100 and the second chip 200, and a portion of the metal interconnection layer 300 covers the inclined outer side surface along with the shape, so that the metal interconnection layer 300 is more stably and reliably attached, as shown in fig. 12j. The metal interconnection layer 300 is electrically connected between the first lead 110 and the second lead 210, and electrically connects the first chip 100 and the second chip 200. Meanwhile, a pad 310 is formed on a side of the second chip 200 facing away from the first surface of the first chip 100, and the pad 310 is formed when the metal interconnection layer 300 is formed, so that the metal interconnection layer 300 is in contact connection with the pad 310, so that the first chip 100 and the second chip 200 can be electrically connected with an external device through the pad 310. The metal interconnection layer 300 may be formed by a metal plating process such as sputtering, electroplating, or evaporation, and the material may be metal such as aluminum, copper, nickel, silver, gold, titanium, or a combination thereof.

Step S109, forming a fourth insulating layer 320, where the fourth insulating layer 320 covers a surface of the second chip 200 away from the first surface, the metal interconnection layer 300, the rest of the surfaces of the inclined outer side surfaces where the metal interconnection layer 300 is not disposed, and the rest of the surfaces of the first surface where the metal interconnection layer 300 is not disposed; and a third opening for exposing the pad 310 is disposed on the fourth insulating layer 320, referring to fig. 12k in particular. The forming process of the fourth insulating layer 320 may be the same as the forming process of the second insulating layer 120 in step S105, and is not described herein again.

In step S110, an electrical contact bump 311 is formed on the pad 310, specifically referring to fig. 12l. Optionally, a Ball Drop (Ball Drop) process is used to plant a solder Ball on the pad 310 to form the electrical contact bump 311, or a solder Ball electroplating process or a solder paste brushing and reflowing process may be used to process the solder Ball.

Step S111, the first incoming wafer and the carrier 600 are cut to form a single chip stacked package structure.

In the chip stack packaging method according to the embodiment of the application, the inclined outer side surface is formed by processing the outer side surface of the second chip 200; and disposing the second chip 200 on the first surface of the first chip 100, so as to realize the stacking of the second chip 200 and the first chip 100; the electrical connection between the second chip 200 and the first chip 100 is realized by arranging a metal interconnection layer 300; and the lateral surface of the second chip 200 is obliquely arranged, so that part of the structure of the metal interconnection layer 300 is stably and reliably attached to the oblique lateral surface along with the shape, a conductive through hole and an intermediate interconnection layer are not required to be additionally arranged, the cost is reduced, the transmission distance between the first chip 100 and the second chip 200 is shortened, the line impedance between the first chip 100 and the second chip 200 is reduced, and the product performance is improved. Moreover, the metal interconnection layer 300 is disposed on the surface of the stack structure of the first chip 100 and the second chip 200, which is beneficial to simplifying the package structure and the package process; the thickness of the stacked structure of the first chip 100 and the second chip 200 is not increased, which is beneficial to reducing the thickness of the packaging structure.

The chip stack packaging method corresponding to fig. 3 to 11 can refer to the above-mentioned packaging method, and only the different steps in the manufacturing process of the structure of fig. 3 to 11 from that of fig. 2 will be described.

The structure in fig. 3 differs from the structure in fig. 2 in the preparation: forming a fifth insulating layer 240 instead of step S109; then, the first wafer with the first chip 100 of the second chip 200 is turned over, and a sixth insulating layer 313, a metal connection layer 314 and an under ball metal layer 312 are sequentially formed on the surface of the first chip 100 away from the second chip 200; finally, the step of forming the electrical contact bump 311 in step S110 is performed. The forming process of the sixth insulating layer 313 may be the same as the forming process of the second insulating layer 120 in step S105, and is not described herein again. The formation process of the metal connection layer 314 and the ubm layer 312 may refer to the step S108 of the formation process of the metal interconnection layer 300, and will not be described herein again.

The structure in fig. 4 differs from the structure in fig. 2 in the preparation: after step S106 and before step S107, a Through Silicon Via (TSV) etching process is added, specifically, a second TSV is formed on the second chip 200 to expose at least a portion of the second pins 210, the second pins 210 are disposed on a surface (corresponding to a bottom surface in the drawing direction) of the second chip 200 facing the first surface, and then a subsequent packaging step is performed.

The structure in fig. 5 differs from the structure in fig. 2 in the preparation: step S104 is omitted, i.e., the step of forming the first through-silicon-via is not required.

The structure in fig. 6 differs from the structure in fig. 2 in the preparation: step S104 is omitted, and after step S106 and before step S107, a Through Silicon Via (TSV) etching process is added, specifically, a second TSV is formed on the second chip 200, so that the second pin 210 on the third surface (corresponding to the bottom surface in the drawing direction) of the second chip 200 is exposed, and then the subsequent packaging step is performed.

The difference between the structure in fig. 7 and the structure in fig. 2 in the preparation is that: after step S105 and before step S106, the metal lead-out layer 130 and the first insulating layer 140 are sequentially formed to guide the first leads 110 in the central region of the first chip 100 to the edge region, thereby facilitating the arrangement of the subsequent metal interconnection layer 300. The forming process of the first insulating layer 140 may be the same as the forming process of the second insulating layer 120 in step S105, and is not repeated herein. The forming process of the metal lead-out layer 130 may refer to the forming process step S108 of the metal interconnect layer 300, and will not be described herein again. Of course, the first insulating layer 140 may be omitted, and the metal extraction layer 130 may be directly provided.

The difference between the structure in fig. 8 and the structure in fig. 2 in the preparation is that: in steps S101 and S102, the second chip 200 is formed, and the third chip 400 is formed at the same time, and the process of forming the third chip 400 is the same as the process of forming the second chip 200, and is not repeated herein. In step S106, while the second chip 200 is attached by the first adhesive layer 230, the third chip 400 is simultaneously attached to the first surface of the first chip 100 by the second adhesive layer 230 a.

The difference between the structure in fig. 9 and the structure in fig. 2 at the time of manufacture is that: in step S101 and step S102, the second chip 200 is formed and the fourth chip 500 is formed at the same time, and the process of forming the fourth chip 500 is the same as the process of routing the second chip 200, and is not described again here. In step S106, after the second chip 200 is attached by the first adhesive layer 230, the fourth chip 500 is attached to the surface of the second chip 200 away from the first chip 100 by the third adhesive layer 230b, and the subsequent steps are performed.

The structure in fig. 10 differs from the structure in fig. 2 in the preparation: before step S111, the carrier 600 is removed, and then cut to form a single chip stacked package structure.

The structure in fig. 11 differs from the structure in fig. 2 in the preparation: after step S106 and before step S107, a second through-silicon via is processed on the second chip 200 to expose the second lead 210; before step S111, the carrier 600 is removed, and then cut to form a single chip stacked package structure.

According to the chip stacking and packaging method provided by the embodiment of the application, the inclined outer side surface is formed by processing the outer side surface of the second chip 200, the second chip 200 is arranged on the first surface of the first chip 100, the first chip 100 and the second chip 200 are electrically connected by forming the metal interconnection layer 300, part of the metal interconnection layer 300 is stably and reliably attached to the inclined outer side surface in a shape following manner, a conductive through hole and an intermediate interconnection layer are not required to be additionally arranged, the production process is simplified, the cost is reduced, the transmission distance between the first chip 100 and the second chip 200 is shortened, the packaging integration level is higher, the line impedance between the first chip 100 and the second chip 200 is reduced, and the product performance is improved.

In the description above, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and these modifications or substitutions do not depart from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip stack package structure, comprising:

the first chip is provided with a first surface and a second surface which are opposite along the thickness direction which is vertical to the first chip;

2. The chip stack package structure according to claim 1, wherein the first chip has a first lead disposed thereon, and the second chip has a second lead disposed thereon; the metal interconnection layer is electrically connected between the first pin and the second pin.

3. The chip stack package structure according to claim 2, wherein the first lead is disposed on the first surface.

4. The chip stack package structure according to claim 2, wherein the first lead is disposed on the second surface;

a first through silicon via is arranged on the first chip, and at least part of the first pin is positioned in the first through silicon via; the metal interconnection layer is electrically connected with the first pin through the first through silicon via.

5. The chip stack package structure according to claim 2, wherein the second lead is disposed on the fourth surface.

6. The chip stack package structure according to claim 2, wherein the second lead is disposed on the third surface;

a second through silicon via is arranged on the second chip, and at least part of the second pin is positioned in the second through silicon via; the metal interconnection layer is electrically connected with the second pin through the second through silicon via.

7. The chip stack package structure according to any one of claims 2 to 6, wherein the first lead is located outside a projection of the second chip on the first surface.

8. The chip stack package structure according to any one of claims 2 to 6, wherein the first pin is located within a coverage of a projection of the second chip on the first surface;

the chip stack packaging structure further comprises a metal lead-out layer, wherein a first end of the metal lead-out layer is electrically connected with the first pin, and a second end of the metal lead-out layer extends to the outer side of the projection of the second chip on the first surface;

the metal interconnection layer is electrically connected between the second end of the metal lead-out layer and the second pin.

9. The chip stack package structure according to claim 8, further comprising a first insulating layer covering the metal extraction layer and the remaining surface of the first surface on which the metal extraction layer is not disposed; a fourth opening used for exposing the metal leading-out layer is formed in the first insulating layer and located on the outer side of the projection of the second chip on the first surface;

the metal interconnection layer is electrically connected with the metal leading-out layer exposed from the fourth opening.

10. The chip stack package structure according to any one of claims 2 to 6, further comprising a second insulating layer conformal-covering a side of the first chip facing the second chip; the second insulating layer is provided with a first opening used for exposing the first pin so as to enable the first pin to be electrically connected with the metal interconnection layer;

the third surface is disposed on the second insulating layer.

11. The chip stack package structure according to claim 10, wherein a first adhesive layer is disposed between the third surface and the second insulating layer, and the first adhesive layer is configured to adhere the second chip and the second insulating layer.

12. The chip stack package structure according to any one of claims 2 to 6, further comprising a third insulating layer conformally covering the inclined outer side surface and a surface of the second chip facing away from the first chip; the third insulating layer is provided with a second opening used for exposing the second pin so as to enable the second pin to be electrically connected with the metal interconnection layer.

13. The chip stack package structure according to any one of claims 1 to 6, further comprising a third chip, wherein the third chip is disposed on the first surface, and an outer side of the third chip is disposed obliquely, and an included angle between the outer side of the third chip and the first surface is an acute angle;

the third chip is electrically connected with the first chip through the metal interconnection layer.

14. The chip stack package structure according to any one of claims 1 to 6, further comprising a fourth chip, wherein the fourth chip is disposed on the fourth surface, an outer side surface of the fourth chip is disposed obliquely, and an included angle between the outer side surface of the fourth chip and the fourth surface is an acute angle;

at least one of the second chip and the first chip is electrically connected with the fourth chip through the metal interconnection layer.

15. The chip stack package structure according to any one of claims 1 to 6, wherein the metal interconnection layer is formed with a pad on the fourth surface of the second chip, or the second surface of the first chip is provided with a pad.

16. The chip stack package structure according to claim 15, wherein the bonding pad has an electrical contact bump thereon, and the electrical contact bump protrudes from a surface of the bonding pad.

17. The chip stack package structure according to claim 16, wherein an under ball metal layer is disposed between the pad and the electrical contact bump.

18. The chip stack package structure according to claim 15, further comprising a fourth insulating layer, wherein a third opening is formed in the fourth insulating layer for exposing the pad;

when the bonding pad is formed on the fourth surface of the second chip, the fourth insulating layer covers the metal interconnection layer and the rest surfaces without the metal interconnection layer;

when the bonding pad is arranged on the second surface of the first chip, the fourth insulating layer covers the second surface.

19. The chip stack package structure according to any one of claims 1 to 6, further comprising a first incoming wafer on which a plurality of the first chips are disposed.

20. The chip stack package structure according to any one of claims 1 to 6, further comprising a carrier, wherein the second surface of the first chip is attached to the carrier;

when the carrier is a transparent carrier, the first chip is an optical sensing type chip, and a sensing area of the optical sensing type chip is located on the second surface of the first chip.

21. A chip stack packaging method is characterized by comprising the following steps:

22. The method for packaging according to claim 21, further comprising, before disposing the second chip on the first surface of the first chip:

23. The method according to claim 22, wherein the forming a metal interconnection layer on the first chip and the second chip specifically comprises:

the metal interconnect layer is formed between the first lead and the second lead.

24. The method of claim 22, wherein the forming the metal interconnect layer comprises:

forming a second through silicon via on the second chip to expose at least part of the second pin, wherein the second pin is arranged on one surface of the second chip facing the first surface;

25. The method for packaging according to any of claims 22-24, further comprising, before disposing the second chip on the first surface of the first chip:

26. The method according to claim 25, wherein the disposing the second chip on the first surface of the first chip specifically comprises:

and attaching the second chip to the first surface of the first chip.

27. The packaging method according to any one of claims 22 to 24, further comprising, before forming the metal interconnect layer on the first chip and the second chip:

28. The method for packaging according to any of claims 21-24, further comprising, after the forming the metal interconnect layer:

29. The method of packaging of claim 28, further comprising:

30. The method of any of claims 21-24, further comprising, after the forming the metal interconnect layer:

turning over the first chip provided with the second chip;

31. The packaging method according to any one of claims 21 to 24, further comprising, before disposing the second chip on the first surface of the first chip:

and grinding and thinning a first incoming wafer containing a plurality of first chips to a target thickness.

32. The method of claim 31, further comprising, after forming the metal interconnect layer: