CN211088246U

CN211088246U - Semiconductor chip packaging structure

Info

Publication number: CN211088246U
Application number: CN201922418284.7U
Authority: CN
Inventors: 徐罕; 陈彦亨; 吴政达; 林正忠; 高建章
Original assignee: SJ Semiconductor Jiangyin Corp
Current assignee: SJ Semiconductor Jiangyin Corp
Priority date: 2019-12-30
Filing date: 2019-12-30
Publication date: 2020-07-24
Anticipated expiration: 2029-12-30

Abstract

The utility model provides a semiconductor chip packaging structure. The packaging structure comprises a semiconductor chip, a conductive column, an epoxy resin layer, a first polymer resin layer, a metal wiring layer, a second polymer resin layer, an under bump metal layer, a solder ball and a protective film; the conductive column is positioned on the upper surface of the semiconductor chip; the epoxy resin layer is used for plastically packaging the semiconductor chip and the conductive columns and covering the side walls of the semiconductor chip, and the conductive columns are exposed on the upper surface of the epoxy resin layer; the first polymer resin layer is positioned on the upper surface of the epoxy resin layer; the metal wiring layer is positioned on the upper surface of the conductive column; the second polymer resin layer is positioned on the side wall and the upper surface of the metal wiring layer; the under bump metal layer is positioned in the groove of the metal wiring layer and extends to the upper surface of the second polymer resin layer; the solder ball is positioned on the upper surface of the under bump metal layer; the protective film is located on the lower surfaces of the semiconductor chip and the epoxy resin layer. Compared with the prior art, the utility model discloses help reducing the device size, reduce the consumption and improve the production yield.

Description

Semiconductor chip packaging structure

Technical Field

The utility model relates to a semiconductor chip package makes the field, especially relates to a semiconductor chip packaging structure.

Background

In order to accommodate more pins in a smaller package area, various novel Packaging methods have been developed, and Wafer level Chip Packaging (Wafer L ev Chip Scale Packaging, abbreviated as W L CSP) is one of them.

SUMMERY OF THE UTILITY MODEL

In view of the above shortcomings in the prior art, an object of the present invention is to provide a semiconductor chip package structure for solving the problems of complicated process flow of the wafer level chip package method in the prior art, high production cost, large structure of the fabricated device, high resistance and power consumption, low reliability of the device, etc.

To achieve the above and other related objects, the present invention provides a semiconductor chip package structure, which includes a semiconductor chip, a conductive pillar, an epoxy resin layer, a first polymer resin layer, a metal wiring layer, a second polymer resin layer, an under bump metal layer, a solder ball, and a protective film; the conductive column is positioned on the upper surface of the semiconductor chip and is electrically connected with the semiconductor chip; the epoxy resin layer plastically encapsulates the semiconductor chip and the conductive column and covers the side wall of the semiconductor chip, the lower surface of the epoxy resin layer is flush with the lower surface of the semiconductor chip, and the conductive column is exposed on the upper surface of the epoxy resin layer; the first polymer resin layer is positioned on the upper surface of the epoxy resin layer, an opening is formed in the first polymer resin layer, and the opening exposes the conductive column; the metal wiring layer is located on the upper surface of the conductive column and extends to the upper surface of the first polymer resin layer, and a groove is formed in the metal wiring layer corresponding to the surface of the conductive column; the second polymer resin layer is positioned on the side wall and the upper surface of the metal wiring layer; an opening is formed in the second polymer resin layer, and the opening exposes the groove of the metal wiring layer; the under bump metal layer is positioned in the groove of the metal wiring layer and extends to the upper surface of the second polymer resin layer; the solder balls are positioned on the upper surface of the under bump metal layer, and the upper surfaces of the solder balls are higher than the upper surface of the second polymer resin layer; the protective film is located on the lower surfaces of the semiconductor chip and the epoxy resin layer.

Optionally, the semiconductor chip package structure further includes a metal seed layer located between the semiconductor chip and the conductive pillar.

Optionally, the metal routing layer includes a first metal layer and a second metal layer, the first metal layer is located on the upper surface of the conductive pillar and extends to the upper surface of the second polymer resin layer, and the second metal layer is located on the upper surface of the first metal layer.

Optionally, the first metal layer includes a copper layer and a titanium layer, the copper layer is located on the upper surface of the conductive pillar and extends to the upper surface of the first polymer resin layer, the titanium layer is located on the upper surface of the copper layer, and the second metal layer includes an electroplated copper layer.

Alternatively, the openings in the first polymeric resin layer gradually increase from bottom to top.

Optionally, the thickness of the first polymer resin layer is less than the thickness of the epoxy resin layer.

Optionally, the conductive pillars comprise copper pillars.

Optionally, the material of the protective film includes one or both of epoxy resin and polyimide.

More optionally, the thickness of the protective film is 8 to 50 μm.

Compared with the prior art, the utility model discloses a semiconductor chip packaging structure carries out six (all around and the top and bottom) encapsulation that encapsulates entirely and obtains through the flow design of optimizing to the chip at the wafer size within range, not only helps reducing the device size, reduces the device consumption, improves the production yield, helps reducing encapsulation processing procedure, reduction in production cost and promotion production efficiency moreover. This application carries out the processing procedure of metal wiring layer before forming the solder ball, is favorable to the solder ball to arrange in the space to can combine the electrical property to come the position of comprehensive consideration metal wiring layer and solder ball, multilayer polymeric resin makes the adhesive force reinforcing of metal wiring layer, solder ball and epoxy layer moreover, and carries out the back protection to the device through the protection film in order to avoid steam infiltration, helps promoting device reliability and device performance, extension device life. Based on the utility model discloses a chip package structure of preparation method preparation has advantages such as miniaturization, low-power consumption and reliability height, has very big commercial value.

Drawings

Fig. 1 shows a flowchart of a method for manufacturing a semiconductor chip package structure according to the present invention.

Fig. 2 to 15 are schematic cross-sectional structural diagrams of steps of the manufacturing method shown in fig. 1, wherein fig. 15 is a schematic structural diagram of a finally manufactured semiconductor chip package structure of the present invention.

Description of the element reference numerals

11 semiconductor substrate

12 semiconductor chip

121 pad

13 conductive column

14 grooves

15 epoxy resin layer

16 first polymeric resin layer

161 opening

17 metal wiring layer

171 first metal layer

172 second metal layer

18 solder ball

19 protective film

20 metal seed layer

21 second polymeric resin layer

22 under bump metallurgy

S1-S12

Detailed Description

The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to fig. 1 to 15. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention in a schematic manner, and only the components related to the present invention are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of the components in actual implementation may be changed at will, and the layout of the components may be more complicated. It should be noted that the upper surface and the lower surface in this embodiment are only shown in a relative position and are not specific limitations on the device.

As shown in fig. 1, the present invention provides a semiconductor chip package structure, the manufacturing method thereof includes the following steps:

s1: providing a semiconductor substrate 11, wherein a plurality of semiconductor chips 12 are formed in the semiconductor substrate 11, as shown in fig. 2 specifically;

s2: forming a conductive pillar 13 on the upper surface of the semiconductor substrate 11 (more specifically, on the upper surface of the semiconductor chip 12), wherein the conductive pillar 13 is electrically connected to the semiconductor chip 12, as shown in fig. 3;

s3: forming a trench 14 in the semiconductor substrate 11, wherein the trench 14 is located between the semiconductor chips 12 and surrounds the semiconductor chips 12, as shown in fig. 4;

s4: forming an epoxy resin layer 15 on the surface of the structure obtained in step 3), wherein the epoxy resin layer 15 plastically molds the semiconductor chip 12 and the conductive pillars 13 and fills the trenches 14, and the conductive pillars 13 are exposed on the upper surface of the epoxy resin layer 15, that is, the upper surfaces of the conductive pillars 13 and the epoxy resin layer 15 are flush with each other, as shown in fig. 5 and 6;

s5: forming a first polymer resin layer 16 on the upper surface of the epoxy resin layer 15 and forming an opening 161 in the first polymer resin layer 16, wherein the opening 161 exposes the conductive pillar 13, as shown in fig. 7;

s6: forming a metal wiring layer 17 on the upper surface of the conductive pillar 13, where the metal wiring layer 17 extends to the upper surface of the first polymer resin layer 16, and a groove is formed in the metal wiring layer 17, as shown in fig. 8;

s7: forming a second polymer resin layer 21 on the sidewalls and the upper surface of the metal wiring layer 17, and forming an opening in the second polymer resin layer 21, wherein the opening exposes the groove of the metal wiring layer 17, as shown in fig. 9;

s8: forming an under bump metallurgy layer 22 in the groove of the metal wiring layer 17, wherein the under bump metallurgy layer 22 extends to the upper surface of the second polymer resin layer 21, as shown in fig. 10;

s9: forming solder balls 18 on the upper surfaces of the under bump metallurgy layers 22, wherein the upper surfaces of the solder balls 18 are higher than the upper surface of the second polymer resin layer 21, as shown in fig. 11;

s10: thinning the lower surface of the semiconductor substrate 11 until the epoxy resin layer 15 in the trench 14 is exposed, as shown in fig. 12;

s11: forming a protective film 19 on the lower surfaces of the semiconductor substrate 11 and the epoxy resin layer 15, as shown in fig. 13;

s12: cutting the structure obtained in step 11) from the trenches 14 of the semiconductor substrate 11 to obtain a plurality of mutually independent semiconductor chip package structures, as shown in fig. 14 and 15.

As an example, the semiconductor substrate 11 may be a silicon substrate, a germanium-silicon composite substrate, an SOI substrate, a sapphire substrate, a gallium nitride substrate, or the like; preferably, in this embodiment, the semiconductor substrate 11 is a silicon wafer. It should be noted that, typically, hundreds or thousands of semiconductor chips 12 are formed on the semiconductor substrate 11, and only a partial structure is illustrated in the schematic diagram. The semiconductor chips 12 are independent of each other, and a scribe line groove is generally formed between two adjacent semiconductor chips 12. Active and/or passive devices are formed on the semiconductor chip 12, a pad 121 for electrically leading out internal functional devices may be formed on the surface of the semiconductor chip 12, so that the semiconductor chip 12 is electrically connected with external devices, the upper surface of the pad 121 is exposed on the upper surface of the semiconductor chip 12, and the upper surface of the pad 121 is flush with the upper surface of the semiconductor chip 12. In the embodiment, a single semiconductor chip 12 has two pads 121 for example, but not limited thereto.

As an example, before forming the conductive pillars 13, a step of forming a metal seed layer 20 on the upper surface of the semiconductor substrate 11 (more precisely, on the upper surface of the semiconductor chip 12) is further included, the conductive pillars 13 are formed on the upper surface of the metal seed layer 20, the material of the metal seed layer 20 includes, but is not limited to, one or both of copper and titanium, and a method of forming the metal seed layer 20 includes, but is not limited to, a sputtering method. The formation of the metal seed layer 20 is beneficial to the formation of the subsequent conductive pillars 13, and is beneficial to improving the conductive performance of the conductive pillars 13. In the embodiment, the thickness of the metal seed layer 20 is 1 to 10 μm as an example. Because utility model people found through many times of experiments, when the thickness of metal seed layer 20 is too small, the electrically conductive and the adhesion that metal seed layer 20 played are not enough can lead to subsequent leading electrical pillar 13 to appear the gap, and when thickness was too big metal seed layer 20 self produces the hole easily and leads to the bad of device.

The conductive posts 13 are directly formed on the surface of the semiconductor chip 12, so that no obstacle exists, no adverse effect on other structures in the preparation process is worried about, and the alignment with the semiconductor chip 12, such as the accurate alignment with the bonding pads 121, can be realized. As an example, the material of the conductive pillar 13 includes, but is not limited to, copper, when the conductive pillar 13 is a copper pillar, the method for forming the conductive pillar 13 includes, but is not limited to, an electroplating method, and the use of copper electroplating is not only beneficial to shortening the process time, but also beneficial to enhancing the bonding force between the conductive pillar 13 and the metal seed layer 20 and the conductive capability of the conductive pillar 13, and is also beneficial to enhancing the corrosion resistance and the moisture resistance of the conductive pillar 13, and is beneficial to reducing the device resistance, reducing the device power consumption, and improving the device performance. In a further example, after the conductive pillar 13 is formed, high-temperature annealing may be performed, so that lattice defects of the conductive pillar 13 may be improved by annealing, stress and voids may be eliminated, and voids at an interface between electroplated copper and sputtered copper may also be eliminated, which is beneficial to improving the conductivity of the conductive pillar 13 and the metal wiring layer 17, and improving device performance. Of course, in other examples, the conductive pillar 13 may also be one or a combination of two or more of other metal materials such as aluminum, nickel, gold, silver, titanium, and the like, and the forming method thereof may also be one or more of a deposition method, an electroless plating method, and the like, and the embodiment is not limited strictly. The height and width of the conductive post 13 can be set according to the requirement, for example, 10 to 50 μm.

As an example, the method for forming the trench 14 in the semiconductor substrate 11 includes, but is not limited to, one or more of photolithography and laser etching. In the present embodiment, as an example, a laser is used to form the trench 14 between the adjacent semiconductor chips 12 from the scribe line groove. Compared with a photoetching method, laser etching is beneficial to simplifying the preparation process and reducing the production cost. And as an example, the depth of the trench 14 is 1/4-1/2 of the thickness of the semiconductor substrate 11, which not only can avoid damage and even fracture of the semiconductor substrate 11 during the cutting process, but also is beneficial for subsequent cutting, and ensures that the epoxy resin layer 15 formed subsequently is sufficiently protected to the semiconductor chip 12.

As an example, the step 4) includes the steps of:

forming an epoxy resin layer 15 on the surface of the structure obtained in step 3) by using one or more methods including, but not limited to, compression molding, transfer molding, liquid sealing molding, mold underfill, capillary underfill, vacuum lamination, spin coating, or the like, wherein the epoxy resin layer 15 plastically molds the semiconductor chip 12 and the conductive pillars 13 and fills the trenches 14, and the thickness of the epoxy resin layer 15 is 50 to 100 μm (inclusive, where a numerical range is referred to in this specification, unless otherwise specified) higher than the height of the conductive pillars 13; setting the thickness of the epoxy resin layer 15 to be 50-100 μm higher than the height of the conductive post 13 helps to ensure the thickness uniformity of the whole semiconductor substrate 11 and to fully meet the subsequent process requirements;

grinding the epoxy resin layer 15 until the conductive post 13 is exposed, wherein the surface roughness of the ground epoxy resin layer 15 is less than or equal to 0.2 μm; the surface roughness of the epoxy resin layer 15 after grinding is less than or equal to 0.2 μm, which is beneficial to the adhesion of the metal wiring layer 17, the solder balls 18 and the surface of the epoxy resin layer 15 formed in the subsequent process.

Of course, in other examples, the epoxy layer 15 may also be formed according to the top of the conductive pillar 13, so that the height of the formed epoxy layer 15 is just the same as the height of the conductive pillar 13 (the sum of the heights of the metal seed layer 20 and the conductive pillar 13 if the metal seed layer 20 is used). Therefore, the subsequent process of grinding the epoxy resin layer 15 can be omitted, the process steps can be reduced, and the production cost can be reduced.

By way of example, the first polymeric resin layer 16 may be formed by one or more of, but is not limited to, compression molding, transfer molding, liquid seal molding, mold underfill, capillary underfill, vacuum lamination, spin coating, or the like. The first polymer resin layer 16 is preferably polyimide (abbreviated as PI). Polyimide has higher heat resistance temperature than epoxy resin, and the first polymer resin layer 16 is formed before the metal wiring layer 17 is formed, so that the adhesion between the metal wiring layer 17 and the epoxy resin layer 15(EMC) is enhanced, the reliability and durability of the device are improved, and the service life of the device is prolonged. As an example, the thickness of the first polymer resin layer 16 is smaller than the thickness of the epoxy resin layer 15. The material and forming method of the second polymer resin layer 21 are preferably the same as those of the first polymer resin layer 16. The structure of the multi-layer polymer resin layer helps to enhance the adhesion among the metal wiring layer 17, the solder balls 18 and the epoxy resin layer 15, and helps to improve the durability of the device.

As an example, the method for forming the opening 161 in the first polymer resin layer 16 includes, but is not limited to, a photolithography etching method, and the opening 161 in the first polymer resin layer 16 is formed to be gradually enlarged from bottom to top, i.e. to be funnel-shaped, so as to facilitate the subsequent formation of the metal wiring layer 17.

As an example, the method of forming the metal wiring layer 17 includes:

forming a first metal layer 171 by sputtering in the opening 161 of the first polymer resin layer 16 and on the upper surface of the first polymer resin layer 16, wherein the first metal layer 171 is connected to the conductive pillar 13, and the material of the first metal layer 171 includes one or both of titanium and copper; methods of forming the first metal layer 171 include, but are not limited to, physical vapor deposition;

forming a second metal layer 172 by electroplating on the upper surface of the first metal layer 171, wherein the material of the second metal layer 172 includes copper, and the method for forming the second metal layer 172 includes, but is not limited to, electroplating; for example, the first metal layer 171 may include a titanium layer and a copper layer stacked from bottom to top, and the second metal layer 172 includes a copper layer, the titanium layer may function as an adhesion layer, and the first metal layer 171 and the second metal layer 172 each include copper, which helps to enhance adhesion between the first metal layer 171 and the second metal layer 172, and is beneficial to improve conductivity and stability of the metal wiring layer 17, and in a further example, after the second metal layer 172 is formed, a high temperature annealing may be performed, so that lattice defects, stress and voids are eliminated, and metal conductivity is improved.

Since the first metal layer 171 and the second metal layer 172 are formed on the entire surface of the first polymer resin layer 16 in the first two steps, etching the second metal layer 172 and the first metal layer 171 to separate the metal wiring layers 17 in the corresponding different openings from each other is further included, and the metal wiring layers 17 extend from the openings 161 to the upper surface of the first polymer resin layer 16, or the first metal layer 171 and the second metal layer 172 partially located on the upper surface of the first polymer resin layer 16 are remained, so as to facilitate the subsequent electrical connection between the metal wiring layers 17 and the solder balls 18. The metal wiring layer 17 does not fill the whole opening but is only located on the sidewall and the bottom of the opening, so that there is still a certain space in the opening, i.e. there is a groove in the metal wiring layer 17, of course, the groove may also be formed by etching a part of the metal wiring layer 17 in the groove after the metal wiring layer 17 is formed, and the groove is not only a space for accommodating the under bump metal layer 22, but also provides convenience for the subsequent process, such as positioning.

Of course, in other examples, the non-metal deposition region may be blocked by a mask or other structures to ensure that the metal wiring layer 17 is formed only in a predetermined region, which is not strictly limited in this embodiment.

As an example, the method of forming the under bump metal layer 22 includes, but is not limited to, an electroplating method, which is advantageous for precisely controlling the position of the under bump metal layer 22, such as in this example, the horizontal surface area of the under bump metal layer 22 on the second polymer resin layer 21 is the same as the horizontal surface area of the metal wiring layer 17 on the first polymer resin layer 16. The material of the under bump metallurgy layer 22 includes one or more of titanium, copper, nickel, tin, and silver, for example. In a further example, the under bump metal layer 22 includes, from bottom to top, a titanium layer (not shown), a copper layer, a nickel layer, and a silver-tin layer (not shown), wherein the titanium layer can function as an adhesion layer, and the nickel layer can protect the copper layer from oxidation, and the silver-tin layer facilitates the connection of the under bump metal layer 22 with subsequent bonding, and the provision of the composite structure helps to enhance the conductivity and stability of the under bump metal layer 22, thereby helping to improve the device performance. And annealing may be performed after the under bump metallurgy 22 is formed to improve crystal defects, relieve stress, and improve the conductivity of the under bump metallurgy 22.

As an example, the step of forming the solder balls 18 includes:

forming a metal bump on the upper surface of the under bump metallurgy layer 22, wherein the material of the metal bump includes but is not limited to one or a combination of two or more of copper, aluminum, nickel, gold, silver and titanium; nickel is preferred in this embodiment to facilitate subsequent heat reflow;

reflowing the metal bump to form the solder ball 18, in which the metal reflows to the recess of the under bump metal layer 22, which is beneficial to enhancing the adhesion between the solder ball 18 and the under bump metal layer 22;

the resulting structure is cleaned.

By way of example, the lower surface of the semiconductor substrate 11 may be thinned by methods including, but not limited to, chemical mechanical polishing until the epoxy layer 15 within the trench 14 is exposed. After grinding, the lower surface of the semiconductor substrate 11 and the lower surface of the epoxy resin layer 15 are flush.

As an example, the formation method of the protective film 19 differs depending on the material of the protective film 19. In this embodiment, as an example, the material of the protective film 19 includes one or two of epoxy resin and polyimide, which is beneficial to enhancing the adhesion between the protective film 19 and the epoxy resin layer 15. The thickness of the protective film 19 is 8-50 mu m, and the protective film 19 can effectively prevent water vapor and the like from permeating into a semiconductor device, and is beneficial to improving the reliability of the device.

As an example, the structure obtained in step 11) may be cut from the grooves 14 by a laser cutting method, including but not limited to, to obtain a plurality of mutually independent semiconductor chip package structures. Since the trench 14 is filled with the epoxy resin layer 15, after cutting, the side surface of the semiconductor chip 12 is covered by the epoxy resin layer 15, so that water vapor permeation can be effectively avoided, and the reliability and durability of the device can be improved.

Compared with the prior art, the utility model discloses carry out six encapsulation entirely and through the flow design of optimizing to the chip at wafer size within range, not only help reducing the device size, reduce the device consumption, improve the production yield, help reducing encapsulation processing procedure, reduction in production cost and promotion production efficiency moreover. Just the utility model discloses need not to use the carrier in the preparation process, help manufacturing cost's reduction. This application carries out the processing procedure of metal wiring layer before forming the solder ball, is favorable to the solder ball to arrange in the space to can combine the electrical property to come the position of comprehensive consideration metal wiring layer and solder ball, multilayer polymeric resin makes the adhesive force reinforcing of metal wiring layer, solder ball and epoxy layer moreover, and carries out the back protection to the device through the protection film in order to avoid steam infiltration, helps promoting device reliability and device performance, extension device life.

Fig. 15 is a semiconductor chip package structure finally provided by the present invention, which is prepared based on the foregoing preparation method, so that the foregoing contents can be fully referred to so far, and the same contents are not repeated as much as possible for the purpose of brevity. The semiconductor chip packaging structure comprises a semiconductor chip 12, a conductive column 13, an epoxy resin layer 15, a first polymer resin layer 16, a metal wiring layer 17, a second polymer resin layer 21, an under bump metal layer 22, a solder ball 18 and a protective film 19; the conductive posts 13 are located on the upper surface of the semiconductor chip 12, and the conductive posts 13 are electrically connected with the semiconductor chip 12; the epoxy resin layer 15 is used for plastically packaging the semiconductor chip 12 and the conductive posts 13 and covering the side walls of the semiconductor chip 12, the lower surface of the epoxy resin layer 15 is flush with the lower surface of the semiconductor chip 12, and the conductive posts 13 are exposed on the upper surface of the epoxy resin layer 15; the first polymer resin layer 16 is located on the upper surface of the epoxy resin layer 15, an opening 161 is formed in the first polymer resin layer 16, and the opening 161 exposes the conductive pillar 13; the metal wiring layer 17 is located on the upper surface of the conductive pillar 13 and extends to the upper surface of the first polymer resin layer 16, and a groove is formed on the metal wiring layer 17 corresponding to the surface of the conductive pillar 13; the second polymer resin layer 21 is located on the sidewall and the upper surface of the metal wiring layer 17; the second polymer resin layer 21 has an opening therein, and the opening exposes the groove of the metal wiring layer 17; the under bump metal layer 22 is located in the groove of the metal wiring layer 17 and extends to the upper surface of the second polymer resin layer 21; the solder balls 18 are located on the upper surface of the under bump metallurgy layer 22, and the upper surfaces of the solder balls 18 are higher than the upper surface of the second polymer resin layer 21; the protective film 19 is located on the lower surfaces of the semiconductor chip 12 and the epoxy layer 15.

Illustratively, the openings 161 in the first polymeric resin layer 16 gradually increase from bottom to top.

As an example, the semiconductor chip package structure further includes a metal seed layer 20 located between the semiconductor chip 12 and the conductive pillar 13.

As an example, the metal wiring layer 17 includes a first metal layer 171 and a second metal layer 172, the first metal layer 171 is located on the upper surface of the conductive pillar 13 and extends to the upper surface of the first polymer resin layer 16, and the second metal layer 172 is located on the upper surface of the first metal layer 171; the first metal layer 171 includes one of copper and titanium, and the second metal layer 172 includes electroplated copper.

In a further example, the first metal layer 171 includes a copper layer on the upper surface of the conductive post 13 and extending to the upper surface of the first polymeric resin layer 16, and a titanium layer on the upper surface of the copper layer, the second metal layer including an electroplated copper layer.

The protective film 19 includes one or both of an epoxy film and a polyimide film, by way of example, and in a further example, the protective film 19 has a thickness of 8 to 50 μm.

To sum up, the utility model provides a semiconductor chip packaging structure. The semiconductor chip packaging structure comprises a semiconductor chip, a conductive column, an epoxy resin layer, a first polymer resin layer, a metal wiring layer, a second polymer resin layer, an under bump metal layer, a solder ball and a protective film; the conductive column is positioned on the upper surface of the semiconductor chip and is electrically connected with the semiconductor chip; the epoxy resin layer plastically encapsulates the semiconductor chip and the conductive column and covers the side wall of the semiconductor chip, the lower surface of the epoxy resin layer is flush with the lower surface of the semiconductor chip, and the conductive column is exposed on the upper surface of the epoxy resin layer; the first polymer resin layer is positioned on the upper surface of the epoxy resin layer, an opening is formed in the first polymer resin layer, and the opening exposes the conductive column; the metal wiring layer is located on the upper surface of the conductive column and extends to the upper surface of the first polymer resin layer, and a groove is formed in the metal wiring layer corresponding to the surface of the conductive column; the second polymer resin layer is positioned on the side wall and the upper surface of the metal wiring layer; an opening is formed in the second polymer resin layer, and the opening exposes the groove of the metal wiring layer; the under bump metal layer is positioned in the groove of the metal wiring layer and extends to the upper surface of the second polymer resin layer; the solder balls are positioned on the upper surface of the under bump metal layer, and the upper surfaces of the solder balls are higher than the upper surface of the second polymer resin layer; the protective film is located on the lower surfaces of the semiconductor chip and the epoxy resin layer. Compared with the prior art, the utility model discloses a semiconductor chip packaging structure carries out six encapsulation that encapsulate entirely and obtains through the flow design of optimizing to the chip at the wafer size within range, not only helps reducing the device size, reduces the device consumption, improves the production yield, helps reducing encapsulation processing procedure, reduction in production cost and promotion production efficiency moreover. This application carries out the processing procedure of metal wiring layer before forming the solder ball, is favorable to the solder ball to arrange in the space to can combine the electrical property to come the position of comprehensive consideration metal wiring layer and solder ball, multilayer polymeric resin makes the adhesive force reinforcing of metal wiring layer, solder ball and epoxy layer moreover, and carries out the back protection to the device through the protection film in order to avoid steam infiltration, helps promoting device reliability and device performance, extension device life. Based on the utility model discloses a chip package structure of preparation method preparation has advantages such as miniaturization, low-power consumption and reliability height, has very big commercial value. Therefore, the utility model effectively overcomes various defects in the prior art and has higher industrial utilization value.

The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A semiconductor chip package structure, comprising:

a semiconductor chip;

the conductive column is positioned on the upper surface of the semiconductor chip and is electrically connected with the semiconductor chip;

the semiconductor chip and the conductive column are plastically packaged and cover the side wall of the semiconductor chip by the epoxy resin layer, the lower surface of the epoxy resin layer is flush with the lower surface of the semiconductor chip, and the conductive column is exposed on the upper surface of the epoxy resin layer;

a first polymer resin layer on the upper surface of the epoxy resin layer, the first polymer resin layer having an opening therein, the opening exposing the conductive post;

the metal wiring layer is positioned on the upper surface of the conductive column and extends to the upper surface of the first polymer resin layer, and a groove is formed in the metal wiring layer corresponding to the surface of the conductive column;

a second polymer resin layer on a sidewall and an upper surface of the metal wiring layer; an opening is formed in the second polymer resin layer, and the opening exposes the groove of the metal wiring layer;

an under bump metal layer located in the groove of the metal wiring layer and extending to an upper surface of the second polymer resin layer;

the solder balls are positioned on the upper surface of the under bump metal layer, and the upper surfaces of the solder balls are higher than the upper surface of the second polymer resin layer;

and a protective film positioned on the lower surfaces of the semiconductor chip and the epoxy resin layer.

2. The semiconductor chip package structure according to claim 1, wherein: the semiconductor chip packaging structure further comprises a metal seed layer located between the semiconductor chip and the conductive column.

3. The semiconductor chip package structure according to claim 1, wherein: the metal wiring layer includes a first metal layer and a second metal layer, the first metal layer is located on the upper surface of the conductive pillar and extends to the upper surface of the second polymer resin layer, and the second metal layer is located on the upper surface of the first metal layer.

4. The semiconductor chip package structure according to claim 3, wherein: the first metal layer includes a copper layer and a titanium layer, the copper layer is located on the upper surface of the conductive post and extends to the upper surface of the first polymer resin layer, the titanium layer is located on the upper surface of the copper layer, and the second metal layer includes an electroplated copper layer.

5. The semiconductor chip package structure according to claim 1, wherein: the openings in the first polymeric resin layer gradually increase from bottom to top.

6. The semiconductor chip package structure according to claim 1, wherein: the thickness of the first polymer resin layer is less than the thickness of the epoxy resin layer.

7. The semiconductor chip package structure according to claim 1, wherein: the conductive post comprises a copper post.

8. The semiconductor chip package structure according to any one of claims 1 to 7, wherein: the protective film includes one or both of an epoxy film and a polyimide film.

9. The semiconductor chip package structure according to claim 8, wherein: the thickness of the protective film is 8-50 mu m.