CN113130412A - Semiconductor chip packaging structure and preparation method thereof - Google Patents

Semiconductor chip packaging structure and preparation method thereof Download PDF

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Publication number
CN113130412A
CN113130412A CN201911387521.6A CN201911387521A CN113130412A CN 113130412 A CN113130412 A CN 113130412A CN 201911387521 A CN201911387521 A CN 201911387521A CN 113130412 A CN113130412 A CN 113130412A
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Prior art keywords
resin layer
semiconductor chip
layer
forming
epoxy resin
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徐罕
陈彦亨
吴政达
林正忠
高建章
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SJ Semiconductor Jiangyin Corp
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Shenghejing Micro Semiconductor Jiangyin Co Ltd
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Priority to CN201911387521.6A priority Critical patent/CN113130412A/en
Publication of CN113130412A publication Critical patent/CN113130412A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention provides a semiconductor chip packaging structure and a preparation method thereof. The preparation method comprises the following steps: providing a semiconductor substrate, wherein a plurality of semiconductor chips are formed in the semiconductor substrate; forming a conductive column which is electrically connected with the semiconductor chip; forming a groove which is positioned between the semiconductor chips and surrounds the semiconductor chips; forming an epoxy resin layer, wherein the semiconductor chip and the conductive columns are plastically packaged and filled in the grooves by the epoxy resin layer, and the conductive columns are exposed on the upper surface of the epoxy resin layer; forming a polymer resin layer; forming an opening in the polymer resin layer, wherein the opening exposes the conductive post; forming an under bump metal layer; forming a solder ball; thinning the lower surface of the semiconductor substrate until the epoxy resin layer is exposed; forming a protective film on the lower surfaces of the semiconductor substrate and the epoxy resin layer; and cutting to obtain a plurality of mutually independent semiconductor chip packaging structures. The invention is beneficial to reducing the size of the device, reducing the power consumption of the device and prolonging the service life of the device.

Description

Semiconductor chip packaging structure and preparation method thereof
Technical Field
The invention relates to the field of semiconductor chip packaging and manufacturing, in particular to a semiconductor chip packaging structure and a preparation method thereof.
Background
With the rapid development of electronic information technology and the increasing demand of consumers, electronic products are becoming light, multifunctional and low-power-consumption. In order to accommodate a larger pin count in a smaller package area, various novel Packaging methods are developed, and Wafer Level Chip package (WLCSP) is one of them. The so-called wafer level chip package is as a name, firstly, the package and the test are performed on the whole wafer, and then, the wafer is cut into individual chip particles. In the conventional wafer-level chip package, a redistribution layer is formed on a wafer, a plastic package material layer is formed on the redistribution layer, a through hole is formed in the plastic package material layer, and a metal electrically connected with the redistribution layer is filled in the through hole to electrically conduct out a device. The traditional packaging method has the disadvantages of complex process, increased production cost and poor device performance, dislocation is easily caused in the process of forming the rewiring layer and the process of forming the opening in the plastic packaging material layer, the device is difficult to be accurately and electrically connected with a chip, the device performance is reduced due to large resistance of the device caused by easy filling defects in the process of filling metal in the opening, and the poor adhesion among the structural layers causes water vapor to easily permeate into the packaging structure, so that the reliability and the service life of the device are reduced. Meanwhile, the structure packaged by the traditional method is ordinary and large, which is contrary to the market demand of miniaturization of devices and easily causes the defects of high power consumption of the devices and the like. In addition, in the existing wafer-level chip packaging process, the chips are generally cut and separated by the carrier, which leads to an increase in production cost.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a semiconductor chip package structure and a method for manufacturing the same, which are used to solve the problems that the wafer level chip package method in the prior art has a complicated process flow, resulting in a high production cost, and the manufactured device has a large structure, high resistance and power consumption, and reduced reliability.
In order to achieve the above and other related objects, the present invention provides a semiconductor chip package structure, which includes a semiconductor chip, a conductive pillar, an epoxy layer, a polymer resin layer, an under bump metallurgy layer, a solder ball and a protection film; the conductive column is positioned on the upper surface of the semiconductor chip and is electrically connected with the semiconductor chip; the epoxy resin layer plastically encapsulates the semiconductor chip and the conductive column and covers the side wall of the semiconductor chip, the lower surface of the epoxy resin layer is flush with the lower surface of the semiconductor chip, and the conductive column is exposed on the upper surface of the epoxy resin layer; the polymer resin layer is positioned on the upper surface of the epoxy resin layer, an opening is formed in the polymer resin layer, and the opening exposes the conductive column; the under bump metal layer is positioned on the upper surface of the conductive pillar and extends to the upper surface of the polymer resin layer; the solder balls are positioned on the upper surface of the under bump metal layer, and the upper surfaces of the solder balls are higher than the upper surface of the polymer resin layer; the protective film is located on the lower surfaces of the semiconductor chip and the epoxy resin layer.
Optionally, the semiconductor chip package structure further includes a metal seed layer located between the semiconductor chip and the conductive pillar.
Optionally, the under bump metallurgy layer includes a first metal layer and a second metal layer, the first metal layer is located on the upper surface of the conductive pillar and extends to the upper surface of the polymer resin layer, and the second metal layer is located on the upper surface of the first metal layer; the first metal layer comprises one of copper and titanium, and the second metal layer comprises electroplated copper.
Optionally, the protective film comprises a resin film, and the thickness of the protective film is 8-50 μm.
The invention also provides a preparation method of the semiconductor chip packaging structure, which comprises the following steps:
1) providing a semiconductor substrate, wherein a plurality of semiconductor chips are formed in the semiconductor substrate;
2) forming a conductive column on the upper surface of the semiconductor substrate, wherein the conductive column is electrically connected with the semiconductor chip;
3) forming a groove in the semiconductor substrate, wherein the groove is positioned between the semiconductor chips and surrounds the semiconductor chips;
4) forming an epoxy resin layer on the surface of the structure obtained in the step 3), wherein the semiconductor chip and the conductive columns are plastically packaged and filled in the grooves by the epoxy resin layer, and the conductive columns are exposed on the upper surface of the epoxy resin layer;
5) forming a polymer resin layer on the upper surface of the epoxy resin layer;
6) forming an opening in the polymer resin layer, the opening exposing the conductive post;
7) forming an under bump metallurgy layer on the upper surface of the conductive pillar, wherein the under bump metallurgy layer extends to the upper surface of the polymer resin layer;
8) forming a solder ball on the upper surface of the under bump metal layer, wherein the upper surface of the solder ball is higher than the upper surface of the polymer resin layer;
9) thinning the lower surface of the semiconductor substrate until the epoxy resin layer in the groove is exposed;
10) forming a protective film on the lower surfaces of the semiconductor substrate and the epoxy resin layer;
11) cutting the structure obtained in the step 10) from the grooves to obtain a plurality of mutually independent semiconductor chip packaging structures.
Optionally, before forming the conductive pillars, a step of forming a metal seed layer on the upper surface of the semiconductor substrate is further included, and the conductive pillars are formed on the upper surface of the metal seed layer.
Optionally, step 4) comprises:
forming an epoxy resin layer on the surface of the structure obtained in the step 3), wherein the semiconductor chip and the conductive column are plastically packaged and the groove is filled with the epoxy resin layer, and the thickness of the epoxy resin layer is 50-100 micrometers higher than the height of the conductive column;
and grinding the epoxy resin layer until the conductive post is exposed, wherein the surface roughness of the ground epoxy resin layer is less than or equal to 0.2 mu m.
Optionally, the method for forming the under bump metallurgy layer includes:
forming a first metal layer in the opening and on the upper surface of the polymer resin layer by sputtering, wherein the first metal layer is connected with the conductive post, and the material of the first metal layer comprises one or two of titanium and copper;
electroplating the upper surface of the first metal layer to form a second metal layer, wherein the material of the second metal layer comprises copper;
and etching the second metal layer and the first metal layer to mutually disconnect the under bump metal layers in the corresponding different openings, wherein the under bump metal layers extend to the upper surface of the polymer resin layer from the openings.
Optionally, the step of forming the solder balls comprises:
forming a metal bump on the upper surface of the under bump metal layer;
reflowing the metal bump to form the solder ball;
the resulting structure is cleaned.
Optionally, the depth of the trench formed in the step 3) is 1/4-1/2 of the thickness of the semiconductor substrate.
Compared with the prior art, the semiconductor chip packaging structure and the preparation method thereof have the advantages that six surfaces of the chip are packaged in a full packaging mode within the wafer size range, and through the optimized flow design, the size of a device is reduced, the power consumption of the device is reduced, the production yield is improved, the packaging process is reduced, the production cost is reduced, and the production efficiency is improved. This application adds the process of polyimide before the metal process under the lug, can make metal level and epoxy adhesive force reinforcing under the lug to carry out the back protection through the protection film to the device in order to avoid the steam infiltration, help promoting the device performance, extension device life. The chip packaging structure prepared based on the preparation method has the advantages of miniaturization, low power consumption, high reliability and the like, and has great commercial value.
Drawings
Fig. 1 is a flowchart illustrating a method for manufacturing a semiconductor chip package structure according to the present invention.
Fig. 2 to 13 are schematic cross-sectional views of steps of the manufacturing method of fig. 1, wherein fig. 13 is a schematic structural view of a finally manufactured semiconductor chip package structure according to the present invention.
Description of the element reference numerals
11 semiconductor substrate
12 semiconductor chip
121 pad
13 conductive column
14 grooves
15 epoxy resin layer
16 polymer resin layer
161 opening
17 under bump metallurgy
171 first metal layer
172 second metal layer
18 solder ball
19 protective film
20 metal seed layer
S1-S11
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 13. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated. It should be noted that the upper surface and the lower surface in this embodiment are only shown in a relative position and are not specific limitations on the device.
As shown in fig. 1, the present invention provides a method for manufacturing a semiconductor chip package structure, which includes the following steps:
s1: providing a semiconductor substrate 11, wherein a plurality of semiconductor chips 12 are formed in the semiconductor substrate 11, as shown in fig. 2 specifically;
s2: forming a conductive pillar 13 on the upper surface of the semiconductor substrate 11 (more specifically, on the upper surface of the semiconductor chip 12), wherein the conductive pillar 13 is electrically connected to the semiconductor chip 12, as shown in fig. 3;
s3: forming a trench 14 in the semiconductor substrate 11, wherein the trench 14 is located between the semiconductor chips 12 and surrounds the semiconductor chips 12, as shown in fig. 4;
s4: forming an epoxy resin layer 15 on the surface of the structure obtained in step 3), wherein the epoxy resin layer 15 plastically molds the semiconductor chip 12 and the conductive pillars 13 and fills the trenches 14, and the conductive pillars 13 are exposed on the upper surface of the epoxy resin layer 15, that is, the upper surfaces of the conductive pillars 13 and the epoxy resin layer 15 are flush with each other, as shown in fig. 5 and 6;
s5: forming a polymer resin layer 16 on the upper surface of the epoxy resin layer 15;
s6: forming an opening 161 in the polymer resin layer 16, wherein the opening 161 exposes the conductive pillar 13, as shown in fig. 7;
s7: forming an under bump metallurgy 17 on the upper surface of the conductive pillar 13 (the under bump metallurgy 17 is in contact with the conductive pillar 13), where the under bump metallurgy 17 extends to the upper surface of the polymer resin layer 16, as shown in fig. 8;
s8: forming a solder ball 18 on the upper surface of the under bump metallurgy 17 (the solder ball 18 contacts the under bump metallurgy 17), wherein the upper surface of the solder ball 18 (the height is the upper surface of the highest position of the solder ball 18 because the solder ball 18 is approximately circular) is higher than the upper surface of the polymer resin layer 16, as shown in fig. 9;
s9: thinning the lower surface of the semiconductor substrate 11 until the epoxy resin layer 15 in the trench 14 is exposed, as shown in fig. 10;
s10: forming a protective film 19 on the lower surfaces of the semiconductor substrate 11 and the epoxy resin layer 15, as shown in fig. 11;
s11: cutting the structure obtained in step 10) from the grooves 14 to obtain a plurality of mutually independent semiconductor chip package structures, as shown in fig. 12 and 13.
As an example, the semiconductor substrate 11 may be a silicon substrate, a germanium-silicon composite substrate, an SOI substrate, a sapphire substrate, a gallium nitride substrate, or the like; preferably, in this embodiment, the semiconductor substrate 11 is a silicon wafer. It should be noted that, typically, hundreds or thousands of semiconductor chips 12 are formed on the semiconductor substrate 11, and only a partial structure is illustrated in the schematic diagram. The semiconductor chips 12 are independent of each other, and a scribe line groove is generally formed between two adjacent semiconductor chips 12. Active and/or passive devices are formed on the semiconductor chip 12, a pad 121 for electrically leading out internal functional devices may be formed on the surface of the semiconductor chip 12, so that the semiconductor chip 12 is electrically connected with external devices, the upper surface of the pad 121 is exposed on the upper surface of the semiconductor chip 12, and the upper surface of the pad 121 is flush with the upper surface of the semiconductor chip 12. In the embodiment, a single semiconductor chip 12 has two pads 121 for example, but not limited thereto.
As an example, before forming the conductive pillars 13, a step of forming a metal seed layer 20 on the upper surface of the semiconductor substrate 11 is further included, the conductive pillars 13 are formed on the upper surface of the metal seed layer 20, the material of the metal seed layer 20 includes, but is not limited to, one or both of copper and titanium, and a method of forming the metal seed layer 20 includes, but is not limited to, a sputtering method. The formation of the metal seed layer 20 is beneficial to the formation of the subsequent conductive pillars 13, and is beneficial to improving the conductive performance of the conductive pillars 13. In the embodiment, the thickness of the metal seed layer 20 is 1 to 10 μm as an example. As the inventor finds out through multiple experiments, when the thickness of the metal seed layer 20 is too small, the conductive property and the adhesion property of the metal seed layer 20 are insufficient, which may cause gaps to occur in the subsequent conductive pillars 13, and when the thickness is too large, the metal seed layer 20 itself is easy to generate holes, which may cause device defects.
The conductive posts 13 are directly formed on the surface of the semiconductor chip 12, so that no obstacle exists, no adverse effect on other structures in the preparation process is worried about, and the alignment with the semiconductor chip 12, such as the accurate alignment with the bonding pads 121, can be realized. As an example, the material of the conductive pillar 13 includes, but is not limited to, copper, when the conductive pillar 13 is a copper pillar, the method for forming the conductive pillar 13 includes, but is not limited to, an electroplating method, and the use of copper electroplating is not only beneficial to shortening the process time, but also beneficial to enhancing the bonding force between the conductive pillar 13 and the metal seed layer 20 and the conductive capability of the conductive pillar 13, and is also beneficial to enhancing the corrosion resistance and the moisture resistance of the conductive pillar 13, and is beneficial to reducing the device resistance, reducing the device power consumption, and improving the device performance. In a further example, after the conductive pillar 13 is formed, high-temperature annealing may be performed, so that lattice defects of the conductive pillar 13 may be improved by annealing, stress and voids may be eliminated, and voids at an interface between electroplated copper and sputtered copper may also be eliminated, which is beneficial to improving the conductivity of the conductive pillar 13 and the under bump metal layer 17, and improving device performance. Of course, in other examples, the conductive pillar 13 may also be one or a combination of two or more of other metal materials such as aluminum, nickel, gold, silver, titanium, and the like, and the forming method thereof may also be one or more of a deposition method, an electroless plating method, and the like, and the embodiment is not limited strictly. The height and width of the conductive post 13 can be set according to the requirement, for example, 10 to 50 μm.
As an example, the method for forming the trench 14 in the semiconductor substrate 11 includes, but is not limited to, one or more of photolithography and laser etching. In the present embodiment, as an example, a laser is used to form the trench 14 between the adjacent semiconductor chips 12 from the scribe line groove. Compared with a photoetching method, the preparation method is beneficial to simplifying the preparation process and reducing the production cost. And as an example, the depth of the trench 14 is 1/4-1/2 of the thickness of the semiconductor substrate 11, which not only can avoid damage and even fracture of the semiconductor substrate 11 during the cutting process, but also is beneficial for subsequent cutting, and ensures that the epoxy resin layer 15 formed subsequently is sufficiently protected to the semiconductor chip 12.
As an example, the step 4) includes the steps of:
forming an epoxy resin layer 15 on the surface of the structure obtained in step 3) by using one or more methods including, but not limited to, compression molding, transfer molding, liquid sealing molding, mold underfill, capillary underfill, vacuum lamination, spin coating, or the like, wherein the epoxy resin layer 15 plastically molds the semiconductor chip 12 and the conductive pillars 13 and fills the trenches 14, and the thickness of the epoxy resin layer 15 is 50 to 100 μm (inclusive, where a numerical range is referred to in this specification, unless otherwise specified) higher than the height of the conductive pillars 13; setting the thickness of the epoxy resin layer 15 to be 50-100 μm higher than the height of the conductive post 13 helps to ensure the thickness uniformity of the whole semiconductor substrate 11 and to fully meet the subsequent process requirements;
grinding the epoxy resin layer 15 until the conductive post 13 is exposed, wherein the surface roughness of the ground epoxy resin layer 15 is less than or equal to 0.2 μm; the surface roughness of the polished epoxy layer 15 is less than or equal to 0.2 μm, which is favorable for the adhesion of the Under Bump Metallurgy (UBM) 17 formed in the subsequent process, the solder balls 18 and the surface of the epoxy layer 15.
Of course, in other examples, the epoxy layer 15 may also be formed according to the top of the conductive pillar 13, so that the height of the formed epoxy layer 15 is just the same as the height of the conductive pillar 13 (the sum of the heights of the metal seed layer 20 and the conductive pillar 13 if the metal seed layer 20 is used). Therefore, the subsequent process of grinding the epoxy resin layer 15 can be omitted, the process steps can be reduced, and the production cost can be reduced.
By way of example, the polymeric resin layer 16 may be formed by one or more of, but is not limited to, compression molding, transfer molding, liquid seal molding, mold underfill, capillary underfill, vacuum lamination, spin coating, or the like. The polymer resin layer 16 is preferably polyimide (abbreviated as PI). The polyimide has higher heat resistance temperature than the epoxy resin, and the polymer resin layer 16 is formed before the under bump metal layer 17 is formed, which helps to enhance the adhesion between the under bump metal layer 17 and the epoxy resin layer 15(EMC), and helps to improve the reliability and durability of the device, thereby helping to prolong the service life of the device. Illustratively, the thickness of the polymer resin layer 16 is less than the thickness of the epoxy resin layer 15.
As an example, the method for forming the opening 161 in the polymer resin layer 16 includes, but is not limited to, a photolithography etching method, and the opening 161 is formed to be gradually enlarged from bottom to top, i.e. in a funnel shape, so as to facilitate the formation of the under bump metallurgy layer 17.
As an example, the method of forming the under bump metallurgy 17 includes:
forming a first metal layer 171 by sputtering in the opening 161 and on the upper surface of the polymer resin layer 16, where the first metal layer 171 is connected to the conductive pillar 13, and a material of the first metal layer 171 includes one or both of titanium and copper; methods of forming the first metal layer 171 include, but are not limited to, physical vapor deposition;
forming a second metal layer 172 by electroplating on the upper surface of the first metal layer 171, wherein the material of the second metal layer 172 includes copper, and the method for forming the second metal layer 172 includes, but is not limited to, electroplating; for example, the first metal layer 171 may include a titanium layer and a copper layer stacked from bottom to top, and the second metal layer 172 includes a copper layer, the titanium layer may serve as an adhesion layer, and the first metal layer 171 and the second metal layer 172 both include copper, which helps to enhance adhesion between the first metal layer 171 and the second metal layer 172, and is beneficial to improve conductivity and stability of the under bump metal layer 17, and in a further example, after the second metal layer 172 is formed, a high temperature annealing may be performed, so that lattice defects, stress and voids are eliminated, and metal conductivity is improved.
Since the first metal layer 171 and the second metal layer 172 are formed on the entire surface of the polymer resin layer 16 in the first two steps, etching the second metal layer 172 and the first metal layer 171 to separate the under bump metallurgy 17 in the corresponding different openings 161 from each other is further performed, and the under bump metallurgy 17 extends from the opening 161 to the upper surface of the polymer resin layer 16, or the first metal layer 171 and the second metal layer 172 partially located on the upper surface of the polymer resin layer 16 are remained, so as to facilitate the subsequent electrical connection between the under bump metallurgy 17 and the solder ball 18. The under bump metallurgy 17 does not fill the whole opening 161 but only locates at the sidewall and bottom of the opening 161, so there is a certain space in the opening 161, and the space is filled by the following solder balls 18, which helps to enhance the stability of the solder balls 18 and improve the device performance.
Of course, in other examples, the under bump metallurgy layer 17 may be formed only in a predetermined region by shielding the non-metal deposition region with a mask or the like, which is not limited in this embodiment.
As an example, the step of forming the solder balls 18 includes:
forming a metal bump on the upper surface of the under bump metallurgy layer 17, wherein the material of the metal bump includes but is not limited to one or a combination of two or more of copper, aluminum, nickel, gold, silver and titanium; nickel is preferred in this embodiment to facilitate subsequent heat reflow;
reflowing the metal bumps to form the solder balls 18;
the resulting structure is cleaned.
By way of example, the lower surface of the semiconductor substrate 11 may be thinned by methods including, but not limited to, chemical mechanical polishing until the epoxy layer 15 within the trench 14 is exposed. After grinding, the lower surface of the semiconductor substrate 11 and the lower surface of the epoxy resin layer 15 are flush.
As an example, the formation method of the protective film 19 differs depending on the material of the protective film 19. In the embodiment, the protective film 19 is a resin film, and the thickness of the protective film 19 is 8-50 μm, so that moisture and the like can be effectively prevented from permeating into the semiconductor device, and the reliability of the device can be improved.
As an example, the structure obtained in step 10) may be cut from the grooves 14 by a laser cutting method, including but not limited to, to obtain a plurality of mutually independent semiconductor chip package structures. Since the trench 14 is filled with the epoxy resin layer 15, after cutting, the side surface of the semiconductor chip 12 is covered by the epoxy resin layer 15, so that water vapor permeation can be effectively avoided, and the reliability and durability of the device can be improved.
Compared with the prior art, the preparation method disclosed by the invention has the advantages that six surfaces of the chip are packaged in a full encapsulation mode within the wafer size range, and the optimized flow design is adopted, so that the size of a device is reduced, the power consumption of the device is reduced, the production yield is improved, the packaging process is reduced, the production cost is reduced, and the production efficiency is improved. In addition, the preparation process of the invention does not need to use a carrier, thereby being beneficial to reducing the production cost. This application adds the process of polyimide before the process of metal level under the lug, can make metal level under the lug and epoxy layer adhesive force reinforcing to carry out the back protection through the protection film to the device in order to avoid the steam infiltration, help promoting the device performance, extension device life.
As shown in fig. 13, the present invention further provides a semiconductor chip package structure, which is prepared based on any one of the preparation methods, so that the above description can be fully referred to, and the same contents are not repeated as much as possible for the sake of brevity. The semiconductor chip packaging structure comprises a semiconductor chip 12, a conductive column 13, an epoxy resin layer 15, a polymer resin layer 16, an under bump metal layer 17, a solder ball 18 and a protective film 19; the conductive posts 13 are located on the upper surface of the semiconductor chip 12, and the conductive posts 13 are electrically connected with the semiconductor chip 12; the epoxy resin layer 15 is used for plastically packaging the semiconductor chip 12 and the conductive posts 13 and covering the side walls of the semiconductor chip 12, the lower surface of the epoxy resin layer 15 is flush with the lower surface of the semiconductor chip 12, and the conductive posts 13 are exposed on the upper surface of the epoxy resin layer 15; the polymer resin layer 16 is located on the upper surface of the epoxy resin layer 15, an opening 161 is formed in the polymer resin layer 16, and the conductive post 13 is exposed by the opening 161; the under bump metallurgy 17 is located on the upper surface of the conductive pillar 13 and extends to the upper surface of the polymer resin layer 16; the solder balls 18 are located on the upper surface of the under bump metallurgy 17, and the upper surfaces of the solder balls 18 are higher than the upper surface of the polymer resin layer 16; the protective film 19 is located on the lower surfaces of the semiconductor chip 12 and the epoxy layer 15.
As an example, the opening 161 is gradually enlarged from the bottom up.
As an example, the semiconductor chip package structure further includes a metal seed layer 20 located between the semiconductor chip 12 and the conductive pillar 13.
As an example, the under bump metallurgy 17 includes a first metal layer 171 and a second metal layer 172, the first metal layer 171 is located on the upper surface of the conductive pillar 13 and extends to the upper surface of the polymer resin layer 16, and the second metal layer 172 is located on the upper surface of the first metal layer 171; the first metal layer 171 includes one of copper and titanium, and the second metal layer 172 includes electroplated copper.
In a further example, the first metal layer 171 includes a titanium layer and a copper layer stacked on top of each other, the copper layer being located on an upper surface of the titanium layer.
Illustratively, the protective film 19 includes a resin film, and the protective film 19 has a thickness of 8 to 50 μm.
In summary, the present invention provides a semiconductor chip package structure and a method for fabricating the same. The semiconductor chip packaging structure comprises a semiconductor chip, a conductive column, an epoxy resin layer, a polymer resin layer, an under bump metal layer, a solder ball and a protective film; the conductive column is positioned on the upper surface of the semiconductor chip and is electrically connected with the semiconductor chip; the epoxy resin layer plastically encapsulates the semiconductor chip and the conductive column and covers the side wall of the semiconductor chip, the lower surface of the epoxy resin layer is flush with the lower surface of the semiconductor chip, and the conductive column is exposed on the upper surface of the epoxy resin layer; the polymer resin layer is positioned on the upper surface of the epoxy resin layer, an opening is formed in the polymer resin layer, and the opening exposes the conductive column; the under bump metal layer is positioned on the upper surface of the conductive pillar and extends to the upper surface of the polymer resin layer; the solder balls are positioned on the upper surface of the under bump metal layer, and the upper surfaces of the solder balls are higher than the upper surface of the polymer resin layer; the protective film is located on the lower surfaces of the semiconductor chip and the epoxy resin layer. Compared with the prior art, the semiconductor chip packaging structure and the preparation method thereof have the advantages that six surfaces of the chip are packaged in a full packaging mode within the wafer size range, and through the optimized flow design, the size of a device is reduced, the power consumption of the device is reduced, the production yield is improved, the packaging process is reduced, the production cost is reduced, and the production efficiency is improved. This application adds the process of polyimide before the metal process under the lug, can make metal level and epoxy adhesive force reinforcing under the lug to carry out the back protection to the device through the protection film and in order to avoid the steam infiltration, help promoting the device performance, extension device life. The chip packaging structure prepared based on the preparation method has the advantages of miniaturization, low power consumption, high reliability and the like, and has great commercial value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. A semiconductor chip package structure, comprising:
a semiconductor chip;
the conductive column is positioned on the upper surface of the semiconductor chip and is electrically connected with the semiconductor chip;
the semiconductor chip and the conductive column are plastically packaged and cover the side wall of the semiconductor chip by the epoxy resin layer, the lower surface of the epoxy resin layer is flush with the lower surface of the semiconductor chip, and the conductive column is exposed on the upper surface of the epoxy resin layer;
a polymer resin layer on the upper surface of the epoxy resin layer, the polymer resin layer having an opening therein, the opening exposing the conductive post;
an under bump metallurgy layer located on the upper surface of the conductive pillar and extending to the upper surface of the polymer resin layer;
the solder ball is positioned on the upper surface of the under bump metal layer, and the upper surface of the solder ball is higher than the upper surface of the polymer resin layer;
and a protective film positioned on the lower surfaces of the semiconductor chip and the epoxy resin layer.
2. The semiconductor chip package structure according to claim 1, wherein: the semiconductor chip packaging structure further comprises a metal seed layer located between the semiconductor chip and the conductive column.
3. The semiconductor chip package structure according to claim 1, wherein: the under bump metallurgy includes a first metal layer and a second metal layer, the first metal layer is located on the upper surface of the conductive pillar and extends to the upper surface of the polymer resin layer, and the second metal layer is located on the upper surface of the first metal layer; the first metal layer comprises one of copper and titanium, and the second metal layer comprises electroplated copper.
4. The semiconductor chip package structure according to any one of claims 1 to 3, wherein: the protective film comprises a resin film, and the thickness of the protective film is 8-50 mu m.
5. A preparation method of a semiconductor chip packaging structure is characterized by comprising the following steps:
1) providing a semiconductor substrate, wherein a plurality of semiconductor chips are formed in the semiconductor substrate;
2) forming a conductive column on the upper surface of the semiconductor substrate, wherein the conductive column is electrically connected with the semiconductor chip;
3) forming a groove in the semiconductor substrate, wherein the groove is positioned between the semiconductor chips and surrounds the semiconductor chips;
4) forming an epoxy resin layer on the surface of the structure obtained in the step 3), wherein the semiconductor chip and the conductive columns are plastically packaged and filled in the grooves by the epoxy resin layer, and the conductive columns are exposed on the upper surface of the epoxy resin layer;
5) forming a polymer resin layer on the upper surface of the epoxy resin layer;
6) forming an opening in the polymer resin layer, the opening exposing the conductive post;
7) forming an under bump metallurgy layer on the upper surface of the conductive pillar, wherein the under bump metallurgy layer extends to the upper surface of the polymer resin layer;
8) forming a solder ball on the upper surface of the under bump metal layer, wherein the upper surface of the solder ball is higher than the upper surface of the polymer resin layer;
9) thinning the lower surface of the semiconductor substrate until the epoxy resin layer in the groove is exposed;
10) forming a protective film on the lower surfaces of the semiconductor substrate and the epoxy resin layer;
11) cutting the structure obtained in the step 10) from the grooves to obtain a plurality of mutually independent semiconductor chip packaging structures.
6. The method of manufacturing a semiconductor chip package structure according to claim 5, wherein: before forming the conductive pillar, a step of forming a metal seed layer on the upper surface of the semiconductor substrate is further included, and the conductive pillar is formed on the upper surface of the metal seed layer.
7. The method for manufacturing the semiconductor chip package structure according to claim 5, wherein the step 4) comprises:
forming an epoxy resin layer on the surface of the structure obtained in the step 3), wherein the semiconductor chip and the conductive column are plastically packaged and the groove is filled with the epoxy resin layer, and the thickness of the epoxy resin layer is 50-100 micrometers higher than the height of the conductive column;
and grinding the epoxy resin layer until the conductive post is exposed, wherein the surface roughness of the ground epoxy resin layer is less than or equal to 0.2 mu m.
8. The method of manufacturing the semiconductor chip package structure according to claim 5, wherein the method of forming the under bump metallurgy layer comprises:
forming a first metal layer in the opening and on the upper surface of the polymer resin layer by sputtering, wherein the first metal layer is connected with the conductive post, and the material of the first metal layer comprises one or two of titanium and copper;
electroplating the upper surface of the first metal layer to form a second metal layer, wherein the material of the second metal layer comprises copper;
and etching the second metal layer and the first metal layer to mutually disconnect the under bump metal layers in the corresponding different openings, wherein the under bump metal layers extend to the upper surface of the polymer resin layer from the openings.
9. The method of manufacturing a semiconductor chip package structure according to claim 6, wherein: the step of forming the solder balls includes:
forming a metal bump on the upper surface of the under bump metal layer;
reflowing the metal bump to form the solder ball;
the resulting structure is cleaned.
10. The method for manufacturing a semiconductor chip package structure according to any one of claims 6 to 9, wherein: the depth of the groove formed in the step 3) is 1/4-1/2 of the thickness of the semiconductor substrate.
CN201911387521.6A 2019-12-30 2019-12-30 Semiconductor chip packaging structure and preparation method thereof Pending CN113130412A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114161591A (en) * 2021-12-03 2022-03-11 江西省纳米技术研究院 Nondestructive cleavage method for semiconductor chip

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114161591A (en) * 2021-12-03 2022-03-11 江西省纳米技术研究院 Nondestructive cleavage method for semiconductor chip

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