CN108461464B

CN108461464B - Semiconductor packaging structure and manufacturing method thereof

Info

Publication number: CN108461464B
Application number: CN201810122289.2A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2018-02-07
Filing date: 2018-02-07
Publication date: 2023-07-25
Anticipated expiration: 2038-02-07
Also published as: CN108461464A

Abstract

The application relates to the field of semiconductor packaging, and discloses a semiconductor packaging structure and a manufacturing method thereof. The semiconductor package structure includes: the first packaging body is provided with a first mounting surface and a first external connection lug which is positioned on the first mounting surface; an anisotropic conductive film including conductive particles, the anisotropic conductive film being bonded to the first mounting surface; the second packaging body comprises a second chip, a second plastic packaging material for sealing the second chip, a first middle layer rewiring structure covered on the second plastic packaging material and a second external bump protruding from the first middle layer rewiring structure. The second external bump is partially embedded in the dielectric layer of the first interlayer rerouting structure; the hardness of the conductive particles is larger than that of the second external protruding blocks, and when the second packaging body is pressed to the first packaging body and bonded by the anisotropic conductive film until the longitudinal gap between the first external protruding blocks and the second external protruding blocks is smaller than the maximum particle size of the conductive particles. By adopting the technical scheme, the throughput can be increased, and the area after encapsulation can be reduced.

Description

Semiconductor packaging structure and manufacturing method thereof

Technical Field

The present disclosure relates to the field of semiconductor packaging, and in particular, to a semiconductor packaging structure and a method for manufacturing the same.

Background

Unlike conventional chip packaging (WLCSP for short, wafer level chip scale package (Wafer Level Chip Scale Packaging), which is a technique of packaging and testing a whole wafer and then dicing individual IC (Integrated Circuit ) particles, the packaged volume is equal to the original size of the IC die. Whereas in conventional fan-out (FO) -WLCSP packages, the chips are typically placed side-by-side laterally, this way of packaging has limitations in throughput.

Disclosure of Invention

The present application provides a semiconductor package structure and a method for manufacturing the same.

In order to achieve the above object, in an aspect of the present application, there is provided a semiconductor package structure including: the first packaging body is provided with a first mounting surface, the first packaging body comprises a first chip, a first plastic packaging material for sealing the first chip and a first external connection lug positioned on the first mounting surface, the first chip is provided with a first active surface and a first back surface opposite to the first active surface, and the first chip comprises a first chip bonding pad positioned on the first active surface; a first anisotropic conductive film including conductive particles, the first anisotropic conductive film being bonded to the first mounting surface; the second packaging body comprises a second chip, a second plastic packaging material for sealing the second chip, a first interlayer re-wiring structure covered on the second plastic packaging material and a second external bump protruding out of the first interlayer re-wiring structure, the second chip is provided with a second active surface and a second back surface opposite to the second active surface, the second chip comprises a second chip bonding pad positioned on the second active surface, a first interlayer passivation layer positioned on the second active surface and a first interlayer interconnection bump positioned in the first interlayer passivation layer and bonded with the second chip bonding pad, and the forming surface of the second plastic packaging material, the outer surface of the first interlayer passivation layer and the top surface of the first interlayer interconnection bump are formed on the continuous surface of the first interlayer; the first interlayer re-wiring structure is formed on the continuous surface of the first interlayer, and the second external bump is partially embedded in the dielectric layer of the first interlayer re-wiring structure and is electrically connected to the top surface of the first interlayer interconnection bump through the first circuit of the first interlayer re-wiring structure; when the second packaging body is pressed to the first packaging body and is adhered by the first anisotropic conductive film until the longitudinal gap between the first external protruding block and the second external protruding block is smaller than the maximum particle size of the conductive particles, the conductive particles are locally embedded in the second external protruding block, so that the second external protruding block is longitudinally and electrically connected with the first external protruding block through the conductive particles.

Optionally, the hardness of the conductive particles is also greater than that of the first external connection bumps.

Optionally, the first intermediate layer interconnect bump is relatively offset from the junction of the first and second external bumps.

Alternatively, the shape of the conductive particles includes any one of a sphere, a cone, a cube, and a polyhedron.

Optionally, the conductive particles have a particle size of less than 5 microns and are made of metal.

Optionally, the second package further includes a second intermediate layer rerouting structure and a third external bump protruding from the second intermediate layer rerouting structure; the second chip further comprises a second intermediate layer passivation layer positioned on the second back surface, and a second intermediate layer interconnection bump which is positioned in the second intermediate layer passivation layer and is electrically connected with the second chip bonding pad through a through silicon via, wherein the packaging surface of the second plastic packaging material, the outer surface of the second intermediate layer passivation layer and the top surface of the second intermediate layer interconnection bump are formed on the continuous surface of the second intermediate layer; the second interlayer re-wiring structure is formed on the continuous surface of the second interlayer, and the third external connection bump is partially embedded in the dielectric layer of the second interlayer re-wiring structure and is electrically connected to the top surface of the second interlayer interconnection bump via the second line of the second interlayer re-wiring structure.

Optionally, the first package further includes: a first bottom layer rerouting structure and a second bottom layer rerouting structure; the first chip further comprises a first bottom passivation layer positioned on the first active surface, a first bottom interconnection bump positioned in the first bottom passivation layer and bonded with the first chip bonding pad, a second bottom passivation layer positioned on the first back surface, and a second bottom interconnection bump positioned in the second bottom passivation layer and electrically connected with the first chip bonding pad through a through silicon via; the forming surface of the first plastic package material, the outer surface of the first bottom passivation layer and the top surface of the first bottom interconnection bump are formed on the continuous surface of the first bottom layer; a first underlying re-wiring structure formed on the first underlying continuous surface, the first underlying re-wiring structure having a dielectric layer, terminal pads formed on an outer surface of the dielectric layer, and third lines within the dielectric layer and electrically connecting the terminal pads and the first underlying interconnect bumps; the first package further comprises solder balls implanted to the terminal pads; the packaging surface of the first plastic packaging material, the outer surface of the second bottom passivation layer and the top surface of the second bottom interconnection bump are formed on the continuous surface of the second bottom; the second under-layer re-wiring structure is formed on the second under-layer continuous surface, and the first external connection bump is partially embedded in the dielectric layer of the second under-layer re-wiring structure and is electrically connected to the top surface of the second under-layer interconnection bump through the fourth line of the second under-layer re-wiring structure.

Optionally, the semiconductor package structure further includes a third package body, the third package body includes a third chip, a third molding compound sealing the third chip, the third chip has a third active surface and a third back surface opposite to the third active surface, the third chip includes a third chip pad located on the third active surface, a first top passivation layer located on the third active surface, and a first top interconnection bump located in the first top passivation layer and bonded to the third chip pad; the forming surface of the third plastic package material, the outer surface of the first top passivation layer and the top surface of the first top interconnection bump are formed on the continuous surface of the first top layer; the third package further includes a first top-level rewiring structure formed on the first top-level continuous surface; a fourth external bump protruding from the first top-layer re-wiring structure, the fourth external bump being partially embedded in the dielectric layer of the first top-layer re-wiring structure and electrically connected to the top surface of the first top-layer interconnection bump via a fifth line of the first top-layer re-wiring structure; and a second anisotropic conductive film including conductive particles, the second anisotropic conductive film being attached to an outer surface of the second intermediate layer rewiring structure; when the third packaging body is pressed to the second packaging body and is adhered by the second anisotropic conductive film until the longitudinal gap between the third external connection lug and the fourth external connection lug is smaller than the maximum particle size of the conductive particles of the second anisotropic conductive film, the conductive particles are partially embedded in the fourth external connection lug, so that the fourth external connection lug is longitudinally and electrically connected with the third external connection lug through the conductive particles.

Optionally, the second package includes a plurality of longitudinally stacked packages, and two adjacent packages are bonded through anisotropic conductive films.

In another aspect of the present application, there is provided a method for manufacturing a semiconductor package structure, the method comprising: the first packaging body comprises a first chip, a first plastic packaging material and a first external connection lug, wherein the first plastic packaging material is used for sealing the first chip; attaching an anisotropic conductive film to the first mounting surface, the anisotropic conductive film comprising conductive particles; providing a second packaging body, wherein the second packaging body comprises a second chip, a second plastic packaging material for sealing the second chip, a first interlayer re-wiring structure covered on the second plastic packaging material and a second external bump protruding out of the first interlayer re-wiring structure, the second chip is provided with a second active surface and a second back surface opposite to the second active surface, the second chip comprises a second chip bonding pad positioned on the second active surface, a first interlayer passivation layer positioned on the second active surface and a first interlayer interconnection bump positioned in the first interlayer passivation layer and bonded with the second chip bonding pad, and the forming surface of the second plastic packaging material, the outer surface of the first interlayer passivation layer and the top surface of the first interlayer interconnection bump are formed on the continuous surface of the first interlayer; the first interlayer re-wiring structure is formed on the continuous surface of the first interlayer, and the second external bump is partially embedded in the dielectric layer of the first interlayer re-wiring structure and is electrically connected to the top surface of the first interlayer interconnection bump through the first circuit of the first interlayer re-wiring structure; and pressing the second packaging body to the first packaging body, wherein the hardness of the conductive particles is greater than that of the second external protruding blocks, and when the second packaging body is pressed to the first packaging body and is bonded by the anisotropic conductive film until the longitudinal gap between the first external protruding blocks and the second external protruding blocks is smaller than the maximum particle size of the conductive particles, the conductive particles are locally embedded in the second external protruding blocks, so that the second external protruding blocks are longitudinally and electrically connected with the first external protruding blocks through the conductive particles.

Optionally, the second package further includes a second intermediate layer rerouting structure and a third external bump protruding from the second intermediate layer rerouting structure, and the method further includes: attaching a second anisotropic conductive film to the outer surface of the second interlayer rerouting structure, the second anisotropic conductive film comprising conductive particles; providing a third packaging body, wherein the third packaging body comprises a third chip, a third plastic packaging material for sealing the third chip and a fourth external connection lug, the third chip is provided with a third active surface, and the third chip comprises a third chip bonding pad positioned on the third active surface; and pressing the third packaging body to the second packaging body, wherein the hardness of the conductive particles of the second anisotropic conductive film is greater than that of the fourth external connection convex block, and when the third packaging body is pressed to the second packaging body and is bonded by the second anisotropic conductive film until the longitudinal gap between the third external connection convex block and the fourth external connection convex block is smaller than the maximum particle diameter of the conductive particles of the second anisotropic conductive film, the conductive particles are partially embedded in the fourth external connection convex block, so that the fourth external connection convex block is longitudinally and electrically connected with the third external connection convex block through the conductive particles.

Optionally, the method further includes laminating a plurality of second packages between the first package and the third package, and bonding the plurality of second packages through the anisotropic conductive film.

In the technical scheme, the vertical stack is completed through wafer bonding, so that compared with a mode of placing chips side by side, the throughput can be increased, and the area after packaging is reduced. In addition, by using Anisotropic Conductive Film (ACF) bonding, the thickness between the individual package layers can be reduced as compared to soldering.

Additional features and advantages of the present application will be set forth in the detailed description which follows.

Drawings

The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate the application and together with the description serve to explain, but not limit the application. In the drawings:

fig. 1 is a cross-sectional view of a semiconductor package structure according to an embodiment of the present application;

fig. 2 is a cross-sectional view of a semiconductor package structure according to another embodiment of the present application;

fig. 3 is a cross-sectional view of a semiconductor package structure according to another further embodiment of the present application;

Fig. 4A to 4D are schematic views of the shape of the conductive particles in the embodiment according to the present application;

fig. 5A to 5H are schematic views showing a structure obtained after each step is performed by a method for manufacturing a semiconductor package structure according to an embodiment of the present application; and

fig. 6A to 6I show schematic diagrams of structures obtained after each step is performed by a method for manufacturing a package body having a dual re-wiring layer (RDL) according to an embodiment of the present application.

Description of the reference numerals

100. Bottom package of 200, 300 semiconductor package structure 110

111. First external connection lug of first mounting surface 112

113. Active surface of bottom chip 114a

114b backside 115 bottom chip pad

116a first underlying passivation layer 116b second underlying passivation layer

117a first under-layer interconnect bump 117b second under-layer interconnect bump

118. Through silicon via 120 ACF

121. Top package of conductive particles 130

131. Top chip 132a active surface

132b backside 133 top chip pad

134. First top passivation layer 135 first top interconnect bump

140. Second continuous surface of top layer molding compound 141

150. First continuous surface of bottom plastic package 151a

151b second continuous surface 152a first underlying rerouting structure

152b second bottom layer rewiring structure 153 dielectric layer outer surface

154a dielectric layer 154b dielectric layer

155a line 155b line

156. Solder ball for terminal pad 157

160. Second mounting surface of first top layer re-routing structure 161

163. Dielectric layer 164 circuit

165. Second external bump

210. First mounting surface of first package 211

212. First chip of first external bump 213

214a active face 214b back face

215. First die pad 216a first underlying passivation layer

216b second underlying passivation layer 217a first underlying interconnect bumps

217b second bottom interconnect bump 218 through silicon via

220 ACF 221 conductive particles

230. Second package 231 second chip

232a active surface 232b back side

233. Second die pad 234a first top passivation layer

234b second top passivation layer 235a first top interconnect bump

235b second top-level interconnect bump 236 through silicon via

240. Third continuous surface of second molding compound 241a

241b fourth continuous surface 242a first top layer rewiring structure

242b second top layer rerouting structure 243 second mounting surface

244a dielectric 244b dielectric

245a line 245b line

246a second outer bump 246b third outer bump

247. Third mounting surface 250 first molding compound

251a first continuous surface 251b second continuous surface

252a first bottom layer re-routing structure 252b second bottom layer re-routing structure

253. Dielectric layer of dielectric layer outer surface 254a

254b dielectric layer 255a line

255b line 256 terminal pad

257. Solder ball

310. First mounting surface of first package 311

312. First external bump 313 first chip

314a first active surface 314b first back surface

315. First die pad 316a first underlying passivation layer

316b second underlying passivation layer 317a first underlying interconnect bump

317b second bottom interconnect bump 318 through silicon via

320 ACF 321 conductive particles

330. Second chip of second Package 331

332. Second active surface 333 second back surface

334. Second chip pad 335a first intermediate passivation layer

335b second interlayer passivation layer 336a first interlayer interconnect bump

336b second inter-layer interconnect bump 337 through silicon via

340. Continuous surface of first intermediate layer of second molding compound 341a

341b second intermediate layer continuous surface 342a first intermediate layer re-routing structure

342b second interlayer rewiring structure

344a dielectric 344b dielectric

345a line 345b line

346a second external bump 346b third external bump

350. First continuous surface of first bottom layer of first molding compound 351a

351b second bottom continuous surface 352a first bottom rerouting structure

352b second bottom layer rerouting structure 353 dielectric layer

354a dielectric layer 354b dielectric layer

355a line 355b line

356. Solder ball for terminal pad 357

360. Third chip of third package 361

362a third active surface 362b third back surface

363. Third chip pad 364 first top passivation layer

365. Third molding compound for first top-layer interconnection bump 370

371. First top-layer rerouting structure for first top-layer continuous surface 372

374. Dielectric layer 375 line

376. Fourth external connection bump 380 ACF

381. Conductive particles

510. Thermal degumming of carrier 520

611. First support 612 first thermal degumming

613. Second carrier 614 second thermal degumming

615. Third thermal degumming of third support 616

617. Fourth carrier 618 fourth thermal degumming

620. Active surface of chip 621a

621b backside 622 chip pad

623. First passivation layer of through silicon via 624

625. First metal bump 626 second passivation layer

627. Second metal bump 628 plastic package material

629. First continuous surface 630 first re-routing structure

631. First dielectric layer 632 first circuit

633. Second continuous surface 634 second redistribution structure

635. Second dielectric layer 636 second line

637. External connection lug

Detailed Description

The following detailed description of specific embodiments of the present application refers to the accompanying drawings. It should be understood that the detailed description is presented herein for purposes of illustration and explanation only and is not intended to limit the present application.

In the present application, unless otherwise stated, terms such as "upper/above, lower/below, left/left, right/right" are used to refer generally to the upper, lower, left, right as shown with reference to the drawings. "inner and outer" generally refer to the inner and outer relative to the contour of the components themselves.

In this application, if the terms "front side of the chip", "active side of the chip", "first surface of the chip" are used, it may refer to a surface having integrated circuits; in this application, if the terms "back side of the chip", "second surface of the chip" are used, they may refer to the surface opposite to "front side of the chip", "active side of the chip", "first surface of the chip".

In the drawings, the shapes of the illustrations as a result, however, of variations in terms of manufacturing processes and/or tolerances. Accordingly, exemplary embodiments of the present application are not limited to the specific shapes shown in the drawings, and may include shape changes caused during manufacturing. Furthermore, the various elements and regions in the figures are only schematically illustrated and thus the present application is not limited to the relative dimensions or distances illustrated in the figures.

Fig. 1 is a cross-sectional view of a semiconductor package 100 according to an embodiment of the present application. Referring to fig. 1, a semiconductor package structure 100 according to an embodiment of the present application may include an underlying package 110, and the underlying package 110 may include an underlying chip 113. The bottom chip 113 may have an active face 114a and a back face 114b opposite the active face 114 a. The bottom chip 113 may include a bottom chip pad 115 located at the active face 114 a. A first underlying passivation layer 116a may be formed on the active face 114a, with the first underlying interconnect bump 117a being located within the first underlying passivation layer 116a and bonded to the underlying die pad 115.

A second underlying passivation layer 116b may be formed on the back surface 114b, and second underlying interconnect bumps 117b are located within the second underlying passivation layer 116b and may be electrically connected to the underlying chip pads 115 through silicon vias 118.

The kind of the first underlying passivation layer 116a or the second underlying passivation layer 116b may include, but is not limited to, inorganic glass and organic polymer. The material of the inorganic glass may include, but is not limited to, oxides (e.g., siO2, al2O3, tiO2, zrO2, fe2O3, sixOy), silicates (e.g., PSG, BSG, BPSG), nitrides (e.g., si3N4, sixNyH, BN, alN, gaN). The material of the organic polymer may include, but is not limited to, synthetic resins (e.g., polyimide-based resins, polysiloxane-based resins), synthetic rubbers (e.g., silicone rubbers). The material of the first or second under-interconnection bump 117a or 117b may include, but is not limited to, gold, silver, copper, platinum, aluminum, and preferably the material of the first or second under-interconnection bump 117a or 117b may include copper.

The bottom layer package 110 may also include a bottom layer molding compound 150 encapsulating the bottom layer chip 113. The primer molding compound 150 may comprise, for example, an epoxy molding compound (Epoxy Molding Compound, EMC), although those skilled in the art will appreciate that other materials are suitable. The formation surface of the underfill encapsulant 150, the outer surface of the first underfill passivation layer 116a, and the top surface of the first under-bump interconnect 117a are formed on the first continuous surface 151a.

The bottom level package 110 may further include a first bottom level rewiring structure 152a formed on the first continuous surface 151a. The first under-layer re-routing structure 152a may include a dielectric layer 154a, terminal pads 156 located on the dielectric layer outer surface 153 of the dielectric layer 154a, and lines 155a located within the dielectric layer 154a and electrically connecting the terminal pads 156 with the first under-layer interconnect bumps 117 a. The material of the dielectric layer 154a may include a polymer film material such as benzocyclobutene (BCB), polyimide (PI), etc., but is not limited thereto. The material of dielectric layer 154a may also include other insulating materials. For example, a wiring 155a and a terminal pad 156 electrically connected to the wiring 155a may be formed in the dielectric layer 154a using a re-wiring (RDL) technique. RDL technology is a technology known to those skilled in the art and is not described in detail herein. In one embodiment of the present application, the material of the wire 155a may include one of copper and aluminum. However, those skilled in the art will appreciate that the material of the wire 155a may comprise other metals (e.g., gold, silver, platinum) or other types of conductive materials other than metals. In one embodiment of the present application, the wire 155a and the terminal pad 156 may use the same material. In another embodiment of the present application, different materials may be used for the wire 155a and the terminal pad 156. In one embodiment of the present application, line 155a may be a fan-out line.

The bottom layer package 110 may also include solder balls 157 implanted to the terminal pads 156. For example, solder balls 157 may be implanted to terminal pads 156 using a ball-implant process.

The encapsulation surface of the underfill encapsulant 150, the outer surface of the second underfill passivation layer 116b, and the top surface of the second under-interconnect bumps 117b are formed on the second continuous surface 151b.

The bottom level package 110 may further include a second bottom level rewiring structure 152b formed on the second continuous surface 151b. The second under-layer re-routing structure 152b may include a dielectric layer 154b, and a wire 155b located within the dielectric layer 154b and electrically connected to the second under-layer interconnect bump 117 b. The material of the dielectric layer 154b may include a polymer film material, such as benzocyclobutene (BCB), polyimide (PI), etc., but is not limited thereto. The material of dielectric layer 154b may also include other insulating materials. For example, a re-Routing (RDL) technique may be employed to form the line 155b in the dielectric layer 154 b. In one embodiment of the present application, the material of the wire 155b may include one of copper and aluminum. However, those skilled in the art will appreciate that the material of the wire 155b may comprise other metals (e.g., gold, silver, platinum) or other types of conductive materials other than metals.

The bottom package 110 may further include a first external bump 112 exposed from the dielectric layer 154b, and the first external bump 112 is electrically connected to the line 155 b. In one embodiment of the present application, the first external bump 112 may protrude from the dielectric layer 154b. The outer surface of the second under-layer re-routing structure 152b and the top surface of the first external connection bump 112 may form the first mounting surface 111. The material of the first external bump 112 may include, but is not limited to, gold, silver, copper, platinum, and aluminum, and preferably, the material of the first external bump 112 may include copper.

The semiconductor package structure 100 may further include An anisotropic conductive film (An-isotropic Conductive Film, ACF), which may contain the conductive particles 121. The ACF120 is attached to the first mounting surface 111. Features of the ACF120 will be described in detail later.

The semiconductor package structure 100 may further include a top-level package 130, and the top-level package 130 may include a top-level chip 131. The top chip 131 may have an active face 132a and a back face 132b opposite the active face 132 a. The top chip 131 may include a top chip pad 133 located at the active surface 132 a. A first top passivation layer 134 may be formed on the active surface 132a, with first top interconnect bumps 135 located within the first top passivation layer 134 and bonded to the top chip pads 133.

The types of the first top passivation layer 134 may include, but are not limited to, inorganic glass and organic polymers. The material of the inorganic glass may include, but is not limited to, oxides (e.g., siO2, al2O3, tiO2, zrO2, fe2O3, sixOy), silicates (e.g., PSG, BSG, BPSG), nitrides (e.g., si3N4, sixNyH, BN, alN, gaN). The material of the organic polymer may include, but is not limited to, synthetic resins (e.g., polyimide-based resins, polysiloxane-based resins), synthetic rubbers (e.g., silicone rubbers). The material of the first top-layer interconnect bump 135 may include, but is not limited to, gold, silver, copper, platinum, aluminum, preferably, the material of the first top-layer interconnect bump 135 may include copper.

The top-level package 130 may also include a top-level molding compound 140 that encapsulates the top-level chip 131. The top layer molding compound 140 may comprise, for example, an epoxy molding compound (Epoxy Molding Compound, EMC), but those skilled in the art will appreciate that other materials are suitable. The formation surface of the top-layer molding compound 140, the outer surface of the first top-layer passivation layer 134, and the top surface of the first top-layer interconnect bump 135 are formed on the second continuous surface 141.

The top level package 130 may also include a first top level rewiring structure 160 formed on the second continuous surface 141. The first top-level re-routing structure 160 may include a dielectric layer 163, and a line 164 located within the dielectric layer 163, the line 164 being electrically connected to the first top-level interconnect bump 135.

The material of the dielectric layer 163 may include a polymer thin film material such as benzocyclobutene (BCB), polyimide (PI), etc., but is not limited thereto. The material of dielectric layer 163 may also include other insulating materials. For example, a re-Routing (RDL) technique may be employed to form the lines 164 in the dielectric layer 163. In one embodiment of the present application, the material of the line 164 may include one of copper and aluminum. However, those skilled in the art will appreciate that the material of the traces 164 may comprise other metals (e.g., gold, silver, platinum) or other types of conductive materials other than metals.

The top package 130 may further include a second external bump 165 exposed outward from the dielectric layer 163, the second external bump 165 being electrically connected to the wiring 164. In one embodiment of the present application, the second external bump 165 may protrude from the dielectric layer 163. The outer surface of the first top-level re-routing structure 160 and the top surface of the second external bump 165 may form a second mounting surface 161. The material of the second external bump 165 may include, but is not limited to, gold, silver, copper, platinum, and aluminum, and preferably, the material of the second external bump 165 may include copper.

The first external connection bump 112 or the second external connection bump 165 may be formed in various ways. In one example, the first or second external bumps 112 or 165 may be grown on the outer surface of the second bottom-layer rerouting structure 152b or the first top-layer rerouting structure 160, and then the grown first or second external bumps 112 or 165 may be plastic encapsulated. In another example, a cavity may be lithographically etched on the second bottom layer rerouting structure 152b or the first top layer rerouting structure 160 and electroplated (e.g., copper electroplated) in the cavity to form the first external bump 112 or the second external bump 165. Those skilled in the art will appreciate that other well-known possible ways for forming the first external bump 112 or the second external bump 165 are within the scope of the present application.

In an embodiment of the present application, the conductive particles 121 may have a hardness greater than that of the second external bump 165. When the top package 130 is pressed onto the bottom package 110, the bottom package 110 is bonded to the ACF120 until the longitudinal gap between the first external bump 112 and the second external bump 165 is smaller than the maximum particle size of the conductive particles 121. The conductive particles 121 may be partially embedded in the second external bump 165 such that the second external bump 165 is electrically connected to the first external bump 112 in the longitudinal direction through the conductive particles 121.

In the embodiment of the present application, the hardness of the conductive particles 121 may also be greater than that of the first external connection bump 112, so that when the top package 130 is pressed onto the bottom package 110, the conductive particles 121 may also be partially embedded in the first external connection bump 112, thereby increasing the conductive area and reducing the impedance.

The types of the bottom chip 113 or the top chip 131 may include a memory chip and a logic chip. Examples of memory chips may include, but are not limited to, random Access Memory (RAM). Examples of RAM may include Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM). Examples of logic chips may include, but are not limited to, graphics processing unit (Graphic Processing Unit, GPU) chips, central processing unit (Central Processing Unit, CPU) chips, system On Chip (SOC).

Fig. 2 is a cross-sectional view of a semiconductor package structure 200 according to another embodiment of the present application. Referring to fig. 2, a semiconductor package structure 200 according to an embodiment of the present application may include a first package body 210, and the first package body 210 may include a first chip 213. The first chip 213 may have an active face 214a and a back face 214b opposite the active face 214 a. The first chip 213 may include a first chip pad 215 located at the active face 214 a. A first underlying passivation layer 216a may be formed on the active face 214a, and a first underlying interconnect bump 217a is located within the first underlying passivation layer 216a and bonded to the first die pad 215.

A second underlying passivation layer 216b may be formed on the back surface 214b, and a second underlying interconnect bump 217b may be located within the second underlying passivation layer 216b and may be electrically connected to the first die pad 215 through a through silicon via 218.

The kind of the first underlying passivation layer 216a or the second underlying passivation layer 216b may include, but is not limited to, inorganic glass and organic polymer. The material of the inorganic glass may include, but is not limited to, oxides (e.g., siO2, al2O3, tiO2, zrO2, fe2O3, sixOy), silicates (e.g., PSG, BSG, BPSG), nitrides (e.g., si3N4, sixNyH, BN, alN, gaN). The material of the organic polymer may include, but is not limited to, synthetic resins (e.g., polyimide-based resins, polysiloxane-based resins), synthetic rubbers (e.g., silicone rubbers). The material of the first or second under-interconnection bumps 217a or 217b may include, but is not limited to, gold, silver, copper, platinum, aluminum, and preferably, the material of the first or second under-interconnection bumps 217a or 217b may include copper.

The first package 210 may further include a first molding compound 250 sealing the first chip 213. The first molding compound 250 may comprise, for example, an epoxy molding compound (Epoxy Molding Compound, EMC), although those skilled in the art will appreciate that other materials are suitable. The forming surface of the first molding compound 250, the outer surface of the first under passivation layer 216a, and the top surface of the first under interconnection bump 217a are formed on the first continuous surface 251a.

The first package 210 may further include a first bottom rerouting structure 252a formed on the first continuous surface 251a. The first under-layer re-routing structure 252a may include a dielectric layer 254a, terminal pads 256 located on an outer surface 253 of the dielectric layer 254a, and lines 255a located within the dielectric layer 254a and electrically connecting the terminal pads 256 with the first under-layer interconnect bumps 217 a. The material of the dielectric layer 254a may include a polymer film material, such as benzocyclobutene (BCB), polyimide (PI), etc., but is not limited thereto. The material of the dielectric layer 254a may also include other insulating materials. For example, a wiring 255a and a terminal pad 256 electrically connected to the wiring 255a may be formed in the dielectric layer 254a using a re-wiring (RDL) technique. RDL technology is a technology known to those skilled in the art and is not described in detail herein. In one embodiment of the present application, the material of the wire 255a may include one of copper and aluminum. However, those skilled in the art will appreciate that the material of the wire 255a may comprise other metals (e.g., gold, silver, platinum) or other types of conductive materials other than metals. In one embodiment of the present application, the wire 255a and the terminal pad 256 may use the same material. In another embodiment of the present application, different materials may be used for the wire 255a and the terminal pad 256. In one embodiment of the present application, the line 255a may be a fan-out line.

The first package 210 may further include solder balls 257 implanted to the terminal pads 256. For example, solder balls 257 may be implanted to terminal pads 256 using a ball-implant process.

The encapsulation surface of the first molding compound 250, the outer surface of the second underlying passivation layer 216b, and the top surface of the second underlying interconnect bump 217b are formed on the second continuous surface 251b.

The first package 210 may further include a second bottom layer rerouting structure 252b formed on the second continuous surface 251b. The second under-layer re-routing structure 252b may include a dielectric layer 254b, and a wire 255b within the dielectric layer 254b and electrically connected to the second under-layer interconnect bump 217 b. The material of the dielectric layer 254b may include a polymer film material, such as benzocyclobutene (BCB), polyimide (PI), etc., but is not limited thereto. The material of dielectric layer 254b may also include other insulating materials. For example, a re-Routing (RDL) technique may be employed to form the lines 255b in the dielectric layer 254 b. In one embodiment of the present application, the material of the wire 255b may include one of copper and aluminum. However, those skilled in the art will appreciate that the material of the wire 255b may comprise other metals (e.g., gold, silver, platinum) or other types of conductive materials other than metals.

The first package 210 may further include a first external bump 212 exposed from the dielectric layer 254b, and the first external bump 212 is electrically connected to the wire 255 b. In one embodiment of the present application, the first external bump 212 may protrude from the dielectric layer 254b. The outer surface of the second under-layer re-routing structure 252b and the top surface of the first external connection bump 212 may form a first mounting surface 211. The material of the first external bump 212 may include, but is not limited to, gold, silver, copper, platinum, and aluminum, and preferably, the material of the first external bump 212 may include copper.

The semiconductor package structure 200 may further include An anisotropic conductive film (An-isotropic Conductive Film, ACF), which may contain the conductive particles 221. The ACF220 is attached to the first mounting surface 211. Features of the ACF220 will be described in detail later.

The semiconductor package structure 200 may further include a second package 230, and the second package 230 may include a second chip 231. The second chip 231 may have an active surface 232a and a back surface 232b opposite to the active surface 232 a. The second chip 231 may include a second chip pad 233 located at the active surface 232 a. A first top passivation layer 234a may be formed on the active surface 232a, and a first top interconnect bump 235a is located within the first top passivation layer 234a and bonded to the second chip pad 233.

A second top passivation layer 234b may be formed on the back surface 232b, and a second top interconnect bump 235b may be located within the second top passivation layer 234b and may be electrically connected to the second chip pad 233 through a through silicon via 236.

The types of the first top passivation layer 234a or the second top passivation layer 234b may include, but are not limited to, inorganic glass and organic polymer. The material of the inorganic glass may include, but is not limited to, oxides (e.g., siO2, al2O3, tiO2, zrO2, fe2O3, sixOy), silicates (e.g., PSG, BSG, BPSG), nitrides (e.g., si3N4, sixNyH, BN, alN, gaN). The material of the organic polymer may include, but is not limited to, synthetic resins (e.g., polyimide-based resins, polysiloxane-based resins), synthetic rubbers (e.g., silicone rubbers). The material of the first top-layer interconnect bump 235a or the second top-layer interconnect bump 235b may include, but is not limited to, gold, silver, copper, platinum, aluminum, and preferably the material of the first top-layer interconnect bump 235a or the second top-layer interconnect bump 235b may include copper.

The second package body 230 may further include a second molding compound 240 sealing the second chip 231. The second molding compound 240 may comprise, for example, an epoxy molding compound (Epoxy Molding Compound, EMC), although those skilled in the art will appreciate that other materials are suitable. The forming surface of the second molding compound 240, the outer surface of the first top passivation layer 234a, and the top surface of the first top interconnect bump 235a are formed on the third continuous surface 241a.

The second package 230 may further include a first top-level re-routing structure 242a formed on the third continuous surface 241 a. The first top-level re-routing structure 242a may include a dielectric layer 244a, and a line 245a within the dielectric layer 244a, the line 245a being electrically connected to the first top-level interconnect bump 235 a.

The material of the dielectric layer 244a may include a polymer thin film material, such as benzocyclobutene (BCB), polyimide (PI), etc., but is not limited thereto. The material of dielectric layer 244a may also include other insulating materials. For example, a re-Routing (RDL) technique may be employed to form line 245a in dielectric layer 244a. In one embodiment of the present application, the material of the line 245a may include one of copper and aluminum. However, those skilled in the art will appreciate that the material of the traces 245a may comprise other metals (e.g., gold, silver, platinum) or other types of conductive materials other than metals.

The second package body 230 may further include a second external bump 246a exposed outward from the dielectric layer 244a, the second external bump 246a being electrically connected to the line 245a. In one embodiment of the present application, the second external bump 246a may protrude from the dielectric layer 244a. The outer surface of the first top-level re-routing structure 242a and the top surface of the second external bump 246a may form a second mounting surface 243. The material of the second external bump 246a may include, but is not limited to, gold, silver, copper, platinum, and aluminum, and preferably, the material of the second external bump 246a may include copper.

The first external connection bump 212 or the second external connection bump 246a may be formed in various ways. In one example, the first or second external bumps 212 or 246a may be grown on the outer surface of the second bottom layer rerouting structure 252b or the first top layer rerouting structure 242a, and then the grown first or second external bumps 212 or 246a may be plastic encapsulated. In another example, a cavity may be lithographically etched on the second bottom layer rerouting structure 252b or the first top layer rerouting structure 242a, and electroplated (e.g., copper electroplated) in the cavity to form the first external bump 212 or the second external bump 246a. Those skilled in the art will appreciate that other well-known possible ways for forming the first circumscribing bump 212 or the second circumscribing bump 246a are within the scope of the present application.

In an embodiment of the present application, the conductive particles 221 may have a hardness greater than that of the second external bump 246a. When the second package 230 is pressed to the first package 210, the first package 210 is adhered to the ACF220 until the longitudinal gap between the first and second external bumps 212 and 246a is smaller than the maximum particle size of the conductive particles 221. The conductive particles 221 may be partially embedded in the second external bump 246a such that the second external bump 246a is electrically connected to the first external bump 212 in the longitudinal direction through the conductive particles 221.

In the embodiment of the present application, the hardness of the conductive particles 221 may be greater than that of the first external connection bump 212, so that when the second package body 230 is pressed onto the first package body 210, the conductive particles 221 may be partially embedded in the first external connection bump 212, thereby increasing the conductive area and reducing the impedance.

The package surface of the second molding compound 240, the outer surface of the second top passivation layer 234b, and the top surface of the second top interconnect bump 235b are formed on the fourth continuous surface 241b.

The second package body 230 may further include a second top-level re-routing structure 242b formed on the fourth continuous surface 241b. The second top-level re-routing structure 242b may include a dielectric layer 244b, and a line 245b within the dielectric layer 244b and electrically connected to the second top-level interconnect bump 235 b. The material of the dielectric layer 244b may include a polymer thin film material, such as benzocyclobutene (BCB), polyimide (PI), etc., but is not limited thereto. The material of dielectric layer 244b may also include other insulating materials. For example, a re-Routing (RDL) technique may be employed to form line 245b in dielectric layer 244 b. In one embodiment of the present application, the material of the line 245b may comprise one of copper and aluminum. However, those skilled in the art will appreciate that the material of the traces 245b may comprise other metals (e.g., gold, silver, platinum) or other types of conductive materials other than metals.

The second package body 230 may further include a third external bump 246b exposed from the dielectric layer 244b, and the third external bump 246b is electrically connected to the line 245 b. In one embodiment of the present application, the third external bump 246b may protrude from the dielectric layer 244b. The outer surface of the second top-level re-routing structure 242b and the top surface of the third external connection bump 246b may form a third mounting surface 247. The third mounting face 247 may be used to superimpose other packages thereon. The material of the third external bump 246b may include, but is not limited to, gold, silver, copper, platinum, and aluminum, and preferably, the material of the third external bump 246b may include copper.

The third external connection bump 246b may be formed in various ways. In one example, the grown third circumscribing bump 246b can be then plastic encapsulated by growing the third circumscribing bump 246b on the outer surface of the second top-level re-wiring structure 242 b. In another example, a cavity may be etched into the second top-level re-wiring structure 242b and electroplated (e.g., copper electroplated) in the cavity to form the third external bump 246b. Those skilled in the art will appreciate that other well-known possible ways for forming the third circumscribing bump 246b are within the scope of the present application.

The types of the first chip 213 or the second chip 231 may include a memory chip and a logic chip. Examples of memory chips may include, but are not limited to, random Access Memory (RAM). Examples of RAM may include Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM). Examples of logic chips may include, but are not limited to, graphics processing unit (Graphic Processing Unit, GPU) chips, central processing unit (Central Processing Unit, CPU) chips, system On Chip (SOC).

Fig. 3 is a cross-sectional view of a semiconductor package structure 300 according to another further embodiment of the present application. Referring to fig. 3, a semiconductor package structure 300 according to an embodiment of the present application may include

The first package 310 has a first mounting surface 311. The first package body 310 may include a first chip 313, a first molding compound 350 sealing the first chip 313, and a first external bump 312 located on the first mounting surface 311. The first chip 313 may have a first active surface 314a and a first back surface 314b opposite to the first active surface 314 a. The first chip 313 may further include a first chip pad 315 located at the first active face 314 a.

The first molding compound 350 may comprise, for example, an epoxy molding compound (Epoxy Molding Compound, EMC), although those skilled in the art will appreciate that other materials are suitable.

The first chip 313 may further include a first under passivation layer 316a on the first active surface 314a, a first under interconnect bump 317a within the first under passivation layer 316a and bonded to the first chip pad 315, a second under passivation layer 316b on the first back surface 314b, and a second under interconnect bump 317b within the second under passivation layer 316b and electrically connected to the first chip pad 315 through a through silicon via 318.

The types of the first or second underlying passivation layer 316a or 316b may include, but are not limited to, inorganic glass and organic polymers. The material of the inorganic glass may include, but is not limited to, oxides (e.g., siO2, al2O3, tiO2, zrO2, fe2O3, sixOy), silicates (e.g., PSG, BSG, BPSG), nitrides (e.g., si3N4, sixNyH, BN, alN, gaN). The material of the organic polymer may include, but is not limited to, synthetic resins (e.g., polyimide-based resins, polysiloxane-based resins), synthetic rubbers (e.g., silicone rubbers). The material of the first under-layer interconnect bump 317a or the second under-layer interconnect bump 317b may include, but is not limited to, gold, silver, copper, platinum, aluminum, and preferably the material of the first under-layer interconnect bump 317a or the second under-layer interconnect bump 317b may include copper.

The formation surface of the first molding compound 350, the outer surface of the first underlying passivation layer 316a, and the top surface of the first underlying interconnect bump 317a are formed on the first underlying continuous surface 351a. The first package body 310 may further include a first underlying re-wiring structure 352a formed on the first underlying continuous surface 351a. The first underlying re-wiring structure 352a may have a dielectric layer 354a, terminal pads 356 formed on an outer surface 353 of the dielectric layer 354a, and lines 355a within the dielectric layer 354a and electrically connecting the terminal pads 356 with the first underlying interconnect bumps 317 a. In one embodiment of the present application, line 355a may be a fan-out line.

The encapsulation surface of the first molding compound 350, the outer surface of the second underlying passivation layer 316b, and the top surface of the second underlying interconnect bump 317b are formed on the second underlying continuous surface 351b. The first package body 310 may further include a second underlying re-wiring structure 352b formed on the second underlying continuous surface 351b. The second under-layer re-routing structure 352b may have a dielectric layer 354b and a line 355b within the dielectric layer 354b and electrically connected to the top surface of the second under-layer interconnect bump 317 b.

The material of the dielectric layer 354a or 354b may include a polymer thin film material, such as benzocyclobutene (BCB), polyimide (PI), etc., but is not limited thereto. The material of dielectric layer 354a or 354b may also include other insulating materials. For example, a re-Routing (RDL) technique may be used to form the line 355a or 355b in the dielectric layer 354a or 354 b. In one embodiment of the present application, the material of the line 355a or 355b may include one of copper and aluminum. However, those skilled in the art will appreciate that the material of the lines 355a or 355b may comprise other metals (e.g., gold, silver, platinum) or other types of conductive materials other than metals.

In embodiments of the present application, the first external bump 312 may be partially embedded in the dielectric layer 354b of the second bottom layer rerouting structure 352b and electrically connected to the top surface of the second bottom layer interconnect bump 317b via the line 355b of the second bottom layer rerouting structure 352 b. The material of the first external bump 312 may include, but is not limited to, gold, silver, copper, platinum, and aluminum, and preferably, the material of the first external bump 312 may include copper.

In an embodiment of the present application, the first package body 310 may further include solder balls 357 implanted to the terminal pads 356.

The semiconductor package structure 300 may further include an Anisotropic Conductive Film (ACF) 320 including conductive particles 321, and the ACF 320 is attached to the first mounting surface 311.

The semiconductor package structure 300 may further include a second package 330. The second package 330 may include a second chip 331, a second molding compound 340 sealing the second chip 331, a first interlayer rewiring structure 342a covering the second molding compound 340, and a second external bump 346a protruding from the first interlayer rewiring structure 342 a. The second chip 331 may have a second active surface 332 and a second back surface 333 opposite the second active surface 332. The second chip 331 may include a second chip pad 334 located on the second active surface 332, a first interlayer passivation layer 335a located on the second active surface 332, and a first interlayer interconnection bump 336a located within the first interlayer passivation layer 335a and bonded to the second chip pad 334. The formation surface of the second molding compound 340, the outer surface of the first interlayer passivation layer 335a, and the top surface of the first interlayer interconnection bump 336a are formed on the first interlayer continuous surface 341a. The first interlayer rerouting structure 342a is formed on the first interlayer continuous surface 341a. The second external bump 346a is partially embedded in the dielectric layer 344a of the first interlayer re-wiring structure 342a and is electrically connected to the top surface of the first interlayer interconnect bump 336a via the line 345a of the first interlayer re-wiring structure 342 a.

In the embodiment of the present application, the conductive particles 321 have a hardness greater than that of the second external bump 346a. When the second package 330 is pressed onto the first package 310, the ACF 320 is used to bond the second package until the longitudinal gap between the first external bump 312 and the second external bump 346a is smaller than the maximum particle size of the conductive particles 321, and the conductive particles 321 are partially embedded in the second external bump 346a, so that the second external bump 346a is electrically connected to the first external bump 312 longitudinally through the conductive particles 321.

In the embodiment of the application, the hardness of the conductive particles 321 may be greater than that of the first external connection bump 312, so that when the second package 330 is pressed onto the first package 310, the conductive particles 321 may be partially embedded in the first external connection bump 312, thereby increasing the conductive area and reducing the impedance.

The second package 330 may further include a second interposer re-routing structure 342b and a third external bump 346b protruding from the second interposer re-routing structure 342 b. The second chip 331 may further include a second intermediate layer passivation layer 335b on the second back surface 333, and a second intermediate layer interconnect bump 336b within the second intermediate layer passivation layer 335b and electrically connected to the second chip pad 334 through a through silicon via 337. The encapsulation surface of the second molding compound 340, the outer surface of the second interlayer passivation layer 335b, and the top surface of the second interlayer interconnect bump 336b are formed on the second interlayer continuous surface 341b. The second intermediate layer rerouting structure 342b is formed on the second intermediate layer continuous surface 341b. The third external bump 346b is partially embedded in the dielectric layer 344b of the second intermediate layer re-wiring structure 342b and is electrically connected to the top surface of the second intermediate layer interconnect bump 336b via the line 345b of the second intermediate layer re-wiring structure 342 b.

The second molding compound 340 may comprise, for example, an epoxy molding compound (Epoxy Molding Compound, EMC), but one skilled in the art will appreciate that other materials are suitable.

The kind of the first interlayer passivation layer 335a or the second interlayer passivation layer 335b may include, but is not limited to, inorganic glass and organic polymer. The material of the inorganic glass may include, but is not limited to, oxides (e.g., siO2, al2O3, tiO2, zrO2, fe2O3, sixOy), silicates (e.g., PSG, BSG, BPSG), nitrides (e.g., si3N4, sixNyH, BN, alN, gaN). The material of the organic polymer may include, but is not limited to, synthetic resins (e.g., polyimide-based resins, polysiloxane-based resins), synthetic rubbers (e.g., silicone rubbers). The material of the first or second interlayer interconnect bump 336a or 336b may include, but is not limited to, gold, silver, copper, platinum, aluminum, preferably, the material of the first or second interlayer interconnect bump 336a or 336b may include copper.

The material of the dielectric layer 344a or 344b may include a polymer thin film material, such as benzocyclobutene (BCB), polyimide (PI), etc., but is not limited thereto. The material of the dielectric layer 344a or 344b may also include other insulating materials. For example, a redistribution line (RDL) technique may be employed to form the lines 345a or 345b in the dielectric layers 344a or 344 b. In one embodiment of the present application, the material of the line 345a or 345b may include one of copper and aluminum. However, those skilled in the art will appreciate that the material of the lines 345a or 345b may comprise other metals (e.g., gold, silver, platinum) or other types of conductive materials other than metals.

The material of the second external bump 346a or the third external bump 346b may include, but is not limited to, gold, silver, copper, platinum, and aluminum, and preferably, the material of the second external bump 346a or the third external bump 346b may include copper.

The semiconductor package structure 300 may further include another ACF 380 including conductive particles 381. The ACF 380 is bonded to the outer surface of the second interlayer re-routing structure 342b

The semiconductor package structure 300 may further include a third package 360, and the third package 360 may include a third chip 361, a third molding compound 370 sealing the third chip 361. The third chip 361 may have a third active surface 362a and a third back surface 362b opposite to the third active surface 362 a. The third chip 361 may include a third chip pad 363 located on the third active surface 362a, a first top passivation layer 364 located on the third active surface 362a, and a first top interconnection bump 365 located within the first top passivation layer 364 and bonded to the third chip pad 363. The forming surface of the third molding compound 370, the outer surface of the first top-layer passivation layer 364, and the top surface of the first top-layer interconnect bump 365 are formed on the first top-layer continuous surface 371. The third package 360 may further include a first top layer rerouting structure 372 formed on the first top layer continuous surface 371. The first top-level re-wiring structure 372 may include a dielectric layer 374 and wiring 375 located within the dielectric layer 374 and electrically connected to the top surface of the first top-level interconnect bump 365.

The third package 360 may further include fourth external bumps 376 protruding from the first top-level re-routing structure 372. In embodiments of the present application, the fourth external bump 376 may be partially embedded in the dielectric layer 374 of the first top-level re-wiring structure 372 and electrically connected to the top surface of the first top-level interconnect bump 365 via the line 375 of the first top-level re-wiring structure 372.

In the embodiment of the present application, the conductive particles 381 of the ACF 380 have a hardness greater than that of the fourth external connection bump 376, and when the third package 360 is pressed onto the second package 330, the ACF 380 is used to bond the conductive particles 381 until the longitudinal gap between the third external connection bump 346b and the fourth external connection bump 376 is smaller than the maximum particle diameter of the conductive particles 381 of the ACF 380, and the conductive particles 381 are partially embedded in the fourth external connection bump 376, so that the fourth external connection bump 376 is electrically connected to the third external connection bump 346b longitudinally through the conductive particles 381.

In the embodiment of the present application, the hardness of the conductive particles 381 may be greater than that of the third external connection bump 346b, so that when the third package body 360 is pressed onto the second package body 330, the conductive particles 381 may be partially embedded in the third external connection bump 346b, thereby increasing the conductive area and reducing the impedance.

The third molding compound 370 may comprise, for example, an epoxy molding compound (Epoxy Molding Compound, EMC), but one skilled in the art will appreciate that other materials are suitable.

The types of the first top passivation layer 364 may include, but are not limited to, inorganic glass and organic polymer. The material of the inorganic glass may include, but is not limited to, oxides (e.g., siO2, al2O3, tiO2, zrO2, fe2O3, sixOy), silicates (e.g., PSG, BSG, BPSG), nitrides (e.g., si3N4, sixNyH, BN, alN, gaN). The material of the organic polymer may include, but is not limited to, synthetic resins (e.g., polyimide-based resins, polysiloxane-based resins), synthetic rubbers (e.g., silicone rubbers). The material of the first top layer interconnect bump 365 may include, but is not limited to, gold, silver, copper, platinum, aluminum, preferably the material of the first top layer interconnect bump 365 may include copper.

The material of the dielectric layer 374 may include a polymer thin film material such as benzocyclobutene (BCB), polyimide (PI), etc., but is not limited thereto. The material of dielectric layer 374 may also include other insulating materials. For example, a re-Routing (RDL) technique may be employed to form lines 375 in dielectric layer 374. In one embodiment of the present application, the material of the line 375 may include one of copper and aluminum. However, those skilled in the art will appreciate that the material of the traces 375 may comprise other metals (e.g., gold, silver, platinum) or other types of conductive materials other than metals.

The material of the fourth external bump 376 may include, but is not limited to, gold, silver, copper, platinum, and aluminum, and preferably, the material of the fourth external bump 376 may include copper.

In the embodiment shown in fig. 3, the external connection bumps (e.g., the first external connection bump 312, the second external connection bump 346a, the third external connection bump 346b, the fourth external connection bump 376) may be formed in a variety of ways. Taking the first external bump 312 as an example, in one example, the first external bump 312 may be grown on the outer surface of the second under-layer re-routing structure 352b, and then the grown first external bump 312 may be plastic-encapsulated. In another example, a cavity may be etched on the second underlying re-wiring structure 352b and electroplated (e.g., copper electroplated) in the cavity to form the first external bump 312. Those skilled in the art will appreciate that other well-known possible ways for forming the first circumscribing bump 312 are within the scope of the present application. In embodiments of the present application, other external bumps, such as the second external bump 346a, the third external bump 346b, and the fourth external bump 376 may be formed using a similar method as the first external bump 312.

Any type of the first chip 313, the second chip 331, and the third chip 361 may include a memory chip and a logic chip. Examples of memory chips may include, but are not limited to, random Access Memory (RAM). Examples of RAM may include Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM). Examples of logic chips may include, but are not limited to, graphics processing unit (Graphic Processing Unit, GPU) chips, central processing unit (Central Processing Unit, CPU) chips, system On Chip (SOC).

In embodiments of the present application, the semiconductor package structure 300 may further include a stacked intermediate package structure. That is, a plurality of second packages 330 stacked may be included between the first package 310 and the third package 360, and the second packages 330 may be pressed together by the ACF 380.

In embodiments of the present application, the interconnect bumps may be relatively offset from the junction points of the external bumps. For example, in the presently claimed embodiment, the first intermediate layer interconnect bump 336a may be relatively offset from the junction of the first circumscribing bump 312 and the second circumscribing bump 346 a.

Fig. 4A to 4D show schematic shapes of conductive particles of the ACF according to an embodiment of the present application. Referring to fig. 4A to 4D, the shape of the conductive particles (e.g., 121, 221, 321, 381) may include any one of a sphere, a cone, a cube, and a polyhedron. In embodiments of the present application, the conductive particles may have a particle size of less than 5 microns and be of a metallic material (e.g., copper). In addition, the ACF may have a thickness of less than 30 microns.

Fig. 5A to 5H are schematic views showing a structure obtained after each step is performed by a method for manufacturing a semiconductor package structure according to an embodiment of the present application. The method may comprise the following steps.

Referring to fig. 5A, a first package 310 is provided. The first package 310 may be attached to a carrier 510. The carrier 510 may be, for example, a glass carrier. For example, a thermal adhesive 520 may be attached to the carrier 510, and the first package 310 may be attached to the thermal adhesive 520. The first package body 310 may have a first mounting surface 311, and the first package body 310 may include a first chip 313, a first molding compound 350 sealing the first chip 313, and a first external bump 312 located on the first mounting surface 311. The first chip 313 may have a first active face 314a and a first back face 314b opposite the first active face 314a, and the first chip 313 may include a first chip pad 315 located at the first active face 314 a.

Referring to fig. 5B, an Anisotropic Conductive Film (ACF) 320 is attached to the first mounting surface 311, and the ACF 320 may include conductive particles 321.

Referring to fig. 5C, a second package 330 is provided. The second package 330 may include a second chip 331, a second molding compound 340 sealing the second chip 331, a first interposer rerouting structure 342a covering the second molding compound 340, and a second external bump 346a protruding from the first interposer rerouting structure 342 a. The second chip 331 may have a second active surface 332 and a second back surface 333 opposite the second active surface 332. The second chip 331 may include a second chip pad 334 located on the second active surface 332, a first interlayer passivation layer 335a located on the second active surface 332, and a first interlayer interconnection bump 336a located within the first interlayer passivation layer 335a and bonded to the second chip pad 334. The formation surface of the second molding compound 340, the outer surface of the first interlayer passivation layer 335a, and the top surface of the first interlayer interconnection bump 336a are formed on the first interlayer continuous surface 341a. The first interlayer rerouting structure 342a is formed on the first interlayer continuous surface 341a. The second external bump 346a is partially embedded in the dielectric layer 344a of the first interlayer re-wiring structure 342a and is electrically connected to the top surface of the first interlayer interconnect bump 336a via the line 345a of the first interlayer re-wiring structure 342 a.

Referring to fig. 5D, the second package 330 is press-fit to the first package 310. The temperature at which the second package 330 is pressed to the first package 310 may be less than 200 ℃. The conductive particles 321 have a hardness greater than that of the second external bump 346a. When the second package 330 is pressed onto the first package 310, the ACF 320 is used to bond the second package until the longitudinal gap between the first external bump 312 and the second external bump 346a is smaller than the maximum particle size of the conductive particles 321, and the conductive particles 321 are partially embedded in the second external bump 346a, so that the second external bump 346a is electrically connected to the first external bump 312 longitudinally through the conductive particles 321.

The second package 330 may further include a second interposer re-routing structure 342b and a third external bump 346b protruding from the second interposer re-routing structure 342 b. Referring to fig. 5E, another ACF 380 is attached to the outer surface of the second interlayer re-wiring structure 342b, the ACF 380 including conductive particles 381.

Referring to fig. 5F, a third package 360 is provided. The third package 360 may include a third chip 361, a third molding compound 370 sealing the third chip 361, and a fourth external bump 376. The third chip 361 may have a third active surface 362a, and the third chip 361 may include a third chip pad 363 located at the third active surface 362 a.

Referring to fig. 5G, the third package 360 is press-fit to the second package 330. The temperature at which the third package 360 is pressed to the second package 330 may be less than 200 ℃. The conductive particles 381 of the ACF 380 have a hardness greater than that of the fourth external connection bump 376, and when the third package body 360 is pressed onto the second package body 330, the conductive particles 381 are bonded to the ACF 380 until the longitudinal gap between the third external connection bump 346b and the fourth external connection bump 376 is smaller than the maximum particle diameter of the conductive particles 381 of the ACF 380, and the conductive particles 381 are partially embedded in the fourth external connection bump 376, so that the fourth external connection bump 376 is electrically connected to the third external connection bump 346b longitudinally through the conductive particles 381.

The carrier 510 is separated. The first package 310 may be separated from the carrier 510, for example, by thermal degumming 520.

The first chip 313 may further include a first underlying passivation layer 316a on the first active surface 314a, a first underlying interconnect bump 317a within the first underlying passivation layer 316a and bonded to the first chip pad 315, a second underlying passivation layer 316b on the first back surface 314b, and a second underlying interconnect bump 317b within the second underlying passivation layer 316b and electrically connected to the first chip pad 315 through a through silicon via 318.

The formation surface of the first molding compound 350, the outer surface of the first underlying passivation layer 316a, and the top surface of the first underlying interconnect bump 317a are formed on the first underlying continuous surface 351a. The first package body 310 may further include a first underlying re-routing structure 352a formed on the first underlying continuous surface 351a. The first under-layer re-routing structure 352a may have a dielectric layer 354a, terminal pads 356 formed on an outer surface 353 of the dielectric layer 354a, and lines 355a within the dielectric layer 354a and electrically connecting the terminal pads 356 with the first under-layer interconnect bumps 317 a.

Referring to fig. 5H, solder balls 357 are implanted in the terminal pads 356.

In an embodiment of the present application, the method may further include pressing a plurality of stacked second packages 330 on the first package 310 before pressing the third package 360. That is, there may be a plurality of vertically stacked second packages 330 between the first package 310 and the third package 360, and the second packages 330 may also be bonded by the ACF 380.

The method illustrated in fig. 5A through 5H may be used to fabricate the semiconductor package 300 illustrated in fig. 3. Those skilled in the art will appreciate that the semiconductor package structure 100 or 200 illustrated in fig. 1 or 2 may be fabricated using a method similar to that illustrated in fig. 5A through 5H.

Fig. 6A to 6I show schematic views of structures obtained after each step is performed by a method for manufacturing a package body having a dual-layer RDL according to an embodiment of the present application. The method may comprise the steps of:

forming a first passivation layer on the back surface of the chip, wherein a first metal bump is formed in the first passivation layer and is electrically connected with a chip bonding pad positioned on the active surface of the chip through a through silicon via;

forming a second passivation layer on the active surface of the chip, wherein a second metal bump bonded with the chip bonding pad is formed in the second passivation layer;

sealing the chip, the first passivation layer and the second passivation layer by using a plastic package material;

back flattening the plastic package material to expose the first metal bump, wherein the package surface of the plastic package material, the outer surface of the first passivation layer and the top surface of the first metal bump are formed on the first continuous surface, and the formation surface of the plastic package material, the outer surface of the second passivation layer and the top surface of the second metal bump are formed on the second continuous surface;

forming a first rerouting structure on the first continuous surface, the first rerouting structure including a first dielectric layer and a first line within the first dielectric layer and electrically connected to the first metal bump;

Forming a second redistribution structure on the second continuous surface, the second redistribution structure including a second dielectric layer and a second line within the second dielectric layer and electrically connected to the second metal bump; and

and forming an external bump in the second re-wiring structure, wherein the external bump is electrically connected with the second circuit. Optionally, the external bump protrudes from an outer surface of the second redistribution structure.

Optionally, the circumscribing bump is laterally offset from the second metal bump.

Optionally, another external bump is formed within the first re-wiring structure that is electrically connected to the first line. Optionally, the further external bump protrudes from an outer surface of the first rewiring structure.

Alternatively, the material of the first metal bump or the second metal bump may include, but is not limited to, gold, silver, copper, platinum, and aluminum, and preferably, the material of the first metal bump or the second metal bump may include copper.

Optionally, the material of the external bump may include, but is not limited to, gold, silver, copper, platinum, and aluminum, and preferably, the material of the external bump may include copper.

Specifically, referring to fig. 6A, a first carrier 611 is provided, and an active face 621a of a chip 620 is attached to the first carrier 611. The chip 620 may have an active face 621a and a back face 621b opposite the active face 621a, and the chip 620 may include a chip pad 622 located on the active face 621a and a through silicon via 623 electrically connected to the chip pad 622. Specifically, the first thermal degummed 612 may be attached to the first carrier 611, and the active surface 621a of the chip 620 is attached to the first thermal degummed 612. In this step, an entire wafer including chips may be attached to the first carrier 611.

Referring to fig. 6B, a first passivation layer 624 is formed on the back surface 621B of the chip 620, and a first metal bump 625 electrically connected to the chip pad 622 through a through silicon via 623 is formed in the first passivation layer 624. Specifically, a cavity may be etched on the first passivation layer 624, and then electroplated (e.g., copper electroplated) in the cavity to form the first metal bump 625. Optionally, the first metal bump 625 formed may also be polished after electroplating.

Referring to fig. 6C, the chip 620 is separated from the first carrier 611. The chips 620 may be separated from the first carrier 611, for example, by heating the first thermal degumming 612. The chip 620 is flipped over and attached to the second carrier 613. For example, a second thermal degummed 614 may be attached to the second carrier 613, and then the outer surface of the first passivation layer 624 is attached to the second thermal degummed 614.

Referring to fig. 6D, a second passivation layer 626 is formed on the active face 621a of the chip 620, and second metal bumps 627 bonded to the top surface of the chip pads 622 are formed in the second passivation layer 626. Specifically, a cavity may be etched on the second passivation layer 626 and then electroplated in the cavity to form the second metal bump 627. Optionally, the second metal bump 627 formed may also be polished after electroplating.

The wafer is diced to obtain chips 620, and the chips 620 are separated from the second carrier 613.

Referring to fig. 6E, a third carrier 615 is provided, and an outer surface of a second passivation layer 626 of the chip 620 is attached to the third carrier 615. Specifically, known Good Die (KGD) may be selected from the singulated die 620, a third thermal degummed 616 is attached to the third carrier 615, and then an outer surface of the second passivation layer 626 of the die 620 is attached to the third thermal degummed 616.

The chip 620 is encapsulated using a molding compound 628. For example, the molding compound 628 encapsulates the die 620, the first passivation layer 624, and the second passivation layer 626. The molding compound 628 may comprise, for example, an epoxy molding compound (Epoxy Molding Compound, EMC), although those skilled in the art will appreciate that other materials are suitable.

Referring to fig. 6F, plastic molding compound 628 is back planarized (e.g., back ground) to expose first metal bump 625. The encapsulation surface of the molding compound 628, the outer surface of the first passivation layer 624, and the top surface of the first metal bump 625 are formed on the first continuous surface 629.

Referring to fig. 6G, a first rerouting structure 630 is formed on the first continuous surface 629. For example, the first re-routing structure 630 may be formed using RDL technology. The first re-wiring structure 630 may include a first dielectric layer 631 and a first wiring 632 located within the first dielectric layer 631 and electrically connected to the top surface of the first metal bump 625.

Referring to fig. 6H, a fourth carrier 617 is provided, the third carrier 615 is separated, the chip 620 is flipped over, and the outer surface of the first rerouting structure 630 is attached to the fourth carrier 617. For example, the third carrier 615 may be separated by heating the third thermal degumming 616. As another example, a fourth thermal bond 618 may be attached to the fourth carrier 617, and then the outer surface of the first redistribution structure 630 may be attached to the fourth thermal bond 618.

The forming surface of the molding compound 628, the outer surface of the second passivation layer 626, and the top surface of the second metal bump 627 are formed on the second continuous surface 633. A second redistribution structure 634 is formed on the second continuous surface 633. For example, the second redistribution structure 634 may be formed using RDL technology. The second re-wiring structure 634 may include a second dielectric layer 635 and a second wiring 636 located within the second dielectric layer 635 and electrically connected to a top surface of the second metal bump 627.

An external bump 637 electrically connected to the second wiring 636 is formed in the second rewiring structure 634. The external bump 637 may protrude from an outer surface of the second redistribution structure 634. The external bump 637 may be formed in a variety of ways. In one example, the external bumps 637 may be grown by growing the external bumps 637 on the outer surface of the second redistribution structure 634 and then plastic-packaging the grown external bumps 637. In another example, a cavity may be etched on the second redistribution structure 634 and plated in the cavity to form an external bump 637. Those skilled in the art will appreciate that other well-known and feasible means for forming the circumscribing bump 637 are within the scope of the present application.

Referring to fig. 6I, the fourth carrier 617 is separated to obtain a package with a dual layer RDL.

Optionally, the method may further include: additional external bumps are formed within the first re-wiring structure 630. The forming manner is the same as or similar to that of the external bump 637, and will not be described here again.

The carrier in the above embodiments may include, but is not limited to, a glass carrier.

Although thermal degumming is used in the above embodiments, it will be appreciated by those skilled in the art that other types of glue that can separate the package from the carrier under certain conditions, such as photoresist, may also be used.

The semiconductor package structure according to the embodiments of the present application can be applied in a wafer level chip scale package (Wafer Level Chip Size Package, WLCSP), particularly in Fan-out (Fan-out) WLCSP (FOWLCSP).

According to the semiconductor packaging structure provided by the embodiment of the application, the vertical stack is completed through wafer bonding, so that compared with a mode of placing chips side by side, the throughput can be increased, and the area after packaging is reduced. In addition, by using ACF bonding, the thickness between the individual package layers can be reduced as compared to soldering.

The preferred embodiments of the present application have been described in detail above with reference to the accompanying drawings, but the present application is not limited to the specific details of the embodiments described above, and various simple modifications may be made to the technical solutions of the present application within the scope of the technical concept of the present application, and all the simple modifications belong to the protection scope of the present application.

It should be further noted that the various features described in the above embodiments may be combined in any suitable manner without a spear shield. In order to avoid unnecessary repetition, the various possible combinations are not described further.

Moreover, any combination of the various embodiments of the present application may be made without departing from the spirit of the present application, which should also be considered as disclosed herein.

Claims

1. A semiconductor package structure, comprising:

the first packaging body is provided with a first mounting surface, the first packaging body comprises a first chip, a first plastic packaging material for sealing the first chip and a first external connection lug positioned on the first mounting surface, the first chip is provided with a first active surface and a first back surface opposite to the first active surface, and the first chip comprises a first chip bonding pad positioned on the first active surface;

a first anisotropic conductive film including conductive particles, the first anisotropic conductive film being bonded to the first mounting surface;

the second packaging body comprises a second chip, a second plastic packaging material for sealing the second chip, a first interlayer rerouting structure covered on the second plastic packaging material and a second external bump protruding out of the first interlayer rerouting structure, wherein the second chip is provided with a second active surface and a second back surface opposite to the second active surface, the second chip comprises a second chip bonding pad positioned on the second active surface, a first interlayer passivation layer positioned on the second active surface and a first interlayer interconnection bump positioned in the first interlayer passivation layer and bonded with the second chip bonding pad, and the forming surface of the second plastic packaging material, the outer surface of the first interlayer passivation layer and the top surface of the first interlayer interconnection bump are formed on a first interlayer continuous surface; the first interlayer re-wiring structure is formed on the first interlayer continuous surface, and the second external bump is partially embedded in the dielectric layer of the first interlayer re-wiring structure and is electrically connected to the top surface of the first interlayer interconnection bump via the first circuit of the first interlayer re-wiring structure;

When the second packaging body is pressed to the first packaging body and is adhered by the first anisotropic conductive film until the longitudinal gap between the first external connection convex block and the second external connection convex block is smaller than the maximum particle size of the conductive particles, the conductive particles are partially embedded in the second external connection convex block, so that the second external connection convex block is longitudinally and electrically connected with the first external connection convex block through the conductive particles;

wherein the type of the first chip or the second chip includes a memory chip and a logic chip.

2. The semiconductor package according to claim 1, wherein the conductive particles have a hardness greater than the first external bump.

3. The semiconductor package according to claim 1, wherein the first interlayer interconnect bump is relatively offset from a junction of the first and second external bumps.

4. The semiconductor package according to claim 1, wherein the shape of the conductive particles comprises any one of a sphere, a cone, a cube, and a polyhedron.

5. The semiconductor package according to claim 1, wherein the conductive particles have a particle size of less than 5 μm and are made of metal.

6. The semiconductor package according to claim 1, wherein the second package further comprises a second interposer rerouting structure and a third external bump protruding from the second interposer rerouting structure; the second chip further comprises a second interlayer passivation layer positioned on the second back surface and a second interlayer interconnection bump which is positioned in the second interlayer passivation layer and is electrically connected with the second chip bonding pad through a through silicon via, and the packaging surface of the second plastic packaging material, the outer surface of the second interlayer passivation layer and the top surface of the second interlayer interconnection bump are formed on the continuous surface of a second interlayer; the second interlayer re-wiring structure is formed on the second interlayer continuous surface, and the third external connection bump is partially embedded in the dielectric layer of the second interlayer re-wiring structure and is electrically connected to the top surface of the second interlayer interconnection bump via the second line of the second interlayer re-wiring structure.

7. The semiconductor package according to claim 1, wherein the first package further comprises: a first bottom layer rerouting structure and a second bottom layer rerouting structure;

The first chip further comprises a first bottom passivation layer positioned on the first active surface, a first bottom interconnection bump positioned in the first bottom passivation layer and bonded with the first chip bonding pad, a second bottom passivation layer positioned on the first back surface, and a second bottom interconnection bump positioned in the second bottom passivation layer and electrically connected with the first chip bonding pad through a through silicon via;

the forming surface of the first plastic package material, the outer surface of the first bottom passivation layer and the top surface of the first bottom interconnection bump are formed on the continuous surface of the first bottom layer; the first bottom layer rerouting structure is formed on the first bottom layer continuous surface, the first bottom layer rerouting structure having a dielectric layer, terminal pads formed on an outer surface of the dielectric layer, and third lines within the dielectric layer and electrically connecting the terminal pads and the first bottom layer interconnect bumps; the first package body further comprises solder balls implanted to the terminal pads;

the packaging surface of the first plastic packaging material, the outer surface of the second bottom passivation layer and the top surface of the second bottom interconnection bump are formed on the second bottom continuous surface; the second under-layer re-wiring structure is formed on the second under-layer continuous surface, and the first external bump is partially embedded in the dielectric layer of the second under-layer re-wiring structure and electrically connected to the top surface of the second under-layer interconnection bump via the fourth line of the second under-layer re-wiring structure.

8. The semiconductor package according to claim 6, further comprising:

a third package including a third chip, a third molding compound sealing the third chip, the third chip having a third active surface and a third back surface opposite the third active surface, the third chip including a third chip pad located on the third active surface, a first top passivation layer located on the third active surface, a first top interconnection bump located within the first top passivation layer and bonded to the third chip pad; the forming surface of the third plastic package material, the outer surface of the first top layer passivation layer and the top surface of the first top layer interconnection bump are formed on the continuous surface of the first top layer; the third package further includes a first top-level rewiring structure formed on the first top-level continuous surface;

a fourth external bump protruding from the first top-layer re-wiring structure, the fourth external bump being partially embedded in the dielectric layer of the first top-layer re-wiring structure and electrically connected to the top surface of the first top-layer interconnection bump via a fifth line of the first top-layer re-wiring structure; and

A second anisotropic conductive film including conductive particles, the second anisotropic conductive film being attached on an outer surface of the second interlayer rerouting structure;

the hardness of the conductive particles of the second anisotropic conductive film is greater than that of the fourth external connection bump, and when the third package is pressed onto the second package and bonded by the second anisotropic conductive film until the longitudinal gap between the third external connection bump and the fourth external connection bump is smaller than the maximum particle size of the conductive particles of the second anisotropic conductive film, the conductive particles are partially embedded in the fourth external connection bump, so that the fourth external connection bump is electrically connected with the third external connection bump in the longitudinal direction through the conductive particles.

9. The semiconductor package according to claim 8, wherein the second package comprises a plurality of packages stacked longitudinally, and adjacent two packages are bonded by an anisotropic conductive film.

10. A method for fabricating a semiconductor package, the method comprising:

providing a first packaging body with a first mounting surface, wherein the first packaging body comprises a first chip, a first plastic packaging material for sealing the first chip and a first external connection convex block positioned on the first mounting surface, the first chip is provided with a first active surface and a first back surface opposite to the first active surface, and the first chip comprises a first chip bonding pad positioned on the first active surface;

Attaching an anisotropic conductive film to the first mounting surface, the anisotropic conductive film comprising conductive particles;

providing a second package body, wherein the second package body comprises a second chip, a second plastic package material for sealing the second chip, a first interlayer rerouting structure covered on the second plastic package material and a second external bump protruding from the first interlayer rerouting structure, the second chip is provided with a second active surface and a second back surface opposite to the second active surface, the second chip comprises a second chip bonding pad positioned on the second active surface, a first interlayer passivation layer positioned on the second active surface and a first interlayer interconnection bump positioned in the first interlayer passivation layer and bonded with the second chip bonding pad, and the forming surface of the second plastic package material, the outer surface of the first interlayer passivation layer and the top surface of the first interlayer interconnection bump are formed on a first interlayer continuous surface; the first interlayer re-wiring structure is formed on the first interlayer continuous surface, and the second external bump is partially embedded in the dielectric layer of the first interlayer re-wiring structure and is electrically connected to the top surface of the first interlayer interconnection bump via the first circuit of the first interlayer re-wiring structure;

And pressing the second packaging body to the first packaging body, wherein the hardness of the conductive particles is larger than that of the second external protruding blocks, and when the second packaging body is pressed to the first packaging body and is adhered by the anisotropic conductive film until the longitudinal gap between the first external protruding blocks and the second external protruding blocks is smaller than the maximum particle size of the conductive particles, the conductive particles are locally embedded in the second external protruding blocks, so that the second external protruding blocks are longitudinally and electrically connected with the first external protruding blocks through the conductive particles.

11. The method of claim 10, wherein the second package further comprises a second intermediate layer rerouting structure and a third external bump protruding from the second intermediate layer rerouting structure, the method further comprising:

attaching a second anisotropic conductive film to an outer surface of the second interlayer rerouting structure, the second anisotropic conductive film comprising conductive particles;

providing a third packaging body, wherein the third packaging body comprises a third chip, a third plastic packaging material for sealing the third chip and a fourth external connection lug, the third chip is provided with a third active surface, and the third chip comprises a third chip bonding pad positioned on the third active surface; and

And pressing the third packaging body to the second packaging body, wherein the hardness of the conductive particles of the second anisotropic conductive film is larger than that of the fourth external connection convex block, and when the third packaging body is pressed to the second packaging body and is bonded by the second anisotropic conductive film until the longitudinal gap between the third external connection convex block and the fourth external connection convex block is smaller than the maximum particle size of the conductive particles of the second anisotropic conductive film, the conductive particles are partially embedded in the fourth external connection convex block, so that the fourth external connection convex block is longitudinally and electrically connected with the third external connection convex block through the conductive particles.

12. The method of claim 11, further comprising:

and pressing a plurality of second packages between the first package and the third package, wherein the second packages are bonded through anisotropic conductive films.

13. The method of claim 10, wherein the conductive particles also have a hardness greater than the first external bump.

14. The method of claim 10, wherein the first interlayer interconnect bump is relatively offset from a junction of the first and second external bumps.

15. The method of claim 10, wherein the conductive particles have a particle size of less than 5 microns and are metallic.