CN116525558A

CN116525558A - Package and method of forming the same

Info

Publication number: CN116525558A
Application number: CN202310206280.0A
Authority: CN
Inventors: 余振华; 王垂堂; 郑文豪; 邵栋梁; 蔡仲豪
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-04-04
Filing date: 2023-03-06
Publication date: 2023-08-01

Abstract

A package includes an encapsulant having a first side and a second side opposite the first side, first and second integrated circuit dies embedded in the encapsulant, and a first interposer on the first side of the encapsulant. The first interposer is mechanically and electrically coupled to the first integrated circuit die and the second integrated circuit die. The package also includes a second interposer on a second side of the encapsulant. The second interposer is mechanically and electrically coupled to the first integrated circuit die and the second integrated circuit die. The second interposer optically or electrically couples the first integrated circuit die to the second integrated circuit die. Embodiments of the present invention also provide methods of forming packages.

Description

Package and method of forming the same

Technical Field

Embodiments of the present invention relate to packages and methods of forming the same.

Background

The semiconductor industry has experienced a rapid growth due to the ever-increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the increase in integration density is due to repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices continues to grow, there is a trend toward smaller, more innovative semiconductor die packaging techniques.

Disclosure of Invention

Some embodiments of the invention provide a package comprising: a sealant having a first side and a second side opposite the first side; a first integrated circuit die and a second integrated circuit die embedded in the encapsulant; a first interposer on a first side of the encapsulant, the first interposer mechanically and electrically coupled to the first integrated circuit die and the second integrated circuit die; and a second interposer on the second side of the encapsulant, the second interposer mechanically and electrically coupled to the first integrated circuit die and the second integrated circuit die, the second interposer optically or electrically coupling the first integrated circuit die to the second integrated circuit die.

Other embodiments of the present invention provide a package comprising: a first integrated circuit die, the first integrated circuit die comprising: a first substrate; a first interconnect structure on a back side of the first substrate; and a second interconnect structure on the front side of the first substrate, wherein the second interconnect structure is electrically coupled to the first interconnect structure; a second integrated circuit die, the second integrated circuit die comprising: a second substrate; a third interconnect structure on a backside of the second substrate; and a fourth interconnect structure on the front side of the second substrate, wherein the fourth interconnect structure is electrically coupled to the third interconnect structure; and a first interposer physically contacting the second interconnect structure and the fourth interconnect structure, the first interposer electrically and optically coupling the second interconnect structure to the fourth interconnect structure.

Still further embodiments of the present invention provide a method of forming a package, comprising: attaching the interposer die to a carrier wafer; forming a first encapsulant over the carrier wafer and extending along sidewalls of the interposer die; bonding the first integrated circuit die and the second integrated circuit die to an interposer die, the interposer die electrically coupling the first integrated circuit die to the second integrated circuit die; forming a second encapsulant over the carrier wafer and extending along sidewalls of the first integrated circuit die and sidewalls of the second integrated circuit die; and bonding an interposer wafer to the first integrated circuit die and the second integrated circuit die, the interposer wafer electrically and optically coupling the first integrated circuit die to the second integrated circuit die.

Drawings

Aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawing figures. It is noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates a cross-sectional view of an integrated circuit die according to some embodiments.

Fig. 2 illustrates a cross-sectional view of an integrated circuit die in accordance with some embodiments.

Fig. 3 and 4 illustrate cross-sectional views of intermediate stages in the fabrication of an interposer, according to some embodiments.

FIG. 5 illustrates a cross-sectional view of an interposer, according to some embodiments.

FIG. 6 illustrates a cross-sectional view of an interposer, according to some embodiments.

FIG. 7 illustrates a cross-sectional view of an interposer, according to some embodiments.

FIG. 8 illustrates a cross-sectional view of an interposer, according to some embodiments.

FIG. 9 illustrates a cross-sectional view of an interposer, according to some embodiments.

FIG. 10 illustrates a cross-sectional view of an interposer, according to some embodiments.

FIG. 11 illustrates a cross-sectional view of an interposer, according to some embodiments.

FIG. 12 illustrates a cross-sectional view of an interposer, according to some embodiments.

Fig. 13-17 illustrate cross-sectional views at intermediate stages in the manufacture of a package assembly, in accordance with some embodiments.

Fig. 18 illustrates a cross-sectional view of a package assembly according to some embodiments.

Fig. 19-23 illustrate cross-sectional views at intermediate stages in the manufacture of a package assembly, in accordance with some embodiments.

Fig. 24 illustrates a cross-sectional view of a package assembly according to some embodiments.

Fig. 25-30 illustrate cross-sectional views at intermediate stages in the manufacture of a package assembly, in accordance with some embodiments.

Fig. 31 illustrates a cross-sectional view of a package assembly according to some embodiments.

Fig. 32A and 32B illustrate plan and cross-sectional views of an interconnect structure of a package assembly according to some embodiments.

Fig. 33A and 33B illustrate plan and cross-sectional views of an interconnect structure of a package assembly according to some embodiments.

Fig. 34 illustrates a cross-sectional view of a package assembly according to some embodiments.

Fig. 35 illustrates a cross-sectional view of a package assembly according to some embodiments.

Fig. 36 illustrates a plan view of an interconnect structure of a package assembly according to some embodiments.

Fig. 37 illustrates a cross-sectional view of a package assembly according to some embodiments.

Fig. 38 illustrates a cross-sectional view of a package assembly according to some embodiments.

Fig. 39 illustrates a cross-sectional view of a package assembly according to some embodiments.

Fig. 40 illustrates a cross-sectional view of a package assembly according to some embodiments.

Fig. 41 illustrates a cross-sectional view of a package assembly according to some embodiments.

Fig. 42 illustrates a cross-sectional view of a package assembly according to some embodiments.

Fig. 43 illustrates a cross-sectional view of a package assembly according to some embodiments.

Fig. 44 illustrates a cross-sectional view of a package assembly according to some embodiments.

Fig. 45 illustrates a cross-sectional view of a package assembly according to some embodiments.

Fig. 46 illustrates a cross-sectional view of a package assembly according to some embodiments.

Fig. 47 illustrates a cross-sectional view of a package assembly according to some embodiments.

Fig. 48 illustrates a cross-sectional view of a package assembly according to some embodiments.

Fig. 49 illustrates a cross-sectional view of a package assembly according to some embodiments.

Fig. 50 illustrates a cross-sectional view of a multi-layer package assembly, according to some embodiments.

Fig. 51 illustrates a cross-sectional view of a multi-layer package assembly, according to some embodiments.

Fig. 52 illustrates a cross-sectional view of an integrated circuit package, in accordance with some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, of the different components used to implement the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, spatially relative terms such as "under …," "under …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Embodiments will be described with respect to embodiments in a specific context, namely an integrated circuit package and method of forming the same. According to various embodiments, an integrated circuit package includes a plurality of integrated circuit dies encapsulated in an encapsulant, wherein each integrated circuit die includes a front-side interconnect structure and a back-side interconnect structure. The package also includes a first interposer in physical and electrical contact with the backside interconnect structure of the integrated circuit die and a second interposer in physical and electrical contact with the front side interconnect structure of the integrated circuit die. The first interposer may be an active interposer (including active electrical devices), a passive interposer (including passive electrical devices), an input/output (I/O) interposer (including I/O circuitry), or the like. The second interposer may be an active interposer (including active electrical devices), a passive interposer (including passive electrical devices), an optical or photonic interposer (including optical devices such as modulators and/or waveguides), a hybrid (electrical/optical) interposer (including electrical and optical devices), or the like. In various embodiments, the second interposer allows coupling of the front-side interconnect structure of the integrated circuit die independent of the back-side interconnect structure of the integrated circuit die (e.g., the super power rail), as well as the interconnect structure and the through vias of the first interposer. In various embodiments, the first interposer and the second interposer are hybrid bonded to the integrated circuit die, which reduces the thermal resistance of the resulting integrated circuit package. By electrically coupling the integrated circuit die via the second interposer, flexibility in circuit design of the integrated circuit package may be improved.

Fig. 1 illustrates a cross-sectional view of an integrated circuit die 50 according to some embodiments. The integrated circuit die 50 will be packaged in subsequent processing to form an integrated circuit package. Each integrated circuit die 50 may be a logic device (e.g., a Central Processing Unit (CPU), a graphics processing unit (CPU), a microcontroller, etc.), a memory device (e.g., a Dynamic Random Access Memory (DRAM) die, a Static Random Access Memory (SRAM) die, etc.), a power management device (e.g., a Power Management Integrated Circuit (PMIC) die), a Radio Frequency (RF) device, a sensor device, a microelectromechanical system (MEMS) device, a signal processing device (e.g., a Digital Signal Processing (DSP) die), a front-end device (e.g., an analog front-end (AFE) die), etc., or a combination thereof (e.g., a system on a chip (SoC) die). The integrated circuit die 50 may be formed in a wafer that may include different die areas that are singulated in subsequent steps to form a plurality of integrated circuit die 50. Integrated circuit die 50 includes a semiconductor substrate 52, devices 54, front side interconnect structures 56, back side interconnect structures 58, carrier 60, and die connectors 62.

The semiconductor substrate 52 may be a doped or undoped silicon substrate, or an active layer of a semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 52 may comprise other semiconductor materials such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or a combination thereof. Other substrates, such as multi-layer or gradient substrates, may also be used. The semiconductor substrate 52 has an active surface or front side surface (e.g., an upwardly facing surface) and a passive surface or back side surface (e.g., a downwardly facing surface).

A device 54 (shown by a transistor) is located at the active surface of the semiconductor substrate 52. Device 54 may be an active device (e.g., transistor, diode, etc.), capacitor, resistor, etc. The passive surface may be devoid of devices. In the illustrated embodiment, the integrated circuit die 50 includes a full-gate-all-around (GAA) transistor, such as a nanostructure field effect transistor (NSFET). In other embodiments, the integrated circuit die 50 may include fin field effect transistors (finfets), planar FETs, or the like in addition to or in lieu of GAA transistors.

The front side interconnect structure 56 is located above the active surface of the semiconductor substrate 52 and is used to electrically connect the devices 54 to form an integrated circuit. The front side interconnect structure 56 may include one or more dielectric layers 56A and corresponding metallization layers 56B (including conductive lines and vias) located in the dielectric layers 56A. Acceptable dielectric materials for dielectric layer 56A include low-k dielectric materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped Silicate Glass (USG), and the like. Acceptable dielectric materials for dielectric layer 56A also include oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; etc.; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, and the like. Other dielectric materials may also be used, such as polymers, e.g., polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB) based polymers, and the like. The metallization layer 56B may be formed of a conductive material, such as a metal, e.g., copper, cobalt, aluminum, gold, combinations thereof, and the like. The front-side interconnect structure 56 may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like.

Backside interconnect structures 58 are formed on the passive surface of semiconductor substrate 52 and may be used to power devices 54 of semiconductor substrate 52. The semiconductor substrate 52 is interposed between a front side interconnect structure 56 and a back side interconnect structure 58. The backside interconnect structure 58 may include one or more dielectric layers 58A and corresponding metallization layers 58B (including conductive lines and vias) located in the dielectric layers 58A. One or more dielectric layers 58A may be formed using similar materials and methods as one or more dielectric layers 56A. The metallization layer 58B may be formed of a conductive material, such as a metal, e.g., copper, cobalt, aluminum, gold, combinations thereof, and the like. The backside interconnect structure 58 may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like.

In some embodiments, the backside interconnect structure 58 is electrically coupled to the device 54 and/or the front side interconnect structure 56 using the super power rail 64. In some embodiments, the super power rail 64 includes Through Substrate Vias (TSVs) extending through the semiconductor substrate 52 to couple to the devices 54. The super power rail 64 may be formed of a conductive material, such as a metal, e.g., copper, cobalt, aluminum, gold, combinations thereof, and the like. In some embodiments, the super power rail 64 may be formed as part of the backside interconnect structure 58.

The carrier 60 may be bonded to the front side interconnect structure 56 such that the front side interconnect structure 56 is interposed between the carrier 60 and the semiconductor substrate 52. Carrier 60 may comprise a semiconductor material (e.g., silicon, etc.) or a dielectric material (e.g., quartz, etc.). In some embodiments, carrier 60 and semiconductor substrate 52 comprise the same semiconductor material. In other embodiments, carrier 60 and semiconductor substrate 52 comprise different semiconductor materials. In some embodiments, the carrier 60 may be used as a support in forming the backside interconnect structure 58. As described in more detail below, in some embodiments, carrier 60 may be removed during packaging.

Die attach 62 is located on back side 50BS of integrated circuit die 50. Die attach 62 may be conductive posts, pads, etc. that make external connections. As described in more detail below, die connectors 62 may be used as bond pads for bonding integrated circuit die 50 to other package components during packaging. Die connectors 62 are located in and/or on backside interconnect structures 58. For example, die connectors 62 may be part of the uppermost metallization layer of backside interconnect structure 58 (the metallization layer furthest from semiconductor substrate 52). Die connectors 62 may be formed of a metal such as copper, aluminum, or the like, and die connectors 62 may be formed by plating, or the like, for example.

Alternatively, a solder region (not separately shown) may be provided on die attach 62 during formation of integrated circuit die 50. The solder regions may be used to perform Chip Probe (CP) testing on the integrated circuit die 50. For example, the solder regions may be solder balls, solder bumps, etc., the solder regions being used to attach the chip probes to the die connectors 62. Chip probing tests may be performed on the integrated circuit die 50 to determine if the integrated circuit die 50 is a Known Good Die (KGD). Thus, only the integrated circuit die 50 of KGD is subjected to subsequent processing and packaged, while the die that fails the chip probe test is not packaged. After testing, the solder areas may be removed in a subsequent processing step.

An insulating layer 66 is located at the back side 50BS of the integrated circuit die 50. An insulating layer 66 is located in and/or on the backside interconnect structure 58. For example, insulating layer 66 may be the uppermost dielectric layer of backside interconnect structure 58 (the dielectric layer furthest from semiconductor substrate 52). Insulating layer 66 laterally encapsulates die attach 62. The insulating layer 66 may be an oxide, nitride, carbide, polymer, or the like, or a combination thereof. The insulating layer 66 may be formed by spin coating, lamination, chemical Vapor Deposition (CVD), or the like, for example. Initially, insulating layer 66 may bury die attach 62 such that a bottom surface of insulating layer 66 is below a bottom surface of die attach 62. In some embodiments, die connectors 62 are exposed through insulating layer 66 during formation of integrated circuit die 50. In other embodiments, die connectors 62 are exposed through insulating layer 66 during packaging of integrated circuit die 50. Exposing die attach 62 may remove any solder areas that may exist on die attach 62. A removal process may be applied to the various layers to remove excess material over die attach 62. The removal process may be a planarization process such as Chemical Mechanical Polishing (CMP), etch back, combinations thereof, and the like. After the planarization process, the bottom surfaces of insulating layer 66 and die attach 62 are substantially coplanar (within process variations) such that they are flush with one another.

In some embodiments, integrated circuit die 50 is a stacked device that includes a plurality of semiconductor substrates 52. For example, the integrated circuit die 50 may be a memory device including a plurality of memory dies, such as a Hybrid Memory Cube (HMC) device, a High Bandwidth Memory (HBM) device, or the like. In such an embodiment, the integrated circuit die 50 includes a plurality of semiconductor substrates 52, the plurality of semiconductor substrates 52 being interconnected by through-substrate vias (TSVs) (e.g., through-silicon vias). Each semiconductor substrate 52 may (or may not) have a separate interconnect structure.

Fig. 2 illustrates a cross-sectional view of an integrated circuit die 50' in accordance with some embodiments. Integrated circuit die 50' is similar to integrated circuit die 50 (see fig. 1), wherein like components are denoted by like reference numerals and a description of like components is not repeated here. In the illustrated embodiment, the integrated circuit die 50' includes conductive vias 68 extending through the carrier 60 and electrically coupled to the front-side interconnect structure 56. As an example of forming the conductive vias 68, openings are formed in the carrier 60 by, for example, etching, milling, laser techniques, combinations thereof, and the like. A thin dielectric material may be formed in the opening, for example by using an oxidation technique. A thin barrier layer may be conformally deposited in the opening, such as by CVD, atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), thermal oxidation, combinations thereof, and the like. The barrier layer may be formed of an oxide, nitride, carbide, combinations thereof, or the like. A conductive material may be deposited over the barrier layer and in the opening. The conductive material may be formed by an electrochemical plating process, CVD, ALD, PVD, combinations thereof, or the like. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, combinations thereof, and the like. Excess conductive material and barrier layer are removed from the upper surface of carrier 60 by, for example, CMP. The barrier layer and the remainder of the conductive material form a conductive via 68.

Fig. 3 and 4 illustrate cross-sectional views of intermediate stages in the fabrication of interposer 200, according to some embodiments. In fig. 3, a wafer 100 is obtained or formed. Wafer 100 includes a plurality of device regions (e.g., device region 100A) that are to be singulated in subsequent processing to form individual devices. In some embodiments, the interposer 200 is formed in a corresponding device region of the wafer 100. Interposer 200 may include substrate 102, interconnect structure 104, and conductive vias 106.

The substrate 102 may be a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multi-layer semiconductor substrate, or the like. The substrate 102 may comprise a semiconductor material, such as silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or a combination thereof. Other substrates, such as multi-layer or gradient substrates, may also be used. The substrate 102 may be doped or undoped.

In some embodiments, the substrate 102 generally does not include active devices located therein, although the interposer 200 may include passive devices formed in and/or on a front or active surface (e.g., the surface facing upward in fig. 3) of the substrate 102. In other embodiments, active devices (e.g., transistors, diodes, etc.) and passive devices (capacitors, resistors, etc.) may be formed in and/or on the front surface of the substrate 102. In some embodiments, the interposer 200 may include optics, such as a modulator and/or a waveguide. Interposer 200 may be an active interposer (including active electrical devices such as SRAM devices), a passive interposer (including passive electrical devices such as capacitors), an I/O interposer (including I/O circuitry), an optical or photonic interposer (including optical devices such as modulators and/or waveguides), a hybrid (electrical/optical) interposer (including electrical and optical devices), or the like.

Interconnect structure 104 is located over the front surface of substrate 102 and is used to electrically connect devices (if any) of substrate 102. The interconnect structure 104 may include one or more dielectric layers 104A and corresponding metallization layers 104B (including conductive lines and vias) located in the dielectric layers 104A. The interconnect structure 104 may be formed using similar materials and methods as the front side interconnect structure 56 described above with reference to fig. 1, and will not be repeated here.

In some embodiments, die connectors 110 and dielectric layer 108 are located at front side 100F of wafer 100. In particular, wafer 100 may include die connectors 110 and dielectric layer 108, die connectors 110 and dielectric layer 108 being similar to die connectors 62 and dielectric layer 66, respectively, of integrated circuit die 50 described above with reference to fig. 1, and will not be repeated here. In some embodiments, die connectors 110 may be part of an upper metallization layer of interconnect structure 104 (the metallization layer furthest from semiconductor substrate 102) and dielectric layer 108 may be part of an upper dielectric layer of interconnect structure 104 (the dielectric layer furthest from semiconductor substrate 102). In other embodiments, die connectors 110 and dielectric layer 108 may be formed separately from interconnect structure 104. As described in more detail below, the die connectors 110 may be used as bond pads for bonding a package component (such as, for example, an integrated circuit die) to the wafer 100. Accordingly, the die connectors 110 may also be referred to as bond pads, and the die connectors 110 and the dielectric layer 108 may be collectively referred to as a bond layer.

Conductive vias 106 extend into the interconnect structure 104 and/or the substrate 102. The conductive via 106 is electrically connected to the metallization layer 104B of the interconnect structure 104. Conductive via 106 is also sometimes referred to as a Through Substrate Via (TSV). As an example of forming the conductive via 106, an opening may be formed in the interconnect structure 104 and/or the substrate 102 by, for example, etching, milling, laser techniques, combinations thereof, and the like. A thin dielectric material may be formed in the opening, for example by using an oxidation technique. A thin barrier layer may be conformally deposited in the opening, such as by CVD, ALD, PVD, thermal oxidation, combinations thereof, and the like. The barrier layer may be formed of an oxide, nitride, carbide, combinations thereof, or the like. A conductive material may be deposited over the barrier layer and in the opening. The conductive material may be formed by an electrochemical plating process, CVD, ALD, PVD, combinations thereof, or the like. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, combinations thereof, and the like. Excess conductive material and barrier layer are removed from the surface of the interconnect structure 104 or the substrate 102, for example, by CMP. The barrier layer and the remaining portion of the conductive material form a conductive via 106.

In fig. 4, the substrate 102 is thinned to expose the conductive vias 106. The exposure of the conductive via 106 may be accomplished by a thinning process, such as a grinding process, CMP, etch back, combinations thereof, and the like. In some embodiments (not separately shown), the thinning process for exposing the conductive vias 106 includes CMP, and the conductive vias 106 protrude at the backside 100BS of the wafer 100 due to dishing that occurs during CMP. In such an embodiment, an insulating layer (not separately shown) may optionally be formed on the back surface of the substrate 102 so as to surround the protruding portion of the conductive via 106. The insulating layer may be formed of a silicon-containing insulator such as silicon nitride, silicon oxide, silicon oxynitride, or the like, and may be formed by a suitable deposition method such as spin coating, CVD, plasma Enhanced CVD (PECVD), high density plasma CVD (HDP-CVD), or the like. After thinning the substrate 102, the conductive vias 106 and the insulating layer (if present) or exposed surface of the substrate 102 are coplanar (within process variations) such that they are flush with each other and exposed at the backside 100BS of the wafer 100.

After thinning the wafer 100, die connectors 114 and dielectric layer 112 are formed at the backside 100BS of the wafer 100. In particular, wafer 100 may include die connectors 114 and dielectric layer 112, die connectors 114 and dielectric layer 112 being similar to die connectors 62 and dielectric layer 66, respectively, of integrated circuit die 50 described above with reference to fig. 1, and will not be repeated here. In some embodiments, a planarization process (such as, for example, CMP) is performed on the die connectors 114 and the dielectric layer 112 such that the exposed surfaces of the die connectors 114 and the dielectric layer 112 are flush with each other within process variations of the planarization process. As described in more detail below, the die connectors 114 may be used as bond pads for bonding other package components to the interposer 200. Accordingly, the die connectors 114 may also be referred to as bond pads, and the die connectors 114 and the dielectric layer 112 may be collectively referred to as a bond layer.

In addition, a singulation process (singulation process) is performed on the wafer 100 by dicing along scribe line regions (e.g., around the device region 100A). Singulation processes may include sawing, etching, cutting (dicing), combinations thereof, and the like. The singulation process forms the interposer 200 from the singulated portions of the wafer 100.

Fig. 5 illustrates a cross-sectional view of an interposer 300 according to some embodiments. The interposer 300 is similar to the interposer 200 (see fig. 4), wherein like components are denoted by like reference numerals, and the description of like components is not repeated here. The interposer 300 may be formed using process steps similar to those described above with reference to fig. 3 and 4, and will not be repeated here. In the illustrated embodiment, interposer 300 includes passive electrical devices and does not include active electrical devices. Interposer 300 may also be referred to as a passive interposer. In the illustrated embodiment, interposer 300 includes dielectric layer 108 and die connectors 110 at front side 300F of interposer 300, and dielectric layer 112 and die connectors 114 at back side 300B of interposer 300.

Fig. 6 illustrates a cross-sectional view of an interposer 300' according to some embodiments. The interposer 300' is similar to the interposer 300 (see fig. 5), wherein like components are denoted by like reference numerals, and the description of like components is not repeated here. The interposer 300' may be formed in a similar manner to the interposer 300 (see fig. 5), and will not be repeated here. In the illustrated embodiment, interposer 300' includes passive electrical devices and does not include active electrical devices. Interposer 300' may also be referred to as a passive interposer. Unlike interposer 300, interposer 300 'does not include conductive vias 106 (see fig. 5) located within substrate 102 and die connectors 114 and dielectric layer 112 (see fig. 5) located at backside 300B of interposer 300'. In the illustrated embodiment, the interposer 300 'includes a dielectric layer 108 and die connectors 110 at a front side 300F of the interposer 300'.

Fig. 7 illustrates a cross-sectional view of an interposer 400, according to some embodiments. The interposer 400 is similar to the interposer 200 (see fig. 4), wherein like components are denoted by like reference numerals, and the description of like components is not repeated here. The interposer 400 may be formed using process steps similar to those described above with reference to fig. 3 and 4, and will not be repeated here. In the illustrated embodiment, interposer 400 includes devices 402, devices 402 containing active and/or passive electrical devices. Interposer 400 may also be referred to as an active interposer. In the illustrated embodiment, interposer 400 includes dielectric layer 108 and die connectors 110 at front side 400F of interposer 400 and dielectric layer 112 and die connectors 114 at back side 400B of interposer 400.

Fig. 8 illustrates a cross-sectional view of an interposer 400' according to some embodiments. The interposer 400' is similar to the interposer 400 (see fig. 7), wherein like components are denoted by like reference numerals, and description of like components is not repeated here. The interposer 400' may be formed in a similar manner to the interposer 400 (see fig. 7), and will not be repeated here. In the illustrated embodiment, the interposer 400' includes a device 402, the device 402 containing active and/or passive electrical devices. Interposer 400' may also be referred to as an active interposer. Unlike interposer 400, interposer 400 'does not include conductive vias 106 (see fig. 7) located within substrate 102 and die connectors 114 and dielectric layer 112 (see fig. 7) located at backside 400B of interposer 400'. In the illustrated embodiment, the interposer 400 'includes a dielectric layer 108 and die connectors 110 at a front side 400F of the interposer 400'.

Fig. 9 illustrates a cross-sectional view of an interposer 500, according to some embodiments. Interposer 500 is similar to interposer 200 (see fig. 4), where like components are denoted by like reference numerals, and descriptions of like components are not repeated here. The interposer 500 may be formed using process steps similar to those described above with reference to fig. 3 and 4, and will not be repeated here. In the illustrated embodiment, interposer 500 includes a device 502, which device 502 includes optical devices, such as modulators, photodetectors, phase shifters, switches, and the like. Interposer 500 may not include active and passive electrical devices. Further, the interconnect structure 104 may include one or more optical waveguides 504 and may or may not include a metallization layer 104B (see fig. 4). Interposer 500 may also be referred to as an optical interposer. In the illustrated embodiment, interposer 500 includes dielectric layer 108 and die connectors 110 at front side 500F of interposer 500 and dielectric layer 112 and die connectors 114 at back side 500B of interposer 500.

Fig. 10 illustrates a cross-sectional view of an interposer 500' according to some embodiments. The interposer 500' is similar to the interposer 500 (see fig. 9), wherein like components are denoted by like reference numerals, and the description of like components is not repeated here. The interposer 500' may be formed in a similar manner to the interposer 500 (see fig. 9), and will not be repeated here. In the illustrated embodiment, interposer 500' includes a device 502, which device 502 includes optical devices, such as modulators, photodetectors, phase shifters, switches, and the like. Interposer 500' may not include active and passive electrical devices. Further, the interconnect structure 104 may include one or more optical waveguides 504 and may or may not include a metallization layer 104B (see fig. 4). Interposer 500' may also be referred to as an optical interposer. Unlike interposer 500, interposer 500 'does not include conductive vias 106 (see fig. 9) within substrate 102 and die connectors 114 and dielectric layer 112 (see fig. 9) located at backside 500B of interposer 500'. In the illustrated embodiment, the interposer 500 'includes a dielectric layer 108 and die connectors 110 at a front side 500F of the interposer 500'.

Fig. 11 illustrates a cross-sectional view of an interposer 600 according to some embodiments. Interposer 600 is similar to interposer 200 (see fig. 4), where like components are denoted by like reference numerals, and the description of like components is not repeated here. The interposer 600 may be formed using process steps similar to those described above with reference to fig. 3 and 4, and will not be repeated here. In the illustrated embodiment, interposer 600 includes devices (not shown) that contain optical devices and active and/or passive electrical devices. Further, in addition to the metallization layer 104B, the interconnect structure 104 may include one or more optical waveguides 602. Interposer 600 may also be referred to as a hybrid interposer. In the illustrated embodiment, interposer 600 includes dielectric layer 108 and die connectors 110 at front side 600F of interposer 600 and dielectric layer 112 and die connectors 114 at back side 600B of interposer 600.

Fig. 12 illustrates a cross-sectional view of an interposer 600' according to some embodiments. Interposer 600' is similar to interposer 600 (see fig. 11), where like components are denoted by like reference numerals, and descriptions of like components are not repeated here. Interposer 600' may be formed in a similar manner to interposer 600 (see fig. 11), and will not be repeated here. In the illustrated embodiment, interposer 600' includes devices (not shown) that contain optical devices and active and/or passive electrical devices. Further, in addition to the metallization layer 104B, the interconnect structure 104 may include one or more optical waveguides 602. Interposer 600' may also be referred to as a hybrid interposer. Unlike interposer 600, interposer 600 'does not include conductive vias 106 (see fig. 11) located within substrate 102 and die connectors 114 and dielectric layer 112 (see fig. 11) located at backside 600B of interposer 600'. In the illustrated embodiment, interposer 600 'includes dielectric layer 108 and die connectors 110 at front side 600F of interposer 600'.

Fig. 13-17 illustrate cross-sectional views at intermediate stages in the manufacture of a package assembly 900 in accordance with some embodiments. In fig. 13, a carrier wafer 700 is provided or formed. The carrier wafer 700 serves as a platform or support for the packaging process described below. In some embodiments, the carrier wafer 700 includes a semiconductor material (e.g., silicon, etc.), a dielectric material (e.g., quartz, etc.), combinations thereof, and the like. As described in more detail below, wafer level package assemblies are formed over a carrier wafer, which are singulated into individual die level package assemblies 900 in subsequent processing. In particular, carrier wafer 700 includes a plurality of package regions (e.g., package regions 700A and 700B) that correspond to respective die-level package assemblies 900.

The interposer 200 (see fig. 4) is attached to a carrier wafer 700. In the illustrated embodiment, one interposer 200 is attached in each package region (e.g., package region 700A or 700B) of carrier wafer 700. In other embodiments, two or more interposers 200 may be attached in each package region of the carrier wafer 700 based on the design requirements of the package assembly 900. Interposer 200 may be an active interposer (e.g., including active electrical devices such as SRAM devices), a passive interposer (e.g., including passive electrical devices such as capacitors), an I/O interposer (including I/O circuitry), or the like. In the illustrated embodiment, the front side 200F of the interposer 200 is attached to the carrier wafer 700. In other embodiments, the backside 200B of the interposer 200 is attached to the carrier wafer 700.

In the illustrated embodiment, the interposer 200 is attached to the carrier wafer 700 using a bonding method (such as, for example, fusion bonding). In some embodiments, when the carrier wafer 700 includes a dielectric material, the interposer 200 is attached to the carrier wafer 700 by fusion bonding the dielectric layer 108 at the front side 200F of the interposer 200 to the carrier wafer 700. In some embodiments, when the carrier wafer 700 includes semiconductor material, a dielectric layer (not shown) is formed over the carrier wafer 700, and the interposer 200 is attached to the carrier wafer 700 by fusion bonding the dielectric layer 108 at the front side 200F of the interposer 200 to the dielectric layer formed on the carrier wafer 700. In some embodiments, prior to the bonding process, the bonding surfaces of interposer 200 (e.g., the bonding surface of dielectric layer 108) and carrier wafer 700 (or the bonding surface of the dielectric layer formed on carrier wafer 700) are cleaned and then activated using a plasma process (e.g., such as an Ar plasma process). Subsequently, an annealing process may be performed to improve the bond between the interposer 200 and the carrier wafer 700. In other embodiments, the interposer 200 is attached to the carrier wafer 700 using an adhesive.

After attaching the interposer 200 to the carrier wafer 700, an encapsulant 702 is formed over and around the interposer 200. The encapsulant 702 may be a molding compound, epoxy, or the like. The encapsulant 702 may be applied by compression molding, transfer molding, or the like, and the encapsulant 702 is formed over the carrier wafer 700 such that the intermediate layer 200 is buried or covered. The encapsulant 702 may be applied in liquid or semi-liquid form and then the encapsulant 702 is subsequently cured. The encapsulant 702 may be thinned to expose the dielectric layer 112 and die connectors 114 at the back side 200B of the interposer 200. The thinning process may be a grinding process, CMP, etch back, combinations thereof, or the like. After the thinning process, the top surfaces of dielectric layer 112, die attach 114, and encapsulant 702 are coplanar (within process variations) so that they are flush with one another.

After the encapsulant 702 is formed, the back side 50BS of the integrated circuit die 50 (e.g., the first integrated circuit die 50A and the second integrated circuit die 50B) is attached to the back side 200B of each interposer 200. In the illustrated embodiment, two integrated circuit dies 50 are attached to each interposer 200. In other embodiments, one or more integrated circuit die 50 may be attached to each interposer 200 based on the design requirements of the package assembly 900. In some embodiments, the first integrated circuit die 50A is a logic device, such as a CPU, GPU, etc., and the second integrated circuit die 50B is a memory device, such as a DRAM die, HMC module, HBM module, etc. In some embodiments, the first integrated circuit die 50A is the same type of device (e.g., soC) as the second integrated circuit die 50B.

In some embodiments, the integrated circuit die 50 is attached to the respective interposer 200 by a bonding process (e.g., a hybrid bonding process). In such an embodiment, the integrated circuit die 50 is bonded to the respective interposer 200 by fusion bonding the dielectric layer 66 at the back side 50BS of the integrated circuit die 50 to the dielectric layer 112 at the back side 200B of the respective interposer 200, and by fusion bonding the die connectors 62 at the back side 50BS of the integrated circuit die 50 to the die connectors 114 at the back side 200B of the respective interposer 200. In some embodiments, prior to the bonding process, the bonding surfaces of interposer 200 (e.g., the bonding surfaces of dielectric layer 112 and die connectors 114) and integrated circuit die 50 (e.g., the bonding surfaces of dielectric layer 66 and die connectors 62) are cleaned and then activated using a plasma process (e.g., an Ar plasma process). Subsequently, an annealing process may be performed to improve the bond between the interposer 200 and the integrated circuit die 50. The integrated circuit die 50 and the corresponding interposer 200 are electrically coupled by bonding structures formed by fusion bonding the die connectors 62 of the integrated circuit die 50 to the die connectors 114 of the corresponding interposer 200.

In fig. 14, an encapsulant 704 is formed over and around the integrated circuit die 50. After formation, an encapsulant 704 encapsulates the integrated circuit die 50. The encapsulant 704 may be formed using similar materials and methods as the encapsulant 702 described above with reference to fig. 13, and will not be repeated here. The encapsulant 704 may be thinned to expose the integrated circuit die 50. The thinning process may be a grinding process, CMP, etch back, combinations thereof, or the like. In some embodiments, the thinning process also removes carrier 60 of integrated circuit die 50. After the thinning process, the encapsulant 704 and the top surface of the front-side interconnect structure 56 of the integrated circuit die 50 are coplanar (within process variations) so that they are flush with each other. In some embodiments, the encapsulant 702 and the encapsulant 704 comprise the same material and the interface between the encapsulant 702 and the encapsulant 704 may be undetectable. In other embodiments, encapsulant 702 and encapsulant 704 comprise different materials.

In the illustrated embodiment, interposer 200 and integrated circuit die 50 are encapsulated by encapsulants 702 and 704 in a two-stage process as described above. In other embodiments, interposer 200 and integrated circuit die 50 may be encapsulated in a single stage process. In such an embodiment, the formation of encapsulant 702 is omitted, and after attaching both interposer 200 and integrated circuit die 50 to carrier wafer 700, encapsulant 704 is formed such that encapsulant 704 fills the gaps between adjacent interposers 200 and the gaps between adjacent integrated circuit die 50.

In fig. 15, an interposer wafer 800 is attached to an integrated circuit die 50. The interposer wafer 800 may include a plurality of die-level intermediaries 850 such that the die-level intermediaries 850 correspond to respective package regions of the carrier wafer 700. Interposer wafer 800 may be similar to interposer wafer 100 (see fig. 4), with like components being denoted by like reference numerals, and description of like components is not repeated here. Interposer wafer 800 may be formed using process steps similar to those described above with reference to fig. 3 and 4, except that the formation of conductive vias 106, dielectric layer 112, and die connectors 114 is omitted. In some embodiments, interposer 850 may be an active interposer (e.g., including active electrical devices such as SRAM devices), a passive interposer (e.g., including passive electrical devices such as capacitors), an I/O interposer (including I/O circuitry), an optical or photonic interposer (e.g., including optical devices such as modulators and/or waveguides), a hybrid (electrical/optical) interposer (including electrical and optical devices), and the like.

In some embodiments, die connectors 706 are formed in the uppermost dielectric layer of the front side interconnect structure 56 of the integrated circuit die 50 (e.g., the dielectric layer of the front side interconnect structure 56 furthest from the substrate of the respective integrated circuit die 50) prior to attaching the interposer wafer 800 to the integrated circuit die 50. In some embodiments, die connectors 706 may be formed using similar materials and methods as die connectors 62 described above with reference to fig. 2, and will not be repeated here. In some embodiments, interposer wafer 800 is attached to integrated circuit die 50 by a bonding process (e.g., a hybrid bonding process). In such an embodiment, interposer wafer 800 is bonded to integrated circuit die 50 by fusion bonding dielectric layer 108 of interposer wafer 800 to the uppermost dielectric layer of front side interconnect structure 56 of integrated circuit die 50, and by fusion bonding die connectors 110 of interposer wafer 800 to die connectors 706 of integrated circuit die 50. In some embodiments, prior to the bonding process, the bonding surfaces of interposer wafer 800 (e.g., the bonding surfaces of dielectric layer 108 and die connectors 110 of interposer wafer 800) and the bonding surfaces of integrated circuit die 50 (e.g., the bonding surfaces of the uppermost dielectric layer of front side interconnect structure 56 of integrated circuit die 50 and the bonding surfaces of die connectors 706 of integrated circuit die 50) are cleaned and then activated using a plasma process (e.g., such as an Ar plasma process). Subsequently, an annealing process may be performed to improve the bond between the interposer wafer 800 and the integrated circuit die 50. The interposer wafer 800 and the integrated circuit die 50 are electrically coupled by bonding structures formed by fusion bonding the die connectors 110 of the interposer wafer 800 to the die connectors 706 of the integrated circuit die 50.

In fig. 16, after the interposer wafer 800 is attached to the integrated circuit die 50, the carrier wafer 700 is separated from the interposer 200. Conductive connections 708 are then formed on the die connections 110 of the interposer 200. The conductive connectors 708 may be Ball Grid Array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connection 708 may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive connection 708 is formed by first forming a solder layer by evaporation, electroplating, printing, solder transfer, solder ball placement, and the like. Once the solder layer is formed on the structure, reflow may be performed to shape the material into the desired bump shape. In another embodiment, the conductive connection 708 includes a metal post (such as a copper post) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal posts may be solderless and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillars. The metal cap layer may include nickel, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or combinations thereof, and may be formed by a plating process.

Further, singulation processes are performed on the resulting wafer level structure by dicing along scribe line regions (e.g., around the package regions 700A and 700B). Singulation processes may include sawing, etching, cutting, combinations thereof, and the like. For example, singulation processes may include sawing the encapsulants 702 and 704, as well as the interconnect structure 104 and the substrate 102 of the interposer wafer 800. The singulation process singulates package regions (e.g., package region 700A) from adjacent package regions (e.g., package region 700B) to form singulated package assemblies 900. Such a package assembly 900 is shown in fig. 17. The singulation process further forms the interposer 850 from the singulated portions of the interposer wafer 800. As a result of the singulation process, the interposer 850 and the outer sidewalls of the encapsulant 704 are laterally co-bounded (within process variations), as shown in fig. 17.

Fig. 18 illustrates a cross-sectional view of a package assembly 1100 according to some embodiments. Package assembly 1100 is similar to package assembly 900, wherein like components are denoted by like reference numerals and description of like components is not repeated here. In contrast to package assembly 900, package assembly 1100 includes interposer 1000 instead of interposer 850. Interposer 1000 is similar to interposer 850, with like components being denoted by like reference numerals and description of like components is not repeated here. In contrast to interposer 850, interposer 1000 includes conductive vias 106, dielectric layer 112, and die connectors 114. The conductive vias 106, dielectric layer 112, and die connectors 114 may be formed as described above with reference to fig. 4, and will not be repeated here.

Fig. 19-23 illustrate cross-sectional views at intermediate stages in the manufacture of a package assembly 1300 in accordance with some embodiments. In fig. 19, an interposer wafer 100 is obtained or formed. The interposer wafer 100 may be formed as described above with reference to fig. 3 and will not be repeated here. Interposer wafer 100 includes a plurality of package regions (e.g., package regions 100A and 100B) that are to be singulated for inclusion in package assembly 1300 in subsequent processing. Interposer wafer 100 includes interposer 200 in each package region (e.g., package regions 100A and 100B).

The back side 50BS of the integrated circuit die 50 (e.g., the first integrated circuit die 50A and the second integrated circuit die 50B) is attached to the front side 100F of the interposer wafer 100 in each package region. In the illustrated embodiment, two integrated circuit dies 50 are attached in each package area. In other embodiments, one or more integrated circuit die 50 are attached in each package region of the interposer wafer 100 based on the design requirements of the package assembly 1300. In some embodiments, the first integrated circuit die 50A is a logic device, such as a CPU, GPU, etc., and the second integrated circuit die 50B is a memory device, such as a DRAM die, HMC module, HBM module, etc. In some embodiments, the first integrated circuit die 50A is the same type of device (e.g., soC) as the second integrated circuit die 50B.

In some embodiments, the integrated circuit die 50 is attached to the interposer wafer 100 by a bonding process (e.g., a hybrid bonding process). In such an embodiment, the integrated circuit die 50 is bonded to the interposer wafer 100 by fusion bonding the dielectric layer 66 at the back side 50BS of the integrated circuit die 50 to the dielectric layer 108 at the front side 100F of the interposer wafer 100, and by fusion bonding the die connectors 62 at the back side 50BS of the integrated circuit die 50 to the die connectors 110 at the front side 100F of the interposer wafer 100. In some embodiments, prior to the bonding process, the bonding surfaces of interposer wafer 100 (e.g., the bonding surfaces of dielectric layer 108 and die connectors 110) and the bonding surfaces of integrated circuit die 50 (e.g., the bonding surfaces of dielectric layer 66 and die connectors 62) are cleaned and then activated using a plasma process (e.g., such as an Ar plasma process). Subsequently, an annealing process may be performed to improve the bond between the interposer wafer 100 and the integrated circuit die 50. The interposer wafer 100 and the integrated circuit die 50 are electrically coupled by bonding structures formed by fusion bonding the die connectors 110 of the interposer wafer 100 to the die connectors 62 of the integrated circuit die 50.

In fig. 20, an encapsulant 1302 is formed over and around the integrated circuit die 50. After formation, an encapsulant 1302 encapsulates the integrated circuit die 50. The sealant 1302 may be formed using similar materials and methods as the sealant 702 described above with reference to fig. 13, and will not be repeated here. The encapsulant 1302 may be thinned to expose the integrated circuit die 50. The thinning process may be a grinding process, CMP, etch back, combinations thereof, or the like. In some embodiments, the thinning process also removes carrier 60 of integrated circuit die 50. After the thinning process, the top surfaces of the encapsulant 1302 and the front-side interconnect structure 56 of the integrated circuit die 50 are coplanar (within process variations) so that they are flush with each other.

In fig. 21, an interposer wafer 1200 is attached to an integrated circuit die 50. Interposer wafer 1200 may include a plurality of die level intermediaries 1250 such that die level intermediaries 1250 correspond to respective package regions of interposer wafer 100. Interposer wafer 1200 may be similar to interposer wafer 100 (see fig. 4), with like components being denoted by like reference numerals, and description of like components is not repeated here. The interposer wafer 1200 may be formed using similar process steps as described above with reference to fig. 3 and 4, except that the formation of the conductive vias 106, dielectric layer 112, and die connectors 114 is omitted. In some embodiments, interposer 1250 may be an active interposer (e.g., including active electrical devices such as SRAM devices), a passive interposer (e.g., including passive electrical devices such as capacitors), an I/O interposer (including I/O circuitry), an optical or photonic interposer (e.g., including optical devices such as modulators and/or waveguides), a hybrid (electrical/optical) interposer (including electrical and optical devices), and the like.

In some embodiments, die connectors 1304 are formed in an uppermost dielectric layer of front side interconnect structures 56 of integrated circuit die 50 (e.g., a dielectric layer of front side interconnect structures 56 furthest from a substrate of a respective integrated circuit die 50) prior to attaching interposer wafer 1200 to integrated circuit die 50. In some embodiments, die connectors 1304 may be formed using materials and methods similar to die connectors 62 described above with reference to fig. 2, and will not be repeated here. In some embodiments, the interposer wafer 1200 is attached to the integrated circuit die 50 by a bonding process (e.g., a hybrid bonding process). In such an embodiment, interposer wafer 1200 is bonded to integrated circuit die 50 by fusion bonding dielectric layer 108 of interposer wafer 1200 to the uppermost dielectric layer of front side interconnect structure 56 of integrated circuit die 50, and by fusion bonding die connectors 110 of interposer wafer 1200 to die connectors 1304 of integrated circuit die 50. In some embodiments, prior to the bonding process, the bonding surfaces of interposer wafer 1200 (e.g., the bonding surfaces of dielectric layer 108 and die connectors 110 of interposer wafer 1200) and the bonding surfaces of integrated circuit die 50 (e.g., the bonding surfaces of the uppermost dielectric layer of front side interconnect structure 56 of integrated circuit die 50 and the bonding surfaces of die connectors 1304 of integrated circuit die 50) are cleaned and then activated using a plasma process (e.g., such as an Ar plasma process). Subsequently, an annealing process may be performed to improve the bond between the interposer wafer 1200 and the integrated circuit die 50. The interposer wafer 1200 and the integrated circuit die 50 are electrically coupled by bonding structures formed by fusion bonding the die connectors 110 of the interposer wafer 1200 to the die connectors 1304 of the integrated circuit die 50.

In fig. 22, the backside 100BS of the interposer wafer 100 is thinned to expose the conductive vias 106. The exposure of the conductive vias 106 may be achieved by performing a thinning process (e.g., a grinding process, CMP, etch back, combinations thereof, etc.) on the substrate 102. In some embodiments (not separately shown), the thinning process for exposing the conductive vias 106 includes CMP, and the conductive vias 106 protrude at the backside 100BS of the wafer 100 due to dishing that occurs during CMP. In such an embodiment, an insulating layer (not separately shown) may optionally be formed on the back surface of the substrate 102 so as to surround the protruding portion of the conductive via 106. The insulating layer may be formed of a silicon-containing insulator such as silicon nitride, silicon oxide, silicon oxynitride, or the like, and may be formed by a suitable deposition method such as spin coating, CVD, PECVD, HDP-CVD, or the like. After thinning the substrate 102, the conductive vias 106 and the insulating layer (if present) or exposed surface of the substrate 102 are coplanar (within process variations) such that they are flush with each other and exposed at the backside 100BS of the interposer wafer 100.

After thinning the interposer wafer 100, a dielectric layer 112 and die connectors 114 are formed at the backside 100BS of the interposer wafer 100. In some embodiments, the dielectric layer 112 and the die connectors 114 are formed as described above with reference to fig. 4, and will not be repeated here. Conductive connections 1306 are then formed on the die connections 114 of the interposer wafer 100. The conductive connections 1306 may be Ball Grid Array (BGA) connections, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connection 1306 may be formed using similar materials and methods as the conductive connection 708 described above with reference to fig. 16, and will not be repeated here.

Further, singulation processes are performed on the resulting wafer level structure by dicing along scribe line regions (e.g., around the package regions 100A and 100B). Singulation processes may include sawing, etching, cutting, combinations thereof, and the like. For example, singulation processes may include dicing the encapsulant 1302, the interconnect structures 104 and the substrate 102 of the interposer wafer 100, and the interconnect structures 104 and the substrate 102 of the interposer wafer 1200. The singulation process singulates package regions (e.g., package region 100A) from adjacent package regions (e.g., package region 100B) to form singulated package assemblies 1300. Such a package assembly 1300 is shown in fig. 23. The singulation process further forms interposer 200 from the singulated portions of interposer wafer 100 and interposer 1250 from the singulated portions of interposer wafer 1200. As a result of the singulation process, the outer sidewalls of interposer 200, interposer 1250, and encapsulant 1302 are laterally co-bounded (within process variations), as shown in fig. 23.

Fig. 24 illustrates a cross-sectional view of a package assembly 1500 according to some embodiments. Package assembly 1500 is similar to package assembly 1300 (see fig. 23), wherein like components are denoted by like reference numerals and description of like components is not repeated here. In contrast to package assembly 1300, package assembly 1500 includes interposer 1400 instead of interposer 1250. Interposer 1400 is similar to interposer 1250, wherein like components are denoted by like reference numerals and description of like components is not repeated here. In contrast to interposer 1250, interposer 1400 includes conductive vias 106, dielectric layer 112, and die connectors 114. The conductive vias 106, dielectric layer 112, and die connectors 114 may be formed as described above with reference to fig. 4, and will not be repeated here.

Fig. 25-30 illustrate cross-sectional views at intermediate stages in the manufacture of a package assembly 1700 in accordance with some embodiments. In fig. 25, a carrier wafer 700 is provided or formed. The carrier wafer 700 serves as a platform or support for the packaging process described below. In some embodiments, the carrier wafer 700 includes a semiconductor material (e.g., silicon, etc.), a dielectric material (e.g., quartz, etc.), combinations thereof, and the like. As described in more detail below, wafer level package assemblies are formed over a carrier wafer, which are singulated into individual die level package assemblies 1700 in subsequent processing. In particular, carrier wafer 700 includes a plurality of package regions (e.g., package regions 700A and 700B) that correspond to respective die-level package assemblies 1700.

The interposer 200 (see fig. 3) is attached to a carrier wafer 700. In the illustrated embodiment, one interposer 200 is attached in each package region (e.g., package region 700A or 700B) of carrier wafer 700. In other embodiments, two or more interposers 200 may be attached in each package region of the carrier wafer 700 based on the design requirements of the package assembly 1700. Interposer 200 may be an active interposer (e.g., including active electrical devices such as SRAM devices), a passive interposer (e.g., including passive electrical devices such as capacitors), an I/O interposer (including I/O circuitry), or the like. In some embodiments, the interposer 200 is attached to the carrier wafer 700 using a bonding method as described above with reference to fig. 13, and will not be repeated here.

After attaching the interposer 200 to the carrier wafer 700, an encapsulant 702 is formed over and around the interposer 200 as described above with reference to fig. 13, and will not be repeated here. The encapsulant 702 may be thinned to expose the dielectric layer 112 and die connectors 114 at the back side 200B of the interposer 200. The thinning process may be a grinding process, CMP, etch back, combinations thereof, or the like. After the thinning process, the top surfaces of dielectric layer 112, die attach 114, and encapsulant 702 are coplanar (within process variations) so that they are flush with one another.

After the encapsulant 702 is formed, the integrated circuit die 50 (e.g., the first integrated circuit die 50A and the second integrated circuit die 50B) are attached to each interposer 200. In the illustrated embodiment, two integrated circuit dies 50 are attached to each interposer 200. In other embodiments, one or more integrated circuit die 50 may be attached to each interposer 200 based on the design requirements of the package assembly 1700. In some embodiments, the first integrated circuit die 50A is a logic device, such as a CPU, GPU, etc., and the second integrated circuit die 50B is a memory device, such as a DRAM die, HMC module, HBM module, etc. In some embodiments, the first integrated circuit die 50A is the same type of device (e.g., soC) as the second integrated circuit die 50B. In some embodiments, the integrated circuit die 50 is attached to the corresponding interposer 200 by a bonding process as described above with reference to fig. 13, and will not be repeated here.

In fig. 26, an encapsulant 704 is formed over and around the integrated circuit die 50 as described above with reference to fig. 14, and will not be repeated here. After formation, an encapsulant 704 encapsulates the integrated circuit die 50. The encapsulant 704 may be thinned to expose the integrated circuit die 50. The thinning process may be a grinding process, CMP, etch back, combinations thereof, or the like. In some embodiments, the thinning process also removes carrier 60 of integrated circuit die 50. After the thinning process, the encapsulant 704 and the top surface of the front-side interconnect structure 56 of the integrated circuit die 50 are coplanar (within process variations) so that they are flush with each other. In some embodiments, the encapsulant 702 and the encapsulant 704 comprise the same material and the interface between the encapsulant 702 and the encapsulant 704 may be undetectable. In other embodiments, encapsulant 702 and encapsulant 704 comprise different materials.

In fig. 27 and 28, an interposer wafer 1600 is formed over the integrated circuit die 50 and the encapsulant 704. Interposer wafer 1600 may include a plurality of die level intermediaries 1650 such that die level intermediaries 1650 correspond to respective package regions of carrier wafer 700. In some embodiments, interposer 1650 may be an active interposer (e.g., including active electrical devices such as SRAM devices), a passive interposer (e.g., including passive electrical devices such as capacitors), an I/O interposer (including I/O circuitry), an optical or photonic interposer (e.g., including optical devices such as modulators and/or waveguides), a hybrid (electrical/optical) interposer (including electrical and optical devices), and the like.

In fig. 27, interconnect structures 1602 of interposer wafer 1600 are formed over integrated circuit die 50 and encapsulant 704. Interconnect structure 1602 may include one or more dielectric layers 1602A and corresponding metallization layers 1602B (including conductive lines and vias) located in dielectric layers 1602A. Acceptable dielectric materials for dielectric layer 1602A include low-k dielectric materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped Silicate Glass (USG), and the like. Acceptable dielectric materials for dielectric layer 1602A also include oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; etc.; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, and the like. Other dielectric materials may also be used, such as polymers, e.g., polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB) based polymers, and the like. The metallization layer 1602B may be formed of a conductive material, such as a metal, e.g., copper, cobalt, aluminum, gold, combinations thereof, and the like. Interconnect structure 1602 may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like.

In fig. 28, a semiconductor substrate 1604 of an interposer wafer 1600 is attached to an interconnect structure 1602 of the interposer wafer 1600. The semiconductor substrate 1604 may be formed using materials and methods similar to those described above with reference to the semiconductor substrate 52 of fig. 1, and will not be repeated here.

In the illustrated embodiment, the semiconductor substrate 1604 is attached to the interconnect structure 1602 by a bonding method (e.g., a fusion bonding method). In some embodiments, a dielectric layer 1606 is formed on the semiconductor substrate 1604 prior to bonding the semiconductor substrate 1604 to the interconnect structure 1602. Subsequently, semiconductor substrate 1604 is bonded to interconnect structure 1602 by fusion bonding dielectric layer 1606 to the uppermost dielectric layer of interconnect structure 1602 (e.g., the dielectric layer of interconnect structure 1602 closest to semiconductor substrate 1604). In some embodiments, prior to the bonding process, the bonding surfaces of the semiconductor substrate 1604 (e.g., the bonding surfaces of the dielectric layer 1606) and the bonding surfaces of the interconnect structure 1602 (e.g., the bonding surfaces of the uppermost dielectric layer of the interconnect structure 1602)) are cleaned and then activated using a plasma process (e.g., such as an Ar plasma process). Subsequently, an annealing process may be performed to improve the bond between the interconnect structure 1602 and the semiconductor substrate 1604.

In fig. 29, after an interposer wafer 1600 is formed over the integrated circuit die 50 and encapsulant 704, the carrier wafer 700 is separated from the interposer 200. Subsequently, as described above with reference to fig. 16, the conductive connection 708 is formed on the die connection 110 of the interposer 200, and a description thereof will not be repeated here.

Further, singulation processes are performed on the resulting wafer level structure by dicing along scribe line regions (e.g., around the package regions 700A and 700B). Singulation processes may include sawing, etching, cutting, combinations thereof, and the like. For example, singulation process may include sawing the encapsulants 702 and 704, as well as the interconnect structure 1602 and the substrate 1604 of the interposer wafer 1600. The singulation process singulates package regions (e.g., package region 700A) from adjacent package regions (e.g., package region 700B) to form singulated package assemblies 1700. Such a package assembly 1700 is shown in fig. 30. The singulation process further forms the interposer 1650 from the singulated portions of the interposer wafer 1600. As a result of the singulation process, the outer sidewalls of the interposer 1650, interposer 200, and encapsulant 704 are laterally co-bounded (within process variations), as shown in fig. 30.

Fig. 31 illustrates a cross-sectional view of a package assembly 1800 according to some embodiments. Package assembly 1800 is similar to package assembly 900 (see fig. 17), wherein like components are denoted by like reference numerals and the description of like components is not repeated here. In contrast to package assembly 900, package assembly 1800 includes interposer 300' (see fig. 6) instead of interposer 850 (see fig. 17). The integrated circuit dies 50A and 50B are electrically coupled through the interposer 300', such as through the interconnect structure 104 and/or passive electrical devices (not shown) of the interposer 300'. The integrated circuit dies 50A and 50B are further electrically coupled through the interposer 200, such as through conductive vias 106, interconnect structures 104, and/or active/passive electrical devices (not shown) of the interposer 200.

Fig. 32A and 32B illustrate plan and cross-sectional views of the interconnect structure 104 of the interposer 300' of the package assembly 1800 (see fig. 31) according to some embodiments. In particular, fig. 32A shows a plan view, and fig. 32B shows a sectional view along a line BB' in fig. 32A. In the illustrated embodiment, package assembly 1800 includes four integrated circuit dies 50 (e.g., integrated circuit dies 50A, 50B, 50C, and 50D) interconnected by interconnect structures 104 of interposer 300'. In some embodiments, the interconnect structure 104 of the interposer 300' includes a metallization layer 104B, and the metallization layer 104B may include wires 104B1, 104B2, 104B3, and 104B4. The conductive lines 104B1, 104B2, 104B3, and 104B4 are disposed in different metallization layers of the interconnect structure 104 such that the conductive line 104B3 is located above the conductive line 104B4, the conductive line 104B2 is located above the conductive line 104B3, and the conductive line 104B1 is located above the conductive line 104B 2. Wires 104B1, 104B2, 104B3, and 104B4 interconnect die connectors 706 of integrated circuit die 50, thereby electrically connecting integrated circuit die 50 to one another. Wire 104B1 interconnects die connectors 706 of integrated circuit dies 50A and 50B to die connectors 706 of integrated circuit dies 50C and 50D, respectively, along the shortest direct path between connected die connectors 706. Wire 104B2 interconnects die connectors 706 of integrated circuit dies 50A and 50C to die connectors 706 of integrated circuit dies 50B and 50D, respectively, along the shortest direct path between connected die connectors 706. Wire 104B3 interconnects die connection 706 of integrated circuit die 50A to die connection 706 of integrated circuit die 50D along the shortest direct path between connected die connections 706. Wires 104B4 interconnect die connectors 706 of integrated circuit die 50B to die connectors 706 of integrated circuit die 50C along the shortest direct path between connected die connectors 706.

Fig. 33A and 33B illustrate plan and cross-sectional views of the interconnect structure 104 of the interposer 300' of the package assembly 1800 (see fig. 31) according to some embodiments. In particular, fig. 33A shows a plan view, and fig. 33B shows a sectional view along a line BB' in fig. 33A. In the illustrated embodiment, package assembly 1800 includes four integrated circuit dies 50 (e.g., integrated circuit dies 50A, 50B, 50C, and 50D) interconnected by interconnect structures 104 of interposer 300'. In some embodiments, the interconnect structure 104 of the interposer 300' includes a metallization layer 104B, which metallization layer 104B may include wires 104B1 and 104B2. Wires 104B1 and 104B2 are disposed in different metallization layers of interconnect structure 104 such that wire 104B1 is located above wire 104B2. Wires 104B1 and 104B2 interconnect die connectors 706 of integrated circuit die 50, thereby electrically connecting integrated circuit die 50 to one another. Wire 104B1 interconnects die connectors 706 of integrated circuit dies 50A and 50B to die connectors 706 of integrated circuit dies 50C and 50D, respectively, along the shortest direct path between connected die connectors 706. Wire 104B2 interconnects die connectors 706 of integrated circuit dies 50A and 50C to die connectors 706 of integrated circuit dies 50B and 50D, respectively, along the shortest direct path between connected die connectors 706.

Fig. 34 illustrates a cross-sectional view of a package assembly 1900 according to some embodiments. Package assembly 1900 is similar to package assembly 900 (see fig. 17), wherein like components are denoted by like reference numerals, and a description of like components is not repeated herein. In contrast to package assembly 900, package assembly 1900 includes interposer 300 (see fig. 5) instead of interposer 850 (see fig. 17). The integrated circuit dies 50A and 50B are electrically coupled through the interposer 300, such as through the interconnect structure 104 and/or passive electrical devices (not shown) of the interposer 300. The integrated circuit dies 50A and 50B are further electrically coupled through the interposer 200, such as through conductive vias 106, interconnect structures 104, and/or active/passive electrical devices (not shown) of the interposer 200.

Fig. 35 illustrates a cross-sectional view of a package assembly 2000, according to some embodiments. The package assembly 2000 is similar to the package assembly 900 (see fig. 17), wherein like components are denoted by like reference numerals, and the description of like components is not repeated herein. In contrast to package assembly 900, package assembly 2000 includes interposer 400' (see fig. 8) instead of interposer 850 (see fig. 17). The integrated circuit dies 50A and 50B are electrically coupled through the interposer 400', such as through the interconnect structure 104 and/or the active/passive electrical devices 402 of the interposer 400'. The integrated circuit dies 50A and 50B are further electrically coupled through the interposer 200, such as through conductive vias 106, interconnect structures 104, and/or active/passive electrical devices (not shown) of the interposer 200.

Fig. 36 illustrates a plan view of the interconnect structure 104 of the interposer 400' of the package assembly 2000, in accordance with some embodiments. In the illustrated embodiment, the package assembly 2000 includes four integrated circuit dies 50 (e.g., integrated circuit dies 50A, 50B, 50C, and 50D) interconnected by an interconnect structure 104 of an interposer 400'. In some embodiments, die connectors 706 of integrated circuit die 50 are coupled to I/O router/switch 404. In some embodiments, the I/O router/switch 404 may be formed by the device 402 (see fig. 35) of the interposer 400'. Interconnect structure 104 of interposer 400' includes metallization layer 104B, which metallization layer 104B may include conductive lines 104B1 and 104B2. In some embodiments, the conductive lines 104B1 and 104B2 are disposed in different metallization layers of the interconnect structure 104 such that the conductive line 104B2 is located above the conductive line 104B 1. Conductor 104B1 interconnects I/O router/switch 404 of integrated circuit dies 50A and 50B to I/O router/switch 404 of integrated circuit dies 50C and 50D, respectively, along the shortest direct path between the connected I/O routers/switches. Wire 104B2 interconnects adjacent I/O routers/switches 404 within each integrated circuit die 50A, 50B, 50C, and 50D along the shortest direct path between the connected I/O routers/switches. Conductor 104B2 further interconnects I/O router/switch 404 of integrated circuit die 50A to I/O router/switch 404 of integrated circuit die 50B and I/O router/switch 404 of integrated circuit die 50C to I/O router/switch 404 of integrated circuit die 50D along the shortest direct path between the connected I/O routers/switches.

Fig. 37 illustrates a cross-sectional view of a package assembly 2100, according to some embodiments. Package assembly 2100 is similar to package assembly 900 (see fig. 17), wherein like components are denoted by like reference numerals and description of like components is not repeated here. In contrast to package assembly 900, package assembly 2100 includes interposer 400 (see fig. 7) instead of interposer 850 (see fig. 17). The integrated circuit dies 50A and 50B are electrically coupled through the interposer 400, such as through the interconnect structure 104 and/or the active/passive electrical devices 402 of the interposer 400. The integrated circuit dies 50A and 50B are further electrically coupled through the interposer 200, such as through interposer 200 conductive vias 106, interconnect structures 104, and/or active/passive electrical devices (not shown).

Fig. 38 illustrates a cross-sectional view of a package assembly 2200 in accordance with some embodiments. Package assembly 2200 is similar to package assembly 900 (see fig. 17), wherein like components are denoted by like reference numerals and description of like components is not repeated here. In contrast to package assembly 900, package assembly 2200 includes interposer 500' (see fig. 10) instead of interposer 850 (see fig. 17). Integrated circuit dies 50A and 50B are electrically coupled through interposer 500', such as through interconnect structure 104, one or more optical waveguides 504, and/or optical device 502 of interposer 500'. The integrated circuit dies 50A and 50B are further electrically coupled through the interposer 200, such as through conductive vias 106, interconnect structures 104, and/or active/passive electrical devices (not shown) of the interposer 200.

Fig. 39 illustrates a cross-sectional view of a package assembly 2300 according to some embodiments. The package assembly 2300 is similar to the package assembly 900 (see fig. 17), wherein like parts are denoted by like reference numerals, and descriptions of like parts are not repeated herein. In contrast to package assembly 900, package assembly 2300 includes interposer 500 (see fig. 9) instead of interposer 850 (see fig. 17). Integrated circuit dies 50A and 50B are electrically coupled through interposer 500, such as through interconnect structure 104, one or more optical waveguides 504, and/or optical device 502 of interposer 500. The integrated circuit dies 50A and 50B are further electrically coupled through the interposer 200, such as through conductive vias 106, interconnect structures 104, and/or active/passive electrical devices (not shown) of the interposer 200.

Fig. 40 illustrates a cross-sectional view of a package assembly 2400 in accordance with some embodiments. The package assembly 2400 is similar to the package assembly 900 (see fig. 17), wherein like components are denoted by like reference numerals and the description of like components is not repeated here. In contrast to the package assembly 900, the package assembly 2400 includes an interposer 600' (see fig. 12) instead of the interposer 850 (see fig. 17). Integrated circuit dies 50A and 50B are electrically coupled through interposer 600', such as through interconnect structure 104 of interposer 600', one or more optical waveguides 602, optical devices (not shown), and/or active/passive electrical devices (not shown). The integrated circuit dies 50A and 50B are further electrically coupled through the interposer 200, such as through conductive vias 106, interconnect structures 104, and/or active/passive electrical devices (not shown) of the interposer 200.

Fig. 41 illustrates a cross-sectional view of a package assembly 2500 in accordance with some embodiments. Package assembly 2500 is similar to package assembly 900 (see fig. 17), wherein like components are denoted by like reference numerals and a description of like components is not repeated herein. In contrast to package assembly 900, package assembly 2500 includes interposer 600 (see fig. 11) instead of interposer 850 (see fig. 17). Integrated circuit dies 50A and 50B are electrically coupled through interposer 600, such as through interconnect structure 104 of interposer 600, one or more optical waveguides 602, optical devices (not shown), and/or active/passive electrical devices (not shown). The integrated circuit dies 50A and 50B are further electrically coupled through the interposer 200, such as through conductive vias 106, interconnect structures 104, and/or active/passive electrical devices (not shown) of the interposer 200.

Fig. 42 illustrates a cross-sectional view of a package assembly 2600, according to some embodiments. The package assembly 2600 is similar to the package assembly 900 (see fig. 17), wherein like components are denoted by like reference numerals and the description of like components is not repeated here. In contrast to package assembly 900, package assembly 2600 includes two intermediaries 200 instead of a single interposer (see fig. 17) such that integrated circuit die 50A is bonded to a first one of intermediaries 200 and integrated circuit die 50B is bonded to a second one of intermediaries 200, wherein the first one of intermediaries 200 is laterally separated from the second one of intermediaries 200 by encapsulant 702. The integrated circuit dies 50A and 50B are electrically coupled through the interposer 850, such as through the interconnect structure 104 of the interposer 850, optical devices (not shown), active electrical devices (not shown), and/or passive electrical devices (not shown).

Fig. 43 illustrates a cross-sectional view of a package assembly 2700 according to some embodiments. The package assembly 2700 is similar to the package assembly 1100 (see fig. 18), wherein like components are denoted by like reference numerals and the description of like components is not repeated here. In contrast to package assembly 1100, package assembly 2700 includes two intermediaries 200 instead of a single interposer (see fig. 18) such that integrated circuit die 50A is bonded to a first one of intermediaries 200 and integrated circuit die 50B is bonded to a second one of intermediaries 200, wherein the first one of intermediaries 200 is laterally separated from the second one of intermediaries 200 by encapsulant 702. Integrated circuit dies 50A and 50B are electrically coupled through interposer 1000, such as through interconnect structures 104 of interposer 1000, optical devices (not shown), active electrical devices (not shown), and/or passive electrical devices (not shown).

Fig. 44 illustrates a cross-sectional view of a package assembly 2800 in accordance with some embodiments. Package assembly 2800 is similar to package assembly 900 (see fig. 17), wherein like components are denoted by like reference numerals and descriptions of like components are not repeated herein. In contrast to package assembly 900, package element 2800 does not include interposer 200 (see fig. 17) such that conductive connections 708 are formed on die connections 62 of integrated circuit dies 50A and 50B. The integrated circuit dies 50A and 50B are electrically coupled through the interposer 850, such as through the interconnect structure 104 of the interposer 850, optical devices (not shown), active electrical devices (not shown), and/or passive electrical devices (not shown).

Fig. 45 illustrates a cross-sectional view of a package assembly 2900 according to some embodiments. Package assembly 2900 is similar to package assembly 1100 (see fig. 18), wherein like components are denoted by like reference numerals and description of like components is not repeated herein. In contrast to package element 1100, package assembly 2900 does not include interposer 200 (see fig. 18) such that conductive connections 708 are formed on die connections 62 of integrated circuit dies 50A and 50B. Integrated circuit dies 50A and 50B are electrically coupled through interposer 1000, such as through interconnect structures 104 of interposer 1000, optical devices (not shown), active electrical devices (not shown), and/or passive electrical devices (not shown).

Fig. 46 illustrates a cross-sectional view of a package assembly 3000 according to some embodiments. Package assembly 3000 is similar to package assembly 900 (see fig. 17), wherein like components are denoted by like reference numerals, and description of like components is not repeated here. In contrast to package assembly 900, package assembly 3000 includes an integrated circuit die 50' instead of integrated circuit die 50 (see fig. 17). The integrated circuit die 50' is electrically coupled through the interposer 850, such as through the interconnect structure 104 of the interposer 850, optical devices (not shown), active electrical devices (not shown), and/or passive electrical devices (not shown). The integrated circuit die 50' is further electrically coupled through the interposer 200, such as through conductive vias 106, interconnect structures 104, and/or active/passive electrical devices (not shown) of the interposer 200.

Fig. 47 illustrates a cross-sectional view of a package assembly 3100 according to some embodiments. Package assembly 3100 is similar to package assembly 1100 (see fig. 18), wherein like components are denoted by like reference numerals and description of like components is not repeated here. In contrast to package assembly 1100, package assembly 3100 includes integrated circuit die 50' instead of integrated circuit die 50 (see fig. 18). The integrated circuit die 50' is electrically coupled through the interposer 1000, such as through the interconnect structure 104 of the interposer 1000, optical devices (not shown), active electrical devices (not shown), and/or passive electrical devices (not shown). The integrated circuit die 50' is further electrically coupled through the interposer 200, such as through conductive vias 106, interconnect structures 104, and/or active/passive electrical devices (not shown) of the interposer 200.

Fig. 48 illustrates a cross-sectional view of a packaged assembly 3200 according to some embodiments. Package assembly 3200 is similar to package assembly 3000 (see fig. 46), wherein like components are denoted by like reference numerals and description of like components is not repeated here. In contrast to package assembly 3000, package assembly 3200 does not include interposer 200 (see fig. 46) such that conductive connections 708 are formed on die connections 62 of integrated circuit die 50'. The integrated circuit die 50' is electrically coupled through the interposer 850, such as through the interconnect structure 104 of the interposer 850, optical devices (not shown), active electrical devices (not shown), and/or passive electrical devices (not shown).

Fig. 49 illustrates a cross-sectional view of a package assembly 3300, according to some embodiments. Package assembly 3300 is similar to package assembly 3100 (see fig. 47), wherein like components are denoted by like reference numerals and description of like components is not repeated here. In contrast to package assembly 3100, package assembly 3300 does not include interposer 200 (see fig. 47) such that conductive connections 708 are formed on die connections 62 of integrated circuit die 50'. The integrated circuit die 50' is electrically coupled through the interposer 1000, such as through the interconnect structure 104 of the interposer 1000, optical devices (not shown), active electrical devices (not shown), and/or passive electrical devices (not shown).

Fig. 50 illustrates a cross-sectional view of a multi-layer package assembly 3400, according to some embodiments. The multi-layer package assembly 3400 includes a package assembly 3402 attached thereto ₁ Is 3402 of the package assembly ₂ . Packaging assembly 3402 ₁ Similar to package assembly 1900 (see FIG. 34), its classLike parts are denoted by like reference numerals, and description of like parts is not repeated here. In some embodiments, the package assembly 3402 may be formed using similar process steps as described above with reference to fig. 13-16 ₁ And will not be repeated here. Unlike package assembly 1900 (see fig. 34), package assembly 3402 ₁ Including a through hole 3404 extending through the encapsulant 704 ₁ . The through hole 3404 may be formed ₁ Referred to as molded through-holes, encapsulant through-holes, or chip through-holes. In some embodiments, after attaching the interposer 200 to the carrier wafer 700 as described above with reference to fig. 13, a seed layer (e.g., such as a copper layer) is formed over the interposer 200, photoresist is formed on the seed layer, and the photoresist is patterned to form a via 3404 ₁ Is provided. Subsequently, a conductive material (e.g., such as copper) is formed in the openings, for example, using a plating process. After the conductive material is formed, the photoresist is removed, and after the photoresist is removed, the exposed portions of the seed layer are removed. The conductive material and the remainder of the seed layer form a through hole 3404 ₁ . Through hole 3404 ₁ The package assembly 3402 ₁ Is electrically coupled to the package 3402 ₁ Is provided for the interposer 300.

Packaging assembly 3402 ₂ Similar to the package assembly 1800 (see fig. 31), wherein like components are denoted by like reference numerals and description of like components is not repeated here. In some embodiments, the package assembly 3402 may be formed using similar process steps as described above with reference to fig. 13-16 ₂ And will not be repeated here. Unlike package assembly 1800 (see fig. 31), package assembly 3402 ₂ Including a through hole 3404 extending through the encapsulant 704 ₂ . The through hole 3404 may be formed ₂ Referred to as molded through-holes, encapsulant through-holes, or chip through-holes. Through holes 3404 can be used ₁ Similar materials and methods to form via 3404 ₂ . Through hole 3404 ₂ The package assembly 3402 ₂ Is electrically coupled to the package 3402 ₂ Is provided for the interposer 300'.

In some embodiments, the package assembly 3402 is packaged using a bonding process (such as a hybrid bonding process) ₂ Attached to package assembly 3402 ₁ . In such an embodiment, package assembly 3402 ₂ Is fusion bonded to package assembly 3402 ₁ And package assembly 3402 ₂ Is fusion bonded to the package assembly 3402 ₁ Is provided for the die attach 114. In some embodiments, prior to the bonding process, the bonding surfaces of dielectric layers 108 and 112 and die connectors 110 and 114 are cleaned and then activated using a plasma process (e.g., such as an Ar plasma process). Subsequently, an annealing process may be performed to improve the package assembly 3402 ₁ And package assembly 3402 ₂ And the engagement therebetween. Packaging assembly 3402 ₁ And package assembly 3402 ₂ Is electrically coupled by a bonding structure that electrically couples the package assembly 3402 by ₂ Is fusion bonded to the package assembly 3402 ₁ Is formed of die attach 114.

In some embodiments, the interposer 300 'may be replaced by any of the interposer 400' (see fig. 8), 500 '(see fig. 10), and 600' (see fig. 12) based on the design requirements of the multi-layer package assembly 3400. In some embodiments, the interposer 300 may be replaced by any of the interposer 400 (see fig. 7), 500 (see fig. 9), and 600 (see fig. 11) based on the design requirements of the multi-layer package assembly 3400. In some embodiments, some or all of the integrated circuit die 50 may be replaced by an integrated circuit die 50' (see fig. 2) based on the design requirements of the multi-layer package assembly 3400. In the illustrated embodiment, the multi-layer package assembly 3400 includes two package assemblies (e.g., package assembly 3402 ₁ And 3402 ₂ ). In other embodiments, the multi-layer package assembly 3400 may include more than two package assemblies based on the design requirements of the multi-layer package assembly 3400.

Fig. 51 illustrates a cross-sectional view of a multi-layer package assembly 3500 in accordance with some embodiments. Multi-layer package assembly 3500 includes package assembly 3502 ₁ Packaging component 3502 ₂ And packaging assembly 3502 ₃ . Packaging assembly 3502 ₂ Attachment ofTo package assembly 3502 ₁ And encapsulates the component 3502 ₃ Attached to package assembly 3502 ₂ So that the package assembly 3502 ₂ Inserted into the package assembly 3502 ₁ And packaging assembly 3502 ₃ Between them.

Packaging assembly 3502 ₁ Similar to package assembly 1900 (see fig. 34), wherein like components are denoted by like reference numerals, and description of like components is not repeated herein. The package assembly 3502 may be formed using process steps similar to those described above with reference to fig. 13-16 ₁ And will not be repeated here. Unlike package assembly 1900 (see fig. 34), package assembly 3502 ₁ Including a through hole 3504 extending through the encapsulant 704 ₁ . The through hole 3504 may be formed ₁ Referred to as molded through-holes, encapsulant through-holes, or chip through-holes. In some embodiments, a through hole 3404 as described above with reference to fig. 50 may be used ₁ Similar materials and methods form through-holes 3504 ₁ And will not be repeated here. Through hole 3504 ₁ Packaging component 3502 ₁ Is electrically coupled to package assembly 3502 ₁ Is provided for the interposer 300.

Packaging assembly 3502 ₂ Similar to the package assembly 2500 (see fig. 41), wherein like components are denoted by like reference numerals, and description of like components is not repeated herein. In some embodiments, package assembly 3502 may be formed using similar process steps as described above with reference to fig. 13-16 ₂ And will not be repeated here. Unlike package assembly 2500 (see fig. 41), package assembly 3502 ₂ Including a through hole 3504 extending through the encapsulant 704 ₂ . The through hole 3504 may be formed ₂ Referred to as molded through-holes, encapsulant through-holes, or chip through-holes. In some embodiments, a through hole 3404 as described above with reference to fig. 50 may be used ₁ Similar materials and methods form through-holes 3504 ₂ And will not be repeated here. Through hole 3504 ₂ Packaging component 3502 ₂ Is electrically coupled to the package element 3502 ₂ Is provided for the interposer 600.

Packaging assembly 3502 ₃ Similar to the package assembly 2200 (see fig. 38), wherein like parts are denoted by like reference numerals, and description of like parts is not repeated herein. In some embodiments, package assembly 3502 may be formed using similar process steps as described above with reference to fig. 13-16 ₃ And will not be repeated here. Unlike package assembly 2200 (see fig. 38), package assembly 3502 ₃ Including a through hole 3504 extending through the encapsulant 704 ₃ . The through hole 3504 may be formed ₃ Referred to as molded through-holes, encapsulant through-holes, or chip through-holes. In some embodiments, a through hole 3404 as described above with reference to fig. 50 may be used ₁ Similar materials and methods form through-holes 3504 ₃ And will not be repeated here. Through hole 3504 ₃ Packaging component 3502 ₃ Is electrically coupled to the package element 3502 ₃ Is provided for the interposer 500'.

In some embodiments, the package assembly 3502 is packaged using a bonding process (such as a hybrid bonding process) ₁ Attached to package assembly 3502 ₂ . In such an embodiment, package assembly 3502 ₂ Is bonded to package assembly 3502 ₁ Such that package assembly 3502 ₂ Is fusion bonded to package assembly 3502 ₁ And causes the package assembly 3502 to ₂ Is fusion bonded to package assembly 3502 ₁ Is provided for the die attach 114. In some embodiments, prior to the bonding process, the bonding surfaces of dielectric layers 108 and 112 and die connectors 110 and 114 are cleaned and then activated using a plasma process (e.g., such as an Ar plasma process). Subsequently, an annealing process may be performed to improve the package assembly 3502 ₁ And packaging assembly 3502 ₂ And the engagement therebetween. Packaging assembly 3502 ₁ And packaging assembly 3502 ₂ Electrically coupled by a bonding structure that electrically couples the package assembly 3502 by ₂ Is fusion bonded to package assembly 3502 ₁ Is formed of die attach 114.

In some embodiments, the package assembly 3502 is packaged using a bonding process (such as a hybrid bonding process) ₃ Attached to package assembly 3502 ₂ . In such an embodiment, package assembly 3502 ₃ Is bonded to package assembly 3502 ₂ To enable packaging of component 3502 ₃ Is fusion bonded to package assembly 3502 ₂ And causes the package assembly 3502 to ₃ Is fusion bonded to package assembly 3502 ₂ Is provided for the die attach 114. In some embodiments, prior to the bonding process, the bonding surfaces of dielectric layers 108 and 112 and die connectors 110 and 114 are cleaned and then activated using a plasma process (e.g., such as an Ar plasma process). Subsequently, an annealing process may be performed to improve the package assembly 3502 ₂ And packaging assembly 3502 ₃ And the engagement therebetween. Packaging assembly 3502 ₂ And packaging assembly 3502 ₃ Electrically coupled by a bonding structure that electrically couples the package assembly 3502 by ₃ Is fusion bonded to package assembly 3502 ₂ Is formed of die attach 114.

In some embodiments, interposer 300 may be replaced by any of the package components of interposer 400 (see fig. 7), 500 (see fig. 9), and 600 (see fig. 11) based on the design requirements of multi-layer package component 3500. In some embodiments, interposer 600 may be replaced by any of the package components of interposers 300 (see fig. 5), 400 (see fig. 7), and 500 (see fig. 9) based on the design requirements of multi-layer package component 3500. In some embodiments, interposer 500 'may be replaced by any of the package components of interposer 300' (see fig. 6), 400 '(see fig. 8), and 600' (see fig. 12) based on the design requirements of multi-layer package component 3500. In some embodiments, some or all of integrated circuit die 50 may be replaced with integrated circuit die 50' (see fig. 2) based on the design requirements of multi-layer package assembly 3500. In the illustrated embodiment, multi-layer package assembly 3500 includes three package assemblies (e.g., package assembly 3502 ₁ 、3502 ₂ And 3502 ₃ ). In other embodiments, the number is based on the design requirements of the multi-layer package assembly 3500The layer package assembly 3500 may include more than three package assemblies.

In some embodiments, any of the package assemblies described above may be attached to a package substrate to form an integrated circuit package. Such an integrated circuit package 3700 is shown in fig. 52. In particular, fig. 52 illustrates a cross-sectional view of an integrated circuit package 3700 including a package assembly 900 (see fig. 17) mounted on a package substrate 3600, in accordance with some embodiments. The package assembly 900 may be mounted on a package substrate 3600 using conductive connections 708.

The package substrate 3600 includes a substrate core 3602 and bond pads 3604 located above the substrate core 3602. The substrate core 3602 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, and the like may also be used. Further, the substrate core 3602 may be an SOI substrate. Typically, the SOI substrate comprises a layer of semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In an alternative embodiment, the substrate core 3602 is based on an insulating core such as a fiberglass reinforced resin core. One example core material is fiberglass resin, such as FR4. Alternatives to the core material include a dual polymer imide-triazine BT resin, or alternatively, other PCB materials or films. Laminated films such as ABF or other laminates may be used for the substrate core 3602.

The substrate core 3602 may include active devices and passive devices (not shown). Various devices, such as transistors, capacitors, resistors, combinations thereof, and the like, may be used to create the structural and functional requirements of the design of the integrated circuit package 3700. The devices may be formed using any suitable method.

The substrate core 3602 may also include metallization layers and vias (not shown) to which the bond pads 3604 are physically and/or electrically coupled. A metallization layer may be formed over the active and passive devices and designed to connect the various devices to form functional circuits. The metallization layer may be formed of alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper), wherein the vias interconnect the layers of conductive material, and may be formed by any suitable process such as deposition, damascene, dual damascene, etc. In some embodiments, the substrate core 3602 is substantially free of active devices and passive devices.

In some embodiments, the conductive connection 708 is reflowed to attach the package assembly 900 to the bond pad 3604. The conductive connections 708 electrically and/or physically couple the package substrate 3600 (including the metallization layer in the substrate core 3602) to the package assembly 900. In some embodiments, a solder resist 3606 is formed on the package substrate 3600. The conductive connection 708 may be disposed in an opening in the solder resist 3606 to couple and mechanically couple to the bond pad 3604. The solder resist 3606 may be used to protect the area of the package substrate 3600 from external damage.

The conductive connection 708 may have an epoxy flux (not shown) formed thereon prior to reflowing the conductive connection 708, at least some of the epoxy portion of the epoxy flux remaining after the package assembly 900 is attached to the package substrate 3600. The remaining epoxy portion may act as an underfill to reduce stress and protect the joint created by reflowing the conductive connection 708. In some embodiments, an underfill 3608 may be formed between the package assembly 900 and the package substrate 3600 and around the conductive connections 708. The underfill 3608 may be formed from a molding compound, an epoxy, or the like. The underfill 3608 may be formed by a capillary process after the package assembly 900 is attached to the package substrate 3600, or the underfill 3608 may be formed by a suitable deposition method before the package assembly 900 is attached to the package substrate 3600.

Other components and processes may also be included. For example, test structures may be included to facilitate verification testing of 3D packages or 3DIC devices. For example, the test structures may include test pads formed in the redistribution layer or on the substrate, the test pads allowing for testing of 3D packages or 3DIC, use of probes and/or probe cards, and the like. Verification tests may be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein may be used in conjunction with test methods that incorporate intermediate verification of known good die to increase yield and reduce cost.

Embodiments may realize advantages. The various embodiments described above allow for the formation of a package assembly (e.g., such as package assembly 900 shown in fig. 17) including a plurality of integrated circuit dies (e.g., such as integrated circuit dies 50A and 50B shown in fig. 17) encapsulated in an encapsulant (e.g., such as encapsulant 704 shown in fig. 17), wherein each integrated circuit die includes a front-side interconnect structure (e.g., such as front-side interconnect structure 56 shown in fig. 1) and a back-side interconnect structure (e.g., such as back-side interconnect structure 58 shown in fig. 1). The package assembly also includes a first interposer (e.g., such as interposer 200 shown in fig. 17) in physical and electrical contact with the backside interconnect structure of the integrated circuit die and a second interposer (e.g., such as interposer 850 shown in fig. 17) in physical and electrical contact with the front side interconnect structure of the integrated circuit die. The second interposer allows coupling of the front-side interconnect structure of the integrated circuit die independent of the back-side interconnect structure of the integrated circuit die (e.g., the super power rail) and the interconnect structure and through vias of the first interposer. By hybrid bonding the first interposer and the second interposer to the integrated circuit die, the thermal resistance of the package assembly is reduced. By electrically coupling the integrated circuit die via the second interposer, flexibility in package assembly circuit design is improved.

According to an embodiment, a package includes an encapsulant having a first side and a second side opposite the first side, first and second integrated circuit dies embedded in the encapsulant, and a first interposer on the first side of the encapsulant. The first interposer is mechanically and electrically coupled to the first integrated circuit die and the second integrated circuit die. The package also includes a second interposer on a second side of the encapsulant. The second interposer is mechanically and electrically coupled to the first integrated circuit die and the second integrated circuit die. The second interposer optically or electrically couples the first integrated circuit die to the second integrated circuit die. In an embodiment, the first interposer includes an active electrical device or a passive electrical device. In an embodiment, the second interposer includes an active electrical device, a passive electrical device, or an optical device. In an embodiment, a first integrated circuit die includes: a substrate; a first interconnect structure on the backside of the substrate, wherein the first interconnect structure physically and electrically contacts the first interposer; and a second interconnect structure on the front side of the substrate, wherein the second interconnect structure physically and electrically contacts the second interposer. In an embodiment, a second integrated circuit die includes: a substrate; a first interconnect structure on the backside of the substrate, wherein the first interconnect structure physically and electrically contacts the first interposer; and a second interconnect structure on the front side of the substrate, wherein the second interconnect structure physically and electrically contacts the second interposer. In an embodiment, the sidewalls of the first interposer, the sidewalls of the second interposer, and the sidewalls of the encapsulant are laterally co-bordered. In an embodiment, a first interposer electrically couples a first integrated circuit die to a second integrated circuit die.

According to another embodiment, a package includes a first integrated circuit die and a second integrated circuit die. The first integrated circuit die includes a first substrate, a first interconnect structure on a back side of the first substrate, and a second interconnect structure on a front side of the first substrate. The second interconnect structure is electrically coupled to the first interconnect structure. The second integrated circuit die includes a second substrate, a third interconnect structure on a backside of the second substrate, and a fourth interconnect structure on a front side of the second substrate. The fourth interconnect structure is electrically coupled to the third interconnect structure. The package also includes a first interposer in physical contact with the second interconnect structure and the fourth interconnect structure, and a second interposer in physical contact with the first interconnect structure and the third interconnect structure. The second interposer electrically couples the first interconnect structure to the third interconnect structure. The first interposer electrically and optically couples the second interconnect structure to the fourth interconnect structure. In an embodiment, the second interposer includes an active electrical device or a passive electrical device. In an embodiment, the first interposer includes electrical devices and optical devices. In an embodiment, the package further includes an encapsulant between the first interposer and the second interposer, the encapsulant extending along sidewalls of the first integrated circuit die and sidewalls of the second integrated circuit die. In an embodiment, the first interposer includes a metallization layer and one or more waveguides, the second interconnect structure and the fourth interconnect structure are electrically coupled through the metallization layer, and the second interconnect structure and the fourth interconnect structure are optically coupled through the one or more waveguides. In an embodiment, the second interposer includes a first bond pad at a front side of the second interposer, and the first interconnect structure includes a second bond pad that physically contacts the first bond pad. In an embodiment, the first interposer includes a third bond pad at a front side of the first interposer, and the second interconnect structure includes a fourth bond pad that physically contacts the third bond pad.

According to still further embodiments, there is provided a package comprising: a first integrated circuit die, the first integrated circuit die comprising: a first substrate; a first interconnect structure on a back side of the first substrate; and a second interconnect structure on the front side of the first substrate, wherein the second interconnect structure is electrically coupled to the first interconnect structure; a second integrated circuit die, the second integrated circuit die comprising: a second substrate; a third interconnect structure on a backside of the second substrate; and a fourth interconnect structure on the front side of the second substrate, wherein the fourth interconnect structure is electrically coupled to the third interconnect structure; and a first interposer physically contacting the second interconnect structure and the fourth interconnect structure, the first interposer electrically and optically coupling the second interconnect structure to the fourth interconnect structure.

In some embodiments, the first interposer includes electrical devices and optical devices.

In some embodiments, the package further includes a second interposer in physical contact with the first interconnect structure and the third interconnect structure, the second interposer electrically coupling the first interconnect structure to the third interconnect structure.

In some embodiments, the second interposer includes an active electrical device or a passive electrical device.

In some embodiments, the package further includes an encapsulant between the first interposer and the second interposer, the encapsulant extending along sidewalls of the first integrated circuit die and sidewalls of the second integrated circuit die.

In some embodiments, the second interposer includes a first bond pad at a front side of the second interposer, and the first interconnect structure includes a second bond pad, wherein the second bond pad physically contacts the first bond pad.

In some embodiments, the first interposer includes a third bond pad at a front side of the first interposer, and the second interconnect structure includes a fourth bond pad, wherein the fourth bond pad physically contacts the third bond pad.

According to yet another embodiment, a method includes attaching an interposer die to a carrier wafer. A first encapsulant is formed over the carrier wafer and extends along sidewalls of the interposer die. The first integrated circuit die and the second integrated circuit die are bonded to the interposer die. The interposer die electrically couples the first integrated circuit die to the second integrated circuit die. A second encapsulant is formed over the carrier wafer and extends along sidewalls of the first integrated circuit die and sidewalls of the second integrated circuit die. An interposer wafer is bonded to the first integrated circuit die and the second integrated circuit die. The interposer wafer electrically and optically couples the first integrated circuit die to the second integrated circuit die. In an embodiment, bonding the first integrated circuit die and the second integrated circuit die to the interposer die includes bonding the first bond pad of the first integrated circuit die and the second bond pad of the second integrated circuit die to a third bond pad of the interposer die. In an embodiment, bonding the interposer wafer to the first and second integrated circuit dies includes bonding fourth and fifth bond pads of the first and second integrated circuit dies to sixth bond pads of the interposer wafer, the first and fourth bond pads being on opposite sides of the first integrated circuit die, the second and fifth bond pads being on opposite sides of the second integrated circuit die. In an embodiment, the method further includes separating the carrier wafer from the interposer wafer, and bonding the plurality of conductive connectors to the interposer wafer. In an embodiment, the first encapsulant and the second encapsulant comprise the same material. In an embodiment, the first encapsulant and the second encapsulant comprise different materials.

The foregoing outlines features of a drop-on embodiment so that those skilled in the art may better understand aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the invention.

Claims

1. A package, comprising:

a sealant having a first side and a second side opposite the first side;

a first integrated circuit die and a second integrated circuit die embedded in the encapsulant;

a first interposer on the first side of the encapsulant, the first interposer mechanically and electrically coupled to the first and second integrated circuit dies; and

a second interposer on the second side of the encapsulant, the second interposer mechanically and electrically coupled to the first and second integrated circuit dies, the second interposer optically or electrically coupling the first integrated circuit die to the second integrated circuit die.

2. The package of claim 1, wherein the first interposer comprises an active electrical device or a passive electrical device.

3. The package of claim 1, wherein the second interposer comprises an active electrical device, a passive electrical device, or an optical device.

4. The package of claim 1, wherein the first integrated circuit die comprises:

a substrate;

a first interconnect structure on a backside of the substrate, wherein the first interconnect structure physically and electrically contacts the first interposer; and

a second interconnect structure on the front side of the substrate, wherein the second interconnect structure physically and electrically contacts the second interposer.

5. The package of claim 1, wherein the second integrated circuit die comprises:

a substrate;

6. The package of claim 1, wherein the sidewalls of the first interposer, the second interposer, and the sidewalls of the encapsulant are laterally co-bordered.

7. The package of claim 1, wherein the first interposer electrically couples the first integrated circuit die to the second integrated circuit die.

8. A package, comprising:

a first integrated circuit die, the first integrated circuit die comprising:

a first substrate;

a first interconnect structure located on a backside of the first substrate; and

a second interconnect structure on the front side of the first substrate, wherein the second interconnect structure is electrically coupled to the first interconnect structure;

a second integrated circuit die, the second integrated circuit die comprising:

a second substrate;

a third interconnect structure located on a backside of the second substrate; and

a fourth interconnect structure on a front side of the second substrate, wherein the fourth interconnect structure is electrically coupled to the third interconnect structure; and

a first interposer physically contacting the second interconnect structure and the fourth interconnect structure, the first interposer electrically and optically coupling the second interconnect structure to the fourth interconnect structure.

9. The package of claim 8, wherein the first interposer comprises an electrical device and an optical device.

10. A method of forming a package, comprising:

attaching the interposer die to a carrier wafer;

forming a first encapsulant over the carrier wafer and extending along sidewalls of the interposer die;

bonding a first integrated circuit die and a second integrated circuit die to the interposer die, the interposer die electrically coupling the first integrated circuit die to the second integrated circuit die;

forming a second encapsulant over the carrier wafer and extending along sidewalls of the first and second integrated circuit dies; and

an interposer wafer is bonded to the first integrated circuit die and the second integrated circuit die, the interposer wafer electrically and optically coupling the first integrated circuit die to the second integrated circuit die.