CN108461464A - Semiconductor package and its manufacturing method - Google Patents

Semiconductor package and its manufacturing method Download PDF

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Publication number
CN108461464A
CN108461464A CN201810122289.2A CN201810122289A CN108461464A CN 108461464 A CN108461464 A CN 108461464A CN 201810122289 A CN201810122289 A CN 201810122289A CN 108461464 A CN108461464 A CN 108461464A
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CN
China
Prior art keywords
convex block
chip
external convex
layer
middle layer
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Granted
Application number
CN201810122289.2A
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Chinese (zh)
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CN108461464B (en
Inventor
不公告发明人
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Changxin Memory Technologies Inc
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Ruili Integrated Circuit Co Ltd
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Priority to CN201810122289.2A priority Critical patent/CN108461464B/en
Publication of CN108461464A publication Critical patent/CN108461464A/en
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Publication of CN108461464B publication Critical patent/CN108461464B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

This application involves field of semiconductor package, a kind of semiconductor package and its manufacturing method are disclosed.Semiconductor package includes：First packaging body has the first mounting surface and the first external convex block positioned at the first mounting surface；The anisotropic conductive film for including conducting particles is fitted on the first mounting surface；Second packaging body, including the second chip, seal the second chip the second plastic packaging material, be covered in the second plastic packaging material the first middle layer reroute structure and be projected on the first middle layer reroute structure the second external convex block.Second external convex block locally it is embedding sink into the first middle layer reroute structure dielectric layer；Wherein the hardness of conducting particles is more than the second external convex block, when the second packaging body presses to the first packaging body and with anisotropic conductive film bonding until the axial clearance between the first external convex block and the second external convex block is less than the maximum particle diameter of conducting particles.Using above-mentioned technical proposal, handling capacity can be increased, and reduce the area after encapsulation.

Description

Semiconductor package and its manufacturing method
Technical field
This application involves field of semiconductor package, and in particular, to a kind of semiconductor package and its manufacturing method.
Background technology
Wafer level chip scale encapsulates (Wafer Level Chip Scale Packaging, abbreviation WLCSP), is different from Traditional chip package mode (first cut and seal survey again, and at least increase the volume of former chip 20% after encapsulating), such technology is Packaging and testing is first carried out on full wafer wafer, then just cuts into IC (Integrated Circuit, integrated electricity one by one Road) particle, therefore the volume after encapsulation is to be equal to the full size of IC bare crystallines.And be fanned out in (FO)-WLCSP encapsulation in traditional, Chip is usually laterally to place side by side, and there are limitations for the encapsulation of this mode its handling capacity.
Invention content
The purpose of the application is to provide a kind of semiconductor package and its manufacturing method.
To achieve the goals above, in the one side of the application, a kind of semiconductor package is provided, including：First envelope Body is filled, there is the first mounting surface, the first packaging body to include the first chip, seal the first plastic packaging material of the first chip and positioned at the First external convex block of one mounting surface, the first chip have the first active face and first back side opposite with the first active face, the One chip includes the first chip bonding pad positioned at the first active face；First anisotropic conductive film, including conducting particles, the first different side Property conductive film is fitted on the first mounting surface；Second packaging body, including the second plastic packaging material of the second chip, the second chip of sealing, The first middle layer for being covered in the second plastic packaging material reroutes structure and is projected on the first middle layer and reroutes outside the second of structure Connect convex block, the second chip has the second active face and second back side opposite with the second active face, and the second chip includes being located at the Second chip bonding pad of two active faces, the first middle layer passivation layer on the second active face and positioned at the first middle layer it is blunt Change in layer and the first middle layer interconnection bumps for being bonded with the second chip bonding pad, the formation surface of the second plastic packaging material, among first The outer surface and the top surface of the first middle layer interconnection bumps of layer passivation layer are formed in the first middle layer continuous surface；First middle layer It reroutes structure to be formed on the first middle layer continuous surface, locally embedding first middle layer of sinking into reroutes knot to the second external convex block The dielectric layer of structure and the first line that structure is rerouted via the first middle layer are electrically connected to the top of the first middle layer interconnection bumps Face；Wherein, the hardness of conducting particles be more than the second external convex block, when the second packaging body press to the first packaging body and with first it is different The bonding of side's property conductive film is until the axial clearance between the first external convex block and the second external convex block is less than the maximum of conducting particles Grain size, conducting particles is locally embedding to sink into the second external convex block, make the second external convex block pass through conducting particles reach with it is first external Longitudinal electrical connection of convex block.
Optionally, the hardness of conducting particles is also more than the first external convex block.
Optionally, the junction of the first relative depature of middle layer interconnection bumps the first external convex block and the second external convex block.
Optionally, the shape of conducting particles includes spherical shape, the taper bodily form, cube shaped, any one in the polygonal bodily form.
Optionally, the grain size of conducting particles is less than 5 microns and is metal material.
Optionally, the second packaging body further includes that the second middle layer reroutes structure and is projected on the rewiring of the second middle layer The external convex block of third of structure；Second chip further includes the second middle layer passivation layer being located on second back side, and positioned at the The second middle layer interconnection bumps being electrically connected in two middle layer passivation layers and with the second chip bonding pad by silicon hole, the second plastic packaging The top surface of the package surface of material, the outer surface of the second middle layer passivation layer and the second middle layer interconnection bumps is formed among second Layer continuous surface；Second middle layer reroutes structure and is formed on the second middle layer continuous surface, and the external convex block of third is locally embedding Sink into the second middle layer to reroute the dielectric layer of structure and be electrically connected to via the second circuit of the second middle layer rewiring structure The top surface of second middle layer interconnection bumps.
Optionally, the first packaging body further includes：First bottom reroutes structure and the second bottom reroutes structure；First core Piece further include be located at the first active face on the first bottom passivation layer, be located at the first bottom passivation layer in and with the first chip bonding pad First bottom interconnection bumps of bonding, the second bottom passivation layer on first back side and in the second bottom passivation layer And the second bottom interconnection bumps being electrically connected with the first chip bonding pad by silicon hole；The formation surface of first plastic packaging material, first The outer surface of bottom passivation layer and the top surface of the first bottom interconnection bumps are formed in the first bottom continuous surface；First bottom weight cloth Cable architecture is formed on the first bottom continuous surface, and the first bottom, which reroutes structure, to be had dielectric layer, be formed in the outer of dielectric layer Terminal pad on surface and in dielectric layer and the tertiary circuit of electric connection terminal pad and the first bottom interconnection bumps； First packaging body further includes planting the soldered ball for being connected to terminal pad；The package surface of first plastic packaging material, the second bottom passivation layer it is outer Surface and the top surface of the second bottom interconnection bumps are formed in the second bottom continuous surface；Second bottom reroutes structure and is formed in the On two bottom continuous surfaces, locally embedding second bottom that sinks into reroutes the dielectric layer of structure and via the second bottom to the first external convex block 4th circuit of layer rewiring structure is electrically connected to the top surface of the second bottom interconnection bumps.
Optionally, semiconductor package further includes third packaging body, and third packaging body includes third chip, sealing third The third plastic packaging material of chip, third chip have third active face and the third back side opposite with third active face, third chip Include the first top layer passivation layer positioned at the third chip bonding pad of third active face, on third active face, be located at the first top The first top layer interconnection bumps being bonded in layer passivation layer and with third chip bonding pad；The formation surface of third plastic packaging material, the first top The outer surface and the top surface of the first top layer interconnection bumps of layer passivation layer are formed in the first top layer continuous surface；Third packaging body also wraps It includes the first top layer and reroutes structure, be formed on the first top layer continuous surface；It is projected on the first top layer reroutes structure the 4th External convex block, locally embedding first top layer that sinks into reroutes the dielectric layer of structure and is rerouted via the first top layer the 4th external convex block 5th circuit of structure is electrically connected to the top surface of the first top layer interconnection bumps；And second anisotropic conductive film, including conductive particle Son, the second anisotropic conductive film are fitted in the second middle layer and reroute on the outer surface of structure；Wherein, the second anisotropy is conductive The hardness of the conducting particles of film is more than the 4th external convex block, when third packaging body presses to the second packaging body and with the second anisotropy Conductive film bonding is until the axial clearance between the external convex block of third and the 4th external convex block is less than the second anisotropic conductive film The maximum particle diameter of conducting particles, the conducting particles is locally embedding to sink into the 4th external convex block, and the 4th external convex block is made to pass through the conduction Particle reaches to be electrically connected with the longitudinal direction of the external convex block of third.
Optionally, the second packaging body includes the packaging body of multiple vertical stacks, and two neighboring packaging body is led by anisotropy Electrolemma is bonded.
In the another aspect of the application, a kind of method for manufacturing semiconductor package is provided, this method includes：It carries For the first packaging body, there is the first mounting surface, the first packaging body includes the first chip, seal the first plastic packaging material of the first chip with And the first external convex block positioned at the first mounting surface, the first chip have the first active face and opposite with the first active face first The back side, the first chip include the first chip bonding pad positioned at the first active face；Anisotropic conductive film is fitted in the first mounting surface On, anisotropic conductive film includes conducting particles；Second packaging body, including the second chip, the second modeling for sealing the second chip are provided Envelope material, the first middle layer for being covered in the second plastic packaging material reroute structure and are projected on the first middle layer reroutes structure the Two external convex blocks, it includes position that the second chip, which has the second active face and second back side opposite with the second active face, the second chip, In the second chip bonding pad of the second active face, the first middle layer passivation layer on the second active face and among first The first middle layer interconnection bumps being bonded in layer passivation layer and with the second chip bonding pad, the formation surface of the second plastic packaging material, first The outer surface of middle layer passivation layer and the top surface of the first middle layer interconnection bumps are formed in the first middle layer continuous surface；In first Interbed reroutes structure and is formed on the first middle layer continuous surface, and the second external convex block is locally embedding to sink into the first middle layer weight cloth The dielectric layer of cable architecture is simultaneously electrically connected to the first middle layer interconnection bumps via the first line of the first middle layer rewiring structure Top surface；Second packaging body is pressed into the first packaging body, wherein the hardness of conducting particles is more than the second external convex block, when the Two packaging bodies press to the first packaging body and with anisotropic conductive film bonding until the first external convex block and the second external convex block it Between axial clearance be less than the maximum particle diameter of conducting particles, conducting particles is locally embedding to sink into the second external convex block, makes second external Convex block is reached by conducting particles to be electrically connected with the longitudinal direction of the first external convex block.
Optionally, the second packaging body further includes that the second middle layer reroutes structure and is projected on the rewiring of the second middle layer The external convex block of third of structure, method further include：Second anisotropic conductive film is fitted in the second middle layer and reroutes structure On outer surface, the second anisotropic conductive film includes conducting particles；There is provided third packaging body, third packaging body include third chip, The third plastic packaging material and the 4th external convex block of third chip are sealed, third chip includes with third active face, third chip Positioned at the third chip bonding pad of third active face；And third packaging body is pressed into the second packaging body, wherein the second anisotropy The hardness of the conducting particles of conductive film be more than the 4th external convex block, when third packaging body press to the second packaging body and with second it is different The bonding of side's property conductive film is less than the second anisotropy conduction until the axial clearance between the external convex block of third and the 4th external convex block The maximum particle diameter of the conducting particles of film, the conducting particles is locally embedding to sink into the 4th external convex block, and the 4th external convex block is made to pass through this Conducting particles reaches to be electrically connected with the longitudinal direction of the external convex block of third.
Optionally, method further includes that multiple second packaging bodies are pressed between the first packaging body and third packaging body, described It is bonded by anisotropic conductive film between multiple second packaging bodies.
Optionally, the hardness of conducting particles is also more than the first external convex block.
Optionally, the junction of the first relative depature of middle layer interconnection bumps the first external convex block and the second external convex block.
Optionally, the grain size of conducting particles is less than 5 microns and is metal material.
In above-mentioned technical proposal, vertical stack is completed by wafer bonding, it can be with compared with the mode of chip placed side by side Increase handling capacity, and reduces the area after encapsulation.In addition, be bonded by using anisotropic conductive film (ACF), compared with welding, The thickness of each packaging body interlayer can be reduced.
Other features and advantage will be described in detail in subsequent specific embodiment part.
Description of the drawings
Attached drawing is for providing further understanding of the present application, and a part for constitution instruction, with following tool Body embodiment is used to explain the application together, but does not constitute the limitation to the application.In the accompanying drawings：
Fig. 1 is the sectional view according to the semiconductor package of the embodiment of the application；
Fig. 2 is the sectional view according to the semiconductor package of another embodiment herein；
Fig. 3 is the sectional view according to the semiconductor package of another further embodiment of the application；
Fig. 4 A to Fig. 4 D are the schematic shapes according to the conducting particles in presently filed embodiment；
Fig. 5 A to Fig. 5 H show the method for manufacturing semiconductor package of the embodiment according to the application The schematic diagram of the structure obtained after executing each step；And
Fig. 6 A to Fig. 6 I show that the manufacture that is used for according to the embodiment of the application has double-layer heavy wiring layer (RDL) Packaging body the schematic diagram of structure that is obtained after executing each step of method.
Reference sign
100,200,300 semiconductor package, 110 bottom packaging body
111 first mounting surface, 112 first external convex block
113 bottom chip 114a active faces
115 bottom chip pad of the back sides 114b
116a the first bottom passivation layer 116b the second bottom passivation layers
117a the first bottom interconnection bumps 117b the second bottom interconnection bumps
118 silicon hole, 120 ACF
121 conducting particles, 130 top layer packaging body
131 top layer chip 132a active faces
133 top layer chip bonding pad of the back sides 132b
134 first top layer passivation layer, 135 first top layer interconnection bumps
140 top layer plastic packaging material, 141 second continuous surface
150 bottom plastic packaging material the first continuous surfaces of 151a
151b the second continuous surface the first bottoms of 152a reroute structure
The second bottoms of 152b reroute 153 dielectric layer outer surface of structure
154a dielectric layer 154b dielectric layers
155a circuit 155b circuits
156 terminal pad, 157 soldered ball
160 first top layers reroute 161 second mounting surface of structure
163 dielectric layer, 164 circuit
165 second external convex blocks
210 first packaging body, 211 first mounting surface
212 first external convex block, 213 first chip
The back sides 214a active face 214b
215 first chip bonding pad 216a the first bottom passivation layers
216b the second bottom passivation layer 217a the first bottom interconnection bumps
218 silicon hole of the second bottoms of 217b interconnection bumps
220 ACF, 221 conducting particles
230 second packaging body, 231 second chip
The back sides 232a active face 232b
233 second chip bonding pad 234a the first top layer passivation layers
234b the second top layer passivation layer 235a the first top layer interconnection bumps
236 silicon hole of the second top layers of 235b interconnection bumps
240 second plastic packaging material 241a third continuous surfaces
The 4th the first top layers of continuous surface 242a of 241b reroute structure
The second top layers of 242b reroute 243 second mounting surface of structure
244a dielectric layer 244b dielectric layers
245a circuit 245b circuits
The second external external convex blocks of convex block 246b thirds of 246a
247 third mounting surface, 250 first plastic packaging material
251a the first continuous surface the second continuous surfaces of 251b
The first bottoms of 252a reroute structure the second bottoms of 252b and reroute structure
253 dielectric layer outer surface 254a dielectric layers
254b dielectric layer 255a circuits
256 terminal pad of 255b circuits
257 soldered balls
310 first packaging body, 311 first mounting surface
312 first external convex block, 313 first chip
First back sides 314a the first active face 314b
315 first chip bonding pad 316a the first bottom passivation layers
316b the second bottom passivation layer 317a the first bottom interconnection bumps
318 silicon hole of the second bottoms of 317b interconnection bumps
320 ACF, 321 conducting particles
330 second packaging body, 331 second chip
332 second active face, 333 second back side
334 second chip bonding pad 335a the first middle layer passivation layers
335b the second middle layer passivation layer 336a the first middle layer interconnection bumps
337 silicon hole of the second middle layers of 336b interconnection bumps
340 second plastic packaging material 341a the first middle layer continuous surfaces
341b the second middle layer continuous surface the first middle layers of 342a reroute structure
The second middle layers of 342b reroute structure
344a dielectric layer 344b dielectric layers
345a circuit 345b circuits
The second external external convex blocks of convex block 346b thirds of 346a
350 first plastic packaging material 351a the first bottom continuous surfaces
351b the second bottom continuous surface the first bottoms of 352a reroute structure
The second bottoms of 352b reroute the outer surface of 353 dielectric layer of structure
354a dielectric layer 354b dielectric layers
355a circuit 355b circuits
356 terminal pad, 357 soldered ball
360 third packaging body, 361 third chip
The 362a third active face 362b thirds back side
363 third chip bonding pad, 364 first top layer passivation layer
365 first top layer interconnection bumps, 370 third plastic packaging material
371 first top layer continuous surface, 372 first top layer reroutes structure
374 dielectric layer, 375 circuit
376 the 4th external convex block, 380 ACF
381 conducting particles
510 carrier, 520 hot degumming
611 first vector, 612 first hot degumming
613 Second support, 614 second hot degumming
The hot degumming of 615 third carrier, 616 third
The 4th hot degumming of 617 the 4th carrier 618
620 chip 621a active faces
622 chip bonding pad of the back sides 621b
623 silicon hole, 624 first passivation layer
625 first metal coupling, 626 second passivation layer
627 second metal coupling, 628 plastic packaging material
629 first continuous surfaces 630 first reroute structure
631 first dielectric layer, 632 first line
633 second continuous surfaces 634 second reroute structure
635 second dielectric layer, 636 second circuit
637 external convex blocks
Specific implementation mode
The specific implementation mode of the application is described in detail below in conjunction with attached drawing.It should be understood that this place is retouched The specific implementation mode stated is only used for describing and explaining the application, is not intended to limit this application.
In this application, in the absence of explanation to the contrary, the noun of locality used such as " above/above and below/under, The left side/left side, the right/right side " is typically referred to reference to upper and lower, left and right shown in the drawings." inside and outside " typically refers to relative to each Component profile itself it is inside and outside.
In this application if using term " front of chip ", " active face of chip ", " first surface of chip ", It can refer to the surface with integrated circuit；In this application if using term " back side of chip ", " the second table of chip Face ", then its can refer to the surface opposite with " front of chip ", " active face of chip ", " first surface of chip ".
In the accompanying drawings, the shape shown can be changed according to manufacturing process and/or tolerance.Therefore, the example of the application Property embodiment be not limited to specific shape shown in the accompanying drawings, and may include in the fabrication process caused by shape change.This Outside, the different elements in attached drawing and region are only schematically shown, therefore the application is not limited to relative size shown in the accompanying drawings Or distance.
Fig. 1 is the sectional view according to the semiconductor package 100 of the embodiment of the application.With reference to figure 1, according to this The semiconductor package 100 of the embodiment of application may include bottom packaging body 110, which can wrap Include bottom chip 113.Bottom chip 113 can have the active face 114a and back side 114b opposite with active face 114a.Bottom Chip 113 may include the bottom chip pad 115 positioned at active face 114a.The first bottom can be formed on active face 114a Passivation layer 116a, the first bottom interconnection bumps 117a be located in the first bottom passivation layer 116a and with 115 key of bottom chip pad It closes.
The second bottom passivation layer 116b, the second bottom interconnection bumps 117b can be overleaf formed on 114b is located at the second bottom It can be electrically connected in layer passivation layer 116b and with bottom chip pad 115 by silicon hole 118.
The type of first bottom passivation layer 116a or the second bottom passivation layer 116b can include but is not limited to unorganic glass And organic polymer.The material of unorganic glass can be including but not limited to oxide is (for example, SiO2、Al2O3、TiO2、ZrO2、 Fe2O3、SixOy), silicate (for example, PSG, BSG, BPSG), nitride is (for example, Si3N4、SixNyH、BN、AlN、GaN).It is organic High molecular material can be including but not limited to synthetic resin (for example, polyimide based resin, polysiloxanes resinoid) closes At rubber (for example, silicone rubber).The material of first bottom interconnection bumps 117a or the second bottom interconnection bumps 117b can wrap Contain but be not limited to gold, silver, copper, platinum, aluminium, it is preferable that the first bottom interconnection bumps 117a's or the second bottom interconnection bumps 117b Material can include copper.
Bottom packaging body 110 can also include the bottom plastic packaging material 150 of sealing bottom chip 113.Bottom plastic packaging material 150 can With comprising such as epoxy molding material (Epoxy Molding Compound, EMC), but those skilled in the art can manage Solution, other materials is also applicable.Bottom plastic packaging material 150 formed surface, the first bottom passivation layer 116a outer surface and The top surface of first bottom interconnection bumps 117a is formed in the first continuous surface 151a.
Bottom packaging body 110 can also include that the first bottom reroutes structure 152a, be formed in the first continuous surface 151a On.It may include dielectric layer 154a that first bottom, which reroutes structure 152a, the terminal soldering positioned at the outer surface 153 of dielectric layer 154a Disk 156, and the circuit that is electrically connected with the first bottom interconnection bumps 117a in dielectric layer 154a and by terminal pad 156 155a.The material of dielectric layer 154a can include high molecular film material, such as benzocyclobutene (BCB), polyimides (PI) Deng, but not limited to this.The material of dielectric layer 154a can also include other insulating materials.For example, rewiring (RDL) may be used The terminal pad 156 that technology forms circuit 155a in dielectric layer 154a and is electrically connected with circuit 155a.RDL technologies are abilities Technology known to field technique personnel, repeats no more herein.In the embodiment of the application, the material of circuit 155a can be with Including one of copper and aluminium.But it will be understood by those skilled in the art that the material of circuit 155a can include other metals Other kinds of conductive material other than (such as gold, silver, platinum) or metal.In the embodiment of the application, circuit 155a and terminal pad 156 can use identical material.In another embodiment herein, circuit 155a and terminal soldering Disk 156 can use different materials.In the embodiment of the application, circuit 155a can be fan-out circuit.
Bottom packaging body 110 can also include planting the soldered ball 157 for being connected to terminal pad 156.It is, for example, possible to use planting ball work The plant of soldered ball 157 is connected to terminal pad 156 by skill.
The package surface of bottom plastic packaging material 150, the outer surface of the second bottom passivation layer 116b and the interconnection of the second bottom are convex The top surface of block 117b is formed in the second continuous surface 151b.
Bottom packaging body 110 can also include that the second bottom reroutes structure 152b, be formed in the second continuous surface 151b On.It may include dielectric layer 154b that second bottom, which reroutes structure 152b, is located in dielectric layer 154b and is interconnected with the second bottom The circuit 155b of convex block 117b electrical connections.The material of dielectric layer 154b can include high molecular film material, such as benzocyclobutane Alkene (BCB), polyimides (PI) etc., but not limited to this.The material of dielectric layer 154b can also include other insulating materials.Example Such as, rewiring (RDL) technology may be used and form circuit 155b in dielectric layer 154b.In the embodiment of the application In, the material of circuit 155b can include one of copper and aluminium.But it will be understood by those skilled in the art that circuit 155b Material can include other kinds of conductive material other than other metals (such as gold, silver, platinum) or metal.
Bottom packaging body 110 can also include from dielectric layer 154b to the first external convex block 112 exposed outside, this is outside first Convex block 112 is connect to be electrically connected with circuit 155b.In the embodiment of the application, the first external convex block 112 can protrude from Dielectric layer 154b.Second bottom, which reroutes the outer surface of structure 152b and the top surface of the first external convex block 112, can form first Mounting surface 111.The material of first external convex block 112 can be including but not limited to gold, silver, copper, platinum, aluminium, it is preferable that first is external The material of convex block 112 can include copper.
Semiconductor package 100 can also include anisotropic conductive film (An-isotropic Conductive Film, ACF) 120, can include conducting particles 121.ACF 120 is fitted on the first mounting surface 111.The feature of ACF 120 will It is described in detail later.
Semiconductor package 100 can also include top layer packaging body 130, which may include top layer Chip 131.Top layer chip 131 can have the active face 132a and back side 132b opposite with active face 132a.Top layer chip 131 It may include the top layer chip bonding pad 133 positioned at active face 132a.The first top layer passivation layer can be formed on active face 132a 134, the first top layer interconnection bumps 135 are located in the first top layer passivation layer 134 and are bonded with top layer chip bonding pad 133.
The type of first top layer passivation layer 134 can include but is not limited to unorganic glass and organic polymer.Unorganic glass Material can be including but not limited to oxide is (for example, SiO2、Al2O3、TiO2、ZrO2、Fe2O3、SixOy), silicate (example Such as, PSG, BSG, BPSG), nitride is (for example, Si3N4、SixNyH、BN、AlN、GaN).Organic macromolecule material can include But it is not limited to, synthetic resin (for example, polyimide based resin, polysiloxanes resinoid), synthetic rubber are (for example, silicone rubber Glue).The material of first top layer interconnection bumps 135 can be including but not limited to gold, silver, copper, platinum, aluminium, it is preferable that the first top layer is mutual Even the material of convex block 135 can include copper.
Top layer packaging body 130 can also include the top layer plastic packaging material 140 of sealing top layer chip 131.Top layer plastic packaging material 140 can With comprising such as epoxy molding material (Epoxy Molding Compound, EMC), but those skilled in the art can manage Solution, other materials is also applicable.Top layer plastic packaging material 140 forms surface, the outer surface of the first top layer passivation layer 134 and the The top surface of one top layer interconnection bumps 135 is formed in the second continuous surface 141.
Top layer packaging body 130 can also include that the first top layer reroutes structure 160, be formed on the second continuous surface 141. It may include dielectric layer 163 that first top layer, which reroutes structure 160, the circuit 164 being located in dielectric layer 163, the circuit 164 and the One top layer interconnection bumps 135 are electrically connected.
The material of dielectric layer 163 can include high molecular film material, such as benzocyclobutene (BCB), polyimides (PI) etc., but not limited to this.The material of dielectric layer 163 can also include other insulating materials.For example, rewiring may be used (RDL) technology forms circuit 164 in dielectric layer 163.In the embodiment of the application, the material of circuit 164 can be with Including one of copper and aluminium.But it will be understood by those skilled in the art that the material of circuit 164 can include other metals Other kinds of conductive material other than (such as gold, silver, platinum) or metal.
Top layer packaging body 130 can also include from dielectric layer 163 to the second external convex block 165 exposed outside, this is outside second Convex block 165 is connect to be electrically connected with circuit 164.In the embodiment of the application, the second external convex block 165 can protrude from Jie Electric layer 163.First top layer, which reroutes the outer surface of structure 160 and the top surface of the second external convex block 165, can form the second installation Face 161.The material of second external convex block 165 can be including but not limited to gold, silver, copper, platinum, aluminium, it is preferable that the second external convex block 165 material can include copper.
It can use a plurality of ways to form 112 or the second external convex block 165 of the first external convex block.In one example, It can be external by rerouting growth regulation one on the outer surface of structure 160 in the second bottom rewiring structure 152b or the first top layer Then the external convex block 165 of convex block 112 or the second is moulded the 112 or the second external convex block 165 of the first external convex block of growth Envelope.In another example, structure 152b can be rerouted in the second bottom or the first top layer is rerouted and made by lithography in structure 160 Cavity, and (such as electro-coppering) is electroplated in the cavities to form 112 or the second external convex block 165 of the first external convex block.This field Technical staff is appreciated that other the well known feasible patterns for being used to form 112 or the second external convex block 165 of the first external convex block Also belong to scope of the present application.
In presently filed embodiment, the hardness of conducting particles 121 can be more than the second external convex block 165.When second When packaging body 130 is pressed to the first packaging body 110, the first packaging body 110 and ACF120 is bonded, until the first external convex block 112 and the second axial clearance between external convex block 165 be less than the maximum particle diameter of conducting particles 121.Conducting particles 121 can office Portion is embedding to sink into the second external convex block 165, and the second external convex block 165 is made to reach and the first external convex block 112 by conducting particles 121 Longitudinal electrical connection.
In presently filed embodiment, the hardness of conducting particles 121 can also be more than the first external convex block 112, thus When the second packaging body 130 presses to the first packaging body 110, conducting particles 121 locally embedding can also sink into the first external convex block 112, it is possible thereby to increase conductive area, reduce impedance.
Bottom chip 113 or the type of top layer chip 131 may include memory chip and logic chip.Memory chip Example can include but is not limited to, random access memory (RAM).The example of RAM may include dynamic random access memory Device (DRAM) or static RAM (SRAM).The example of logic chip can include but is not limited to, graphics process list First (Graphic Processing Unit, GPU) chip, central processing unit (Central Processing Unit, CPU) Chip, system level chip (System on Chip, SOC).
Fig. 2 is the sectional view according to the semiconductor package 200 of another embodiment herein.With reference to figure 2, according to The semiconductor package 200 of presently filed embodiment may include the first packaging body 210, which can be with Including the first chip 213.First chip 213 can have the active face 214a and back side 214b opposite with active face 214a.The One chip 213 may include the first chip bonding pad 215 positioned at active face 214a.The first bottom can be formed on active face 214a Layer passivation layer 216a, the first bottom interconnection bumps 217a be located at the first bottom passivation layer 216a it is interior and with the first chip bonding pad 215 Bonding.
The second bottom passivation layer 216b, the second bottom interconnection bumps 217b can be overleaf formed on 214b is located at the second bottom It can be electrically connected in layer passivation layer 216b and with the first chip bonding pad 215 by silicon hole 218.
The type of first bottom passivation layer 216a or the second bottom passivation layer 216b can include but is not limited to unorganic glass And organic polymer.The material of unorganic glass can be including but not limited to oxide is (for example, SiO2、Al2O3、TiO2、ZrO2、 Fe2O3、SixOy), silicate (for example, PSG, BSG, BPSG), nitride is (for example, Si3N4、SixNyH、BN、AlN、GaN).It is organic High molecular material can be including but not limited to synthetic resin (for example, polyimide based resin, polysiloxanes resinoid) closes At rubber (for example, silicone rubber).The material of first bottom interconnection bumps 217a or the second bottom interconnection bumps 217b can wrap Contain but be not limited to gold, silver, copper, platinum, aluminium, it is preferable that the first bottom interconnection bumps 217a's or the second bottom interconnection bumps 217b Material can include copper.
First packaging body 210 can also include the first plastic packaging material 250 of the first chip 213 of sealing.First plastic packaging material 250 can With comprising such as epoxy molding material (Epoxy Molding Compound, EMC), but those skilled in the art can manage Solution, other materials is also applicable.First plastic packaging material 250 formed surface, the first bottom passivation layer 216a outer surface and The top surface of first bottom interconnection bumps 217a is formed in the first continuous surface 251a.
First packaging body 210 can also include that the first bottom reroutes structure 252a, be formed in the first continuous surface 251a On.It may include dielectric layer 254a that first bottom, which reroutes structure 252a, the terminal soldering positioned at the outer surface 253 of dielectric layer 254a Disk 256, and the circuit that is electrically connected with the first bottom interconnection bumps 217a in dielectric layer 254a and by terminal pad 256 255a.The material of dielectric layer 254a can include high molecular film material, such as benzocyclobutene (BCB), polyimides (PI) Deng, but not limited to this.The material of dielectric layer 254a can also include other insulating materials.For example, rewiring (RDL) may be used The terminal pad 256 that technology forms circuit 255a in dielectric layer 254a and is electrically connected with circuit 255a.RDL technologies are abilities Technology known to field technique personnel, repeats no more herein.In the embodiment of the application, the material of circuit 255a can be with Including one of copper and aluminium.But it will be understood by those skilled in the art that the material of circuit 255a can include other metals Other kinds of conductive material other than (such as gold, silver, platinum) or metal.In the embodiment of the application, circuit 255a and terminal pad 256 can use identical material.In another embodiment herein, circuit 255a and terminal soldering Disk 256 can use different materials.In the embodiment of the application, circuit 255a can be fan-out circuit.
First packaging body 210 can also include planting the soldered ball 257 for being connected to terminal pad 256.It is, for example, possible to use planting ball work The plant of soldered ball 257 is connected to terminal pad 256 by skill.
The package surface of first plastic packaging material 250, the outer surface of the second bottom passivation layer 216b and the interconnection of the second bottom are convex The top surface of block 217b is formed in the second continuous surface 251b.
First packaging body 210 can also include that the second bottom reroutes structure 252b, be formed in the second continuous surface 251b On.It may include dielectric layer 254b that second bottom, which reroutes structure 252b, is located in dielectric layer 254b and is interconnected with the second bottom The circuit 255b of convex block 217b electrical connections.The material of dielectric layer 254b can include high molecular film material, such as benzocyclobutane Alkene (BCB), polyimides (PI) etc., but not limited to this.The material of dielectric layer 254b can also include other insulating materials.Example Such as, rewiring (RDL) technology may be used and form circuit 255b in dielectric layer 254b.In the embodiment of the application In, the material of circuit 255b can include one of copper and aluminium.But it will be understood by those skilled in the art that circuit 255b Material can include other kinds of conductive material other than other metals (such as gold, silver, platinum) or metal.
First packaging body 210 can also include from dielectric layer 254b to the first external convex block 212 exposed outside, this is outside first Convex block 212 is connect to be electrically connected with circuit 255b.In the embodiment of the application, the first external convex block 212 can protrude from Dielectric layer 254b.Second bottom, which reroutes the outer surface of structure 252b and the top surface of the first external convex block 212, can form first Mounting surface 211.The material of first external convex block 212 can be including but not limited to gold, silver, copper, platinum, aluminium, it is preferable that first is external The material of convex block 212 can include copper.
Semiconductor package 200 can also include anisotropic conductive film (An-isotropic Conductive Film, ACF) 220, can include conducting particles 221.ACF 220 is fitted on the first mounting surface 211.The feature of ACF 220 will It is described in detail later.
Semiconductor package 200 can also include the second packaging body 230, which may include second Chip 231.Second chip 231 can have the active face 232a and back side 232b opposite with active face 232a.Second chip 231 It may include the second chip bonding pad 233 positioned at active face 232a.The first top layer passivation layer can be formed on active face 232a 234a, the first top layer interconnection bumps 235a are located in the first top layer passivation layer 234a and are bonded with the second chip bonding pad 233.
The second top layer passivation layer 234b, the second top layer interconnection bumps 235b can be overleaf formed on 232b is located at the second top It can be electrically connected in layer passivation layer 234b and with the second chip bonding pad 233 by silicon hole 236.
The type of first top layer passivation layer 234a or the second top layer passivation layer 234b can include but is not limited to unorganic glass And organic polymer.The material of unorganic glass can be including but not limited to oxide is (for example, SiO2、Al2O3、TiO2、ZrO2、 Fe2O3、SixOy), silicate (for example, PSG, BSG, BPSG), nitride is (for example, Si3N4、SixNyH、BN、AlN、GaN).It is organic High molecular material can be including but not limited to synthetic resin (for example, polyimide based resin, polysiloxanes resinoid) closes At rubber (for example, silicone rubber).The material of first top layer interconnection bumps 235a or the second top layer interconnection bumps 235b can wrap Contain but be not limited to gold, silver, copper, platinum, aluminium, it is preferable that the first top layer interconnection bumps 235a's or the second top layer interconnection bumps 235b Material can include copper.
Second packaging body 230 can also include the second plastic packaging material 240 of the second chip 231 of sealing.Second plastic packaging material 240 can With comprising such as epoxy molding material (Epoxy Molding Compound, EMC), but those skilled in the art can manage Solution, other materials is also applicable.Second plastic packaging material 240 formed surface, the first top layer passivation layer 234a outer surface and The top surface of first top layer interconnection bumps 235a is formed in third continuous surface 241a.
Second packaging body 230 can also include that the first top layer reroutes structure 242a, be formed in third continuous surface 241a On.It may include dielectric layer 244a that first top layer, which reroutes structure 242a, the circuit 245a being located in dielectric layer 244a, the circuit 245a is electrically connected with the first top layer interconnection bumps 235a.
The material of dielectric layer 244a can include high molecular film material, such as benzocyclobutene (BCB), polyimides (PI) etc., but not limited to this.The material of dielectric layer 244a can also include other insulating materials.For example, rewiring may be used (RDL) technology forms circuit 245a in dielectric layer 244a.In the embodiment of the application, the material of circuit 245a can To include one of copper and aluminium.But it will be understood by those skilled in the art that the material of circuit 245a can include other gold Belong to the other kinds of conductive material other than (such as gold, silver, platinum) or metal.
Second packaging body 230 can also include from dielectric layer 244a to the second external convex block 246a exposed outside, this second External convex block 246a is electrically connected with circuit 245a.In the embodiment of the application, the second external convex block 246a can dash forward For dielectric layer 244a.First top layer reroutes the outer surface of structure 242a and the top surface of the second external convex block 246a and can be formed Second mounting surface 243.The material of second external convex block 246a can be including but not limited to gold, silver, copper, platinum, aluminium, it is preferable that the The material of two external convex block 246a can include copper.
It can use a plurality of ways to form 212 or the second external convex block 246a of the first external convex block.In one example, It can be by being rerouted on the outer surface of structure 242a outside growth regulation one in the second bottom rewiring structure 252b or the first top layer The external convex block 246a of convex block 212 or the second is met, then the 212 or the second external convex block 246a of the first external convex block of growth is carried out Plastic packaging.In another example, structure 252b can be rerouted in the second bottom or the first top layer reroutes structure 242a glazings Cavity is carved, and (such as electro-coppering) is electroplated in the cavities to form 212 or the second external convex block 246a of the first external convex block.This Field technology personnel be appreciated that be used to form 212 or the second external convex block 246a of the first external convex block other well known to can Line mode also belongs to scope of the present application.
In presently filed embodiment, the hardness of conducting particles 221 can be more than the second external convex block 246a.When second When packaging body 230 is pressed to the first packaging body 210, the first packaging body 210 and ACF 220 is bonded, until the first external convex block 212 and the second axial clearance between external convex block 246a be less than the maximum particle diameter of conducting particles 221.Conducting particles 221 can be with Part is embedding to sink into the second external convex block 246a, make the second external convex block 246a pass through conducting particles 221 reach with it is first external convex Longitudinal electrical connection of block 212.
In presently filed embodiment, the hardness of conducting particles 221 can also be more than the first external convex block 212, thus When the second packaging body 230 presses to the first packaging body 210, conducting particles 221 locally embedding can also sink into the first external convex block 212, it is possible thereby to increase conductive area, reduce impedance.
The package surface of second plastic packaging material 240, the outer surface of the second top layer passivation layer 234b and the interconnection of the second top layer are convex The top surface of block 235b is formed in the 4th continuous surface 241b.
Second packaging body 230 can also include that the second top layer reroutes structure 242b, be formed in the 4th continuous surface 241b On.It may include dielectric layer 244b that second top layer, which reroutes structure 242b, is located in dielectric layer 244b and is interconnected with the second top layer The circuit 245b of convex block 235b electrical connections.The material of dielectric layer 244b can include high molecular film material, such as benzocyclobutane Alkene (BCB), polyimides (PI) etc., but not limited to this.The material of dielectric layer 244b can also include other insulating materials.Example Such as, rewiring (RDL) technology may be used and form circuit 245b in dielectric layer 244b.In the embodiment of the application In, the material of circuit 245b can include one of copper and aluminium.But it will be understood by those skilled in the art that circuit 245b Material can include other kinds of conductive material other than other metals (such as gold, silver, platinum) or metal.
Second packaging body 230 can also include from dielectric layer 244b to the external convex block 246b of third exposed outside, the third External convex block 246b is electrically connected with circuit 245b.In the embodiment of the application, the external convex block 246b of third can dash forward For dielectric layer 244b.Second top layer reroutes the outer surface of structure 242b and the top surface of the external convex block 246b of third and can be formed Third mounting surface 247.The third mounting surface 247 can be used for being superimposed other packaging bodies on it.The external convex block 246b of third Material can be including but not limited to gold, silver, copper, platinum, aluminium, it is preferable that the material of the external convex block 246b of third can include copper.
It can use a plurality of ways to form the external convex block 246b of third.It in one example, can be by the second top Layer reroutes three external convex block 246b of growth regulation on the outer surface of structure 242b, then convex block 246b external to the third of growth into Row plastic packaging.In another example, it can be rerouted in the second top layer and make cavity by lithography on structure 242b, and be electroplated in the cavities (such as electro-coppering) forms the external convex block 246b of third.It will be understood by those skilled in the art that it is external convex to be used to form third Other well known feasible patterns of block 246b also belong to scope of the present application.
The type of first chip 213 or the second chip 231 may include memory chip and logic chip.Memory chip Example can include but is not limited to, random access memory (RAM).The example of RAM may include dynamic random access memory Device (DRAM) or static RAM (SRAM).The example of logic chip can include but is not limited to, graphics process list First (Graphic Processing Unit, GPU) chip, central processing unit (Central Processing Unit, CPU) Chip, system level chip (System on Chip, SOC).
Fig. 3 is the sectional view according to the semiconductor package 300 of another further embodiment of the application.Reference chart 3, may include according to the semiconductor package 300 of presently filed embodiment
First packaging body 310 has the first mounting surface 311.First packaging body 310 may include the first chip 313, sealing First plastic packaging material 350 of the first chip 313 and the first external convex block 312 positioned at the first mounting surface 311.First chip 313 There can be the first active face 314a and first back side 314b opposite with the first active face 314a.First chip 313 can be with It include the first chip bonding pad 315 positioned at the first active face 314a.
First plastic packaging material 350 can include such as epoxy molding material (Epoxy Molding Compound, EMC), It will be recognized to those skilled in the art that other materials is also applicable.
First chip 313 can also include the first bottom passivation layer 316a being located on the first active face 314a, be located at the The first bottom interconnection bumps 317a for be bonded in one bottom passivation layer 316a and with the first chip bonding pad 315, positioned at first back side The second bottom passivation layer 316b on 314b and in the second bottom passivation layer 316b and pass through silicon hole 318 and the first core The second bottom interconnection bumps 317b that piece pad 315 is electrically connected.
The type of first bottom passivation layer 316a or the second bottom passivation layer 316b can include but is not limited to unorganic glass And organic polymer.The material of unorganic glass can be including but not limited to oxide is (for example, SiO2、Al2O3、TiO2、ZrO2、 Fe2O3、SixOy), silicate (for example, PSG, BSG, BPSG), nitride is (for example, Si3N4、SixNyH、BN、AlN、GaN).It is organic High molecular material can be including but not limited to synthetic resin (for example, polyimide based resin, polysiloxanes resinoid) closes At rubber (for example, silicone rubber).The material of first bottom interconnection bumps 317a or the second bottom interconnection bumps 317b can wrap Contain but be not limited to gold, silver, copper, platinum, aluminium, it is preferable that the first bottom interconnection bumps 317a's or the second bottom interconnection bumps 317b Material can include copper.
First plastic packaging material 350 forms surface, the outer surface of the first bottom passivation layer 316a and the first bottom interconnection bumps The top surface of 317a is formed in the first bottom continuous surface 351a.First packaging body 310 can also include that the first bottom reroutes knot Structure 352a is formed on the first bottom continuous surface 351a.First bottom reroute structure 352a can have dielectric layer 354a, The terminal pad 356 being formed on the outer surface 353 of dielectric layer 354a and the simultaneously electric connection terminal weldering in dielectric layer 354a The circuit 355a of disk 356 and the first bottom interconnection bumps 317a.In the embodiment of the application, circuit 355a can be Fan-out circuit.
Outer surface and the second bottom interconnection bumps of the package surface of first plastic packaging material 350, the second bottom passivation layer 316b The top surface of 317b is formed in the second bottom continuous surface 351b.First packaging body 310 can also include that the second bottom reroutes knot Structure 352b is formed on the second bottom continuous surface 351b.Second bottom, which reroutes structure 352b, can have dielectric layer 354b With the circuit 355b being electrically connected in dielectric layer 354b and with the top surface of the second bottom interconnection bumps 317b.
The material of dielectric layer 354a or 354b can include high molecular film material, such as benzocyclobutene (BCB), polyamides Imines (PI) etc., but not limited to this.The material of dielectric layer 354a or 354b can also include other insulating materials.For example, can be with Circuit 355a or 355b are formed in dielectric layer 354a or 354b using rewiring (RDL) technology.In the implementation of the application In mode, the material of circuit 355a or 355b can include one of copper and aluminium.But those skilled in the art can manage Solution, the material of circuit 355a or 355b can include that other kinds of other than other metals (such as gold, silver, platinum) or metal is led Electric material.
In presently filed embodiment, the first external convex block 312 locally can reroute structure by embedding second bottom that sinks into It is convex that the dielectric layer 354b of 352b and the circuit 355b that structure 352b is rerouted via the second bottom are electrically connected to the interconnection of the second bottom The top surface of block 317b.The material of first external convex block 312 can be including but not limited to gold, silver, copper, platinum, aluminium, it is preferable that first The material of external convex block 312 can include copper.
In presently filed embodiment, the first packaging body 310 can also include planting the soldered ball for being connected to terminal pad 356 357。
Semiconductor package 300 can also include anisotropic conductive film (ACF) 320, including conducting particles 321, the ACF 320 are fitted on the first mounting surface 311.
Semiconductor package 300 can also include the second packaging body 330.Second packaging body 330 may include the second core Piece 331, the second plastic packaging material 340 for sealing the second chip 331, the first middle layer rewiring knot for being covered in the second plastic packaging material 340 Structure 342a and the second external convex block 346a for being projected on the first middle layer rewiring structure 342a.Second chip 331 can have There are the second active face 332 and second back side 333 opposite with the second active face 332.Second chip 331 may include being located at second Second chip bonding pad 334 of active face 332, the first middle layer passivation layer 335a on the second active face 332 and it is located at The first middle layer interconnection bumps 336a being bonded in first middle layer passivation layer 335a and with the second chip bonding pad 334.Second modeling Envelope expects the top surface of 340 formation surface, the outer surface and the first middle layer interconnection bumps 336a of the first middle layer passivation layer 335a It is formed in the first middle layer continuous surface 341a.First middle layer reroutes structure 342a and is formed in the first middle layer continuous surface On 341a.Locally embedding first middle layer of sinking into reroutes the dielectric layer 344a of structure 342a and via the to second external convex block 346a The circuit 345a of one middle layer rewiring structure 342a is electrically connected to the top surface of the first middle layer interconnection bumps 336a.
In presently filed embodiment, the hardness of conducting particles 321 is more than the second external convex block 346a.When the second encapsulation Body 330 presses to the first packaging body 310, with the bondings of ACF 320 until the first external convex block 312 and the second external convex block 346a it Between axial clearance be less than the maximum particle diameter of conducting particles 321, the part of conducting particles 321 is embedding to sink into the second external convex block 346a, Make the second external convex block 346a pass through conducting particles 321 reach with the first external convex block 312 longitudinal direction be electrically connected.
In presently filed embodiment, the hardness of conducting particles 321 can also be more than the first external convex block 312, thus When the second packaging body 330 presses to the first packaging body 310, conducting particles 321 locally embedding can also sink into the first external convex block 312, it is possible thereby to increase conductive area, reduce impedance.
Second packaging body 330 can also include that the second middle layer reroutes structure 342b and is projected on the second middle layer weight The external convex block 346b of third of wire structures 342b.Second chip 331 can also include be located at second back side 333 on second in Interbed passivation layer 335b, and in the second middle layer passivation layer 335b and pass through silicon hole 337 and the second chip bonding pad 334 Second middle layer interconnection bumps 336b of electrical connection.The package surface of second plastic packaging material 340, the second middle layer passivation layer 335b Outer surface and the top surface of the second middle layer interconnection bumps 336b are formed in the second middle layer continuous surface 341b.Second middle layer weight Wire structures 342b is formed on the second middle layer continuous surface 341b.The external convex block 346b of third is locally embedding to sink among second Layer reroutes the dielectric layer 344b of structure 342b and is electrically connected to via the circuit 345b of the second middle layer rewiring structure 342b The top surface of second middle layer interconnection bumps 336b.
Second plastic packaging material 340 can include such as epoxy molding material (Epoxy Molding Compound, EMC), It will be recognized to those skilled in the art that other materials is also applicable.
The type of first middle layer passivation layer 335a or the second middle layer passivation layer 335b can include but is not limited to inorganic Glass and organic polymer.The material of unorganic glass can be including but not limited to oxide is (for example, SiO2、Al2O3、TiO2、 ZrO2、Fe2O3、SixOy), silicate (for example, PSG, BSG, BPSG), nitride is (for example, Si3N4、SixNyH、BN、AlN、 GaN).Organic macromolecule material can be including but not limited to, and synthetic resin is (for example, polyimide based resin, polysiloxane-based Resin), synthetic rubber (for example, silicone rubber).First middle layer interconnection bumps 336a or the second middle layer interconnection bumps 336b Material can be including but not limited to gold, silver, copper, platinum, aluminium, it is preferable that among the first middle layer interconnection bumps 336a or second The material of layer interconnection bumps 336b can include copper.
The material of dielectric layer 344a or 344b can include high molecular film material, such as benzocyclobutene (BCB), polyamides Imines (PI) etc., but not limited to this.The material of dielectric layer 344a or 344b can also include other insulating materials.For example, can be with Circuit 345a or 345b are formed in dielectric layer 344a or 344b using rewiring (RDL) technology.In the implementation of the application In mode, the material of circuit 345a or 345b can include one of copper and aluminium.But those skilled in the art can manage Solution, the material of circuit 345a or 345b can include that other kinds of other than other metals (such as gold, silver, platinum) or metal is led Electric material.
The material of second external convex block 346a or the external convex block 346b of third can including but not limited to gold, silver, copper, platinum, Aluminium, it is preferable that the material of the second external convex block 346a or the external convex block 346b of third can include copper.
Semiconductor package 300 can also include another ACF 380, including conducting particles 381.The ACF 380 is pasted It closes on the outer surface that the second middle layer reroutes structure 342b
Semiconductor package 300 can also include third packaging body 360, which may include third The third plastic packaging material 370 of chip 361, sealing third chip 361.Third chip 361 can have third active face 362a and with Third back side 362b opposite third active face 362a.Third chip 361 may include the third positioned at third active face 362a Chip bonding pad 363, is located in the first top layer passivation layer 364 simultaneously the first top layer passivation layer 364 on third active face 362a The first top layer interconnection bumps 365 being bonded with third chip bonding pad 363.The formation surface of third plastic packaging material 370, the first top layer are blunt The outer surface for changing layer 364 and the top surface of the first top layer interconnection bumps 365 are formed in the first top layer continuous surface 371.Third encapsulates Body 360 can also include that the first top layer reroutes structure 372, be formed on the first top layer continuous surface 371.First top layer weight cloth Cable architecture 372 may include dielectric layer 374 and be electrically connected in dielectric layer 374 and with the top surface of the first top layer interconnection bumps 365 The circuit 375 connect.
Third packaging body 360 can also include the 4th external convex block 376 for being projected on the first top layer and rerouting structure 372. In presently filed embodiment, the 4th external convex block 376 can the local embedding dielectric sunk into the first top layer and reroute structure 372 Layer 374 and the circuit 375 that structure 372 is rerouted via the first top layer are electrically connected to the top surface of the first top layer interconnection bumps 365.
In presently filed embodiment, the hardness of the conducting particles 381 of ACF 380 is more than the 4th external convex block 376, when When third packaging body 360 presses to the second packaging body 330, bonded until outside the external convex block 346b and the 4th of third with ACF 380 The maximum particle diameter of conducting particles 381 of the axial clearance less than ACF 380 between convex block 376 is connect, 381 part of conducting particles is embedding Sink into the 4th external convex block 376, the 4th external convex block 376 is made to reach and the external convex block 346b of third by the conducting particles 381 Longitudinal electrical connection.
In presently filed embodiment, the hardness of conducting particles 381 can also be more than the external convex block 346b of third, thus When third packaging body 360 presses to the second packaging body 330, conducting particles 381 locally embedding can also sink into the external convex block of third 346b reduces impedance it is possible thereby to increase conductive area.
Third plastic packaging material 370 can include such as epoxy molding material (Epoxy Molding Compound, EMC), It will be recognized to those skilled in the art that other materials is also applicable.
The type of first top layer passivation layer 364 can include but is not limited to unorganic glass and organic polymer.Unorganic glass Material can be including but not limited to oxide is (for example, SiO2、Al2O3、TiO2、ZrO2、Fe2O3、SixOy), silicate (example Such as, PSG, BSG, BPSG), nitride is (for example, Si3N4、SixNyH、BN、AlN、GaN).Organic macromolecule material can include But it is not limited to, synthetic resin (for example, polyimide based resin, polysiloxanes resinoid), synthetic rubber are (for example, silicone rubber Glue).The material of first top layer interconnection bumps 365 can be including but not limited to gold, silver, copper, platinum, aluminium, it is preferable that the first top layer is mutual Even the material of convex block 365 can include copper.
The material of dielectric layer 374 can include high molecular film material, such as benzocyclobutene (BCB), polyimides (PI) etc., but not limited to this.The material of dielectric layer 374 can also include other insulating materials.For example, rewiring may be used (RDL) technology forms circuit 375 in dielectric layer 374.In the embodiment of the application, the material of circuit 375 can be with Including one of copper and aluminium.But it will be understood by those skilled in the art that the material of circuit 375 can include other metals Other kinds of conductive material other than (such as gold, silver, platinum) or metal.
The material of 4th external convex block 376 can be including but not limited to gold, silver, copper, platinum, aluminium, it is preferable that the 4th is external convex The material of block 376 can include copper.
In the embodiment illustrated in fig. 3, it can use a plurality of ways to be formed external convex block (for example, first is external convex Block 312, the second external convex block 346a, the external convex block 346b of third, the 4th external convex block 376).It is with the first external convex block 312 Example can pass through the one external convex block of growth regulation on the outer surface that the second bottom reroutes structure 352b in one example 312, plastic packaging then is carried out to the first external convex block 312 of growth.In another example, it can reroute and tie in the second bottom It makes cavity on structure 352b by lithography, and (such as electro-coppering) is electroplated in the cavities to form the first external convex block 312.Art technology Personnel are appreciated that other the well known feasible patterns for being used to form the first external convex block 312 also belong to scope of the present application. In presently filed embodiment, the method similar with the first external convex block 312 is formed can be used to form other external convex blocks, Such as the second external convex block 346a, the external convex block 346b of third, the 4th external convex block 376.
Arbitrary type in first chip 313, the second chip 331, third chip 361 may include memory chip and Logic chip.The example of memory chip can include but is not limited to, random access memory (RAM).The example of RAM can wrap Include dynamic random access memory (DRAM) or static RAM (SRAM).The example of logic chip may include but It is not limited to, graphics processing unit (Graphic Processing Unit, GPU) chip, central processing unit (Central Processing Unit, CPU) chip, system level chip (System on Chip, SOC).
In presently filed embodiment, semiconductor package 300 can also include stacking intermediate package body structure. That is may include multiple second packaging bodies 330 stacked between the first packaging body 310 and third packaging body 360, second It can be pressed by ACF 380 between packaging body 330.
In presently filed embodiment, interconnection bumps can be with the junction of the external convex block of relative depature.For example, in this Shen In embodiment please, the first middle layer interconnection bumps 336a can be external convex with the first external convex block of relative depature 312 and second The junction of block 346a.
Fig. 4 A to 4D show the schematic shapes of the conducting particles of the ACF according to presently filed embodiment.Reference chart 4A to 4D, the shape of conducting particles (for example, 121,221,321,381) may include spherical shape, the taper bodily form, cube shaped, more Any one in the bodily form of angle.In presently filed embodiment, the grain size of conducting particles can be less than 5 microns and be metal material Matter (for example, copper).In addition, the thickness of ACF can be less than 30 microns.
Fig. 5 A to Fig. 5 H show the method for manufacturing semiconductor package of the embodiment according to the application The schematic diagram of the structure obtained after executing each step.This method may comprise steps of.
With reference to figure 5A, the first packaging body 310 is provided.First packaging body 310 can be attached on a carrier 510.It should Carrier 510 may, for example, be glass carrier.Such as a hot degumming 520 can be attached on carrier 510, in the hot degumming 520 Attach the first packaging body 310.It may include that first packaging body 310, which can have the first mounting surface 311, the first packaging body 310, One chip 313, the first plastic packaging material 350 for sealing the first chip 313 and the first external convex block positioned at the first mounting surface 311 312.First chip 313 can have the first active face 314a and first back side 314b opposite with the first active face 314a, the One chip 313 may include the first chip bonding pad 315 positioned at the first active face 314a.
With reference to figure 5B, anisotropic conductive film (ACF) 320 is fitted on the first mounting surface 311, which can wrap Containing conducting particles 321.
With reference to figure 5C, the second packaging body 330 is provided.Second packaging body 330 may include the second chip 331, sealing second Second plastic packaging material 340 of chip 331, the first middle layer for being covered in the second plastic packaging material 340 reroute structure 342a and protrusion The second external convex block 346a of structure 342a is rerouted in the first middle layer.Second chip 331 can have the second active face 332 Second back side 333 opposite with the second active face 332.Second chip 331 may include positioned at the second of the second active face 332 Chip bonding pad 334, the first middle layer passivation layer 335a on the second active face 332 and be located at the first middle layer passivation layer The first middle layer interconnection bumps 336a being bonded in 335a and with the second chip bonding pad 334.The formation table of second plastic packaging material 340 Face, the outer surface of the first middle layer passivation layer 335a and the top surface of the first middle layer interconnection bumps 336a are formed in the first middle layer Continuous surface 341a.First middle layer reroutes structure 342a and is formed on the first middle layer continuous surface 341a.Second is external Locally embedding first middle layer of sinking into reroutes the dielectric layer 344a of structure 342a and is rerouted via the first middle layer convex block 346a The circuit 345a of structure 342a is electrically connected to the top surface of the first middle layer interconnection bumps 336a.
With reference to figure 5D, the second packaging body 330 is pressed into the first packaging body 310.Second packaging body 330 presses to the first envelope Temperature when filling body 310 can be less than 200 DEG C.The hardness of conducting particles 321 is more than the second external convex block 346a.When the second encapsulation When body 330 presses to the first packaging body 310, bonded until the first external convex block 312 and the second external convex block 346a with ACF 320 Between axial clearance be less than the maximum particle diameter of conducting particles 321, the part of conducting particles 321 is embedding to sink into the second external convex block 346a, make the second external convex block 346a pass through conducting particles 321 reach with the first external convex block 312 longitudinal direction be electrically connected.
Second packaging body 330 can also include that the second middle layer reroutes structure 342b and is projected on the second middle layer weight The external convex block 346b of third of wire structures 342b.With reference to figure 5E, another ACF 380 is fitted in the second middle layer and reroutes knot On the outer surface of structure 342b, which includes conducting particles 381.
With reference to figure 5F, third packaging body 360 is provided.Third packaging body 360 may include third chip 361, sealing third The third plastic packaging material 370 and the 4th external convex block 376 of chip 361.Third chip 361 can have third active face 362a, Third chip 361 may include the third chip bonding pad 363 positioned at third active face 362a.
With reference to figure 5G, third packaging body 360 is pressed into the second packaging body 330.Third packaging body 360 presses to the second envelope Temperature when filling body 330 can be less than 200 DEG C.The hardness of the conducting particles 381 of ACF 380 is more than the 4th external convex block 376, when When third packaging body 360 presses to the second packaging body 330, bonded until the external convex block 346b and the 4th of third with ACF 380 The maximum particle diameter of conducting particles 381 of the axial clearance less than ACF 380 between external convex block 376,381 part of conducting particles It is embedding to sink into the 4th external convex block 376, so that the 4th external convex block 376 is reached and the external convex block of third by the conducting particles 381 Longitudinal electrical connection of 346b.
Carrier of separating 510.Such as first packaging body 310 can be detached with carrier 510 by heating hot degumming 520.
First chip 313 can also include the first bottom passivation layer 316a being located on the first active face 314a, be located at the The first bottom interconnection bumps 317a for be bonded in one bottom passivation layer 316a and with the first chip bonding pad 315, positioned at first back side The second bottom passivation layer 316b on 314b and in the second bottom passivation layer 316b and pass through silicon hole 318 and the first core The second bottom interconnection bumps 317b that piece pad 315 is electrically connected.
First plastic packaging material 350 forms surface, the outer surface of the first bottom passivation layer 316a and the first bottom interconnection bumps The top surface of 317a is formed in the first bottom continuous surface 351a.First packaging body 310 can also include that the first bottom reroutes knot Structure 352a is formed on the first bottom continuous surface 351a.First bottom reroute structure 352a can have dielectric layer 354a, The terminal pad 356 being formed on the outer surface 353 of dielectric layer 354a and the simultaneously electric connection terminal weldering in dielectric layer 354a The circuit 355a of disk 356 and the first bottom interconnection bumps 317a.
With reference to figure 5H, the plant of soldered ball 357 is connected to terminal pad 356.
In presently filed embodiment, this method can also be included in before pressing third packaging body 360 in the first envelope The second packaging body 330 of multiple stackings is pressed on dress body 310.That is, in the first packaging body 310 and third packaging body 360 Between can also pass through 380 keys of ACF with the second packaging body 330 of multiple vertical stacks, between the second packaging body 330 It closes.
Method shown in Fig. 5 A to 5H can be used for manufacturing the semiconductor package 300 shown in Fig. 3.People in the art Member it is appreciated that method similar with the method shown in Fig. 5 A to 5H can be used manufacture Fig. 1 or Fig. 2 shows semiconductor package Fill 100 or 200.
Fig. 6 A to Fig. 6 I are shown according to the embodiment of the application for manufacture the packaging body with bilayer RDL The schematic diagram for the structure that method obtains after executing each step.This method may comprise steps of：
The first passivation layer is formed on the back side of chip, is formed with the first metal coupling in first passivation layer, this first Metal coupling is electrically connected by silicon hole with the chip bonding pad of the active face positioned at chip；
The second passivation layer is formed on the active face of chip, and be bonded with chip bonding pad is formed in second passivation layer Two metal couplings；
Use plastic packaging material encapsulating chip, the first passivation layer and the second passivation layer；
Back planarization is carried out to expose the first metal coupling to plastic packaging material, wherein the package surface of plastic packaging material, first blunt The top surface of the outer surface and the first metal coupling of changing layer is formed in the first continuous surface, the formation surface of plastic packaging material, second blunt The top surface of the outer surface and the second metal coupling of changing layer is formed in the second continuous surface；
First is formed on the first continuous surface and reroutes structure, which includes the first dielectric layer and position In the first line being electrically connected in the first dielectric layer and with the first metal coupling；
Second is formed on the second continuous surface and reroutes structure, which includes the second dielectric layer and position In the second circuit being electrically connected in the second dielectric layer and with the second metal coupling；And
The external convex block being electrically connected with the second circuit is formed in the second rewiring structure.Optionally, the external convex block is prominent The outer surface for rerouting structure for second.
Optionally, the second metal coupling of the laterally opposed deviation of external convex block.
Optionally, another external convex block being electrically connected with first line is formed in the first rewiring structure.Optionally, should Another external convex block protrudes from the outer surface of the first rewiring structure.
Optionally, the material of the first metal coupling or the second metal coupling can including but not limited to gold, silver, copper, platinum, Aluminium, it is preferable that the material of the first metal coupling or the second metal coupling can include copper.
Optionally, the material of external convex block can be including but not limited to gold, silver, copper, platinum, aluminium, it is preferable that external convex block Material can include copper.
Specifically, with reference to figure 6A, first vector 611 is provided, the active face 621a of chip 620 is attached to first vector On 611.It may include position that chip 620, which can have active face 621a and the back side 621b opposite with active face 621a, chip 620, In the chip bonding pad 622 of active face 621a, and the silicon hole 623 that is electrically connected with chip bonding pad 622.It specifically, can be The first hot degumming 612 is attached on one carrier 611, and the active face 621a of chip 620 is attached in the first hot degumming 612.At this Can be that the full wafer wafer including chip is attached in first vector 611 in step.
With reference to figure 6B, the first passivation layer 624 is formed on the back side 621b of chip 620, is formed in first passivation layer 624 There is the first metal coupling 625 being electrically connected with chip bonding pad 622 by silicon hole 623.It specifically, can be in the first passivation layer It makes cavity on 624 by lithography, (such as electro-coppering) is then electroplated in the cavities to form the first metal coupling 625.Optionally, in electricity The first metal coupling 625 of formation can also be polished after plating.
With reference to figure 6C, chip 620 is detached with first vector 611.Such as it can be by heating the first hot degumming 612 by core Piece 620 is detached with first vector 611.Chip 620 is overturn and is attached on Second support 613.For example, can be in Second support The second hot degumming 614 is attached on 613, and the outer surface of the first passivation layer 624 is then attached into the second hot degumming 614.
With reference to figure 6D, the second passivation layer 626 is formed on the active face 621a of chip 620, shape in second passivation layer 626 Second metal coupling 627 of the top surface bonding of Cheng Youyu chip bonding pads 622.It specifically, can the photoetching on the second passivation layer 626 Go out cavity, is then electroplated in the cavities to form the second metal coupling 627.It optionally, after plating can also be to formation Second metal coupling 627 is polished.
Wafer is cut to obtain chip 620, and chip 620 is detached with Second support 613.
With reference to figure 6E, third carrier 615 is provided, the outer surface of the second passivation layer 626 of chip 620, which is attached to third, to be carried Body 615.Specifically, known good chip (KGD) can be selected from the chip 620 being cut into, and attached on third carrier 615 Then the hot degumming 616 of third attaches to the outer surface of the second passivation layer 626 of chip 620 in the hot degumming of third 616.
Chip 620 is packaged using plastic packaging material 628.For example, 628 encapsulating chip 620 of plastic packaging material, the first passivation layer 624 and second passivation layer 626.Plastic packaging material 628 can include such as epoxy molding material (Epoxy Molding Compound, EMC), it will be recognized to those skilled in the art that other materials is also applicable.
With reference to figure 6F, back planarization (such as backgrind) is carried out to plastic packaging material 628, to expose the first metal coupling 625.The top surface of the package surface of plastic packaging material 628, the outer surface of the first passivation layer 624 and the first metal coupling 625 is formed in First continuous surface 629.
With reference to figure 6G, the first rewiring structure 630 is formed on the first continuous surface 629.It is, for example, possible to use RDL skills Art forms the first rewiring structure 630.First rewiring structure 630 may include the first dielectric layer 631 and be located at first The first line 632 being electrically connected in dielectric layer 631 and with the top surface of the first metal coupling 625.
With reference to figure 6H, the 4th carrier 617, separation third carrier 615 are provided, turning-over of chip 620 reroutes structure by first 630 outer surface attaches on the 4th carrier 617.For example, third carrier can be detached by heating the hot degumming of third 616 615.For another example the 4th hot degumming 618 can be attached on the 4th carrier 617, the appearance for then rerouting structure 630 by first Face paste is attached in the 4th hot degumming 618.
Formation surface, the outer surface of the second passivation layer 626 and the top surface shape of the second metal coupling 627 of plastic packaging material 628 At in the second continuous surface 633.Second is formed on the second continuous surface 633 reroutes structure 634.It is, for example, possible to use RDL Technology forms the second rewiring structure 634.Second rewiring structure 634 may include the second dielectric layer 635 and positioned at the The second circuit 636 being electrically connected in two dielectric layers 635 and with the top surface of the second metal coupling 627.
The external convex block 637 being electrically connected with the second circuit 636 is formed in the second rewiring structure 634.External convex block 637 The outer surface of the second rewiring structure 634 can be protruded from.It can use a plurality of ways to form external convex block 637.At one It, can be by growing external convex block 637 on the outer surface of the second rewiring structure 634, then to the external of growth in example Convex block 637 carries out plastic packaging.In another example, cavity can be made by lithography in the second rewiring structure 634, and in the cavities It is electroplated to form external convex block 637.It will be understood by those skilled in the art that being used to form well known to other of external convex block 637 Feasible pattern also belongs to scope of the present application.
With reference to figure 6I, the 4th carrier 617 is detached, to obtain the packaging body with bilayer RDL.
Optionally, this method can also include：It is rerouted first and forms other external convex block in structure 630.Its shape Same or similar with the mode that forms external convex block 637 at mode, details are not described herein again.
Carrier in the above embodiment can include but is not limited to glass carrier.
Although having used hot degumming in the above-described embodiment, it will be recognized to those skilled in the art that can also Use the other kinds of glue that packaging body can be detached from the carrier under certain condition, such as photoresist.
Crystal wafer chip dimension encapsulation (Wafer is can be applied to according to the semiconductor package of the application embodiment Level Chip Size Package, WLCSP) in, it is especially fanned out in formula (Fan-out) WLCSP (FOWLCSP).
According to the semiconductor package that presently filed embodiment provides, vertical stack is completed by wafer bonding, with The mode of chip placed side by side, which is compared, can increase handling capacity, and reduce the area after encapsulation.In addition, be bonded by using ACF, Compared with welding, it is possible to reduce the thickness of each packaging body interlayer.
The preferred embodiment of the application is described in detail above in association with attached drawing, still, the application is not limited to above-mentioned reality The detail in mode is applied, in the range of the technology design of the application, a variety of letters can be carried out to the technical solution of the application Monotropic type, these simple variants belong to the protection domain of the application.
It is further to note that specific technical features described in the above specific embodiments, in not lance In the case of shield, it can be combined by any suitable means.In order to avoid unnecessary repetition, the application to it is various can The combination of energy no longer separately illustrates.
In addition, arbitrary combination can also be carried out between a variety of different embodiments of the application, as long as it is without prejudice to originally The thought of application equally should be considered as content disclosed in the present application.

Claims (15)

1. a kind of semiconductor package, which is characterized in that including：
First packaging body, has the first mounting surface, first packaging body include the first chip, sealing first chip the One plastic packaging material and the first external convex block positioned at first mounting surface, first chip have the first active face and with institute The first opposite back side of the first active face is stated, first chip includes the first chip bonding pad positioned at first active face；
First anisotropic conductive film, including conducting particles, first anisotropic conductive film is fitted on first mounting surface；
Second packaging body, including the second plastic packaging material of the second chip, sealing second chip, it is covered in second plastic packaging material The first middle layer reroute structure and be projected on the second external convex block that first middle layer reroutes structure, described the It includes positioned at described that two chips, which have the second active face and second back side opposite with second active face, second chip, Second chip bonding pad of the second active face, the first middle layer passivation layer on second active face and positioned at described the The first middle layer interconnection bumps being bonded in one middle layer passivation layer and with second chip bonding pad, second plastic packaging material It forms surface, the outer surface of the first middle layer passivation layer and the top surface of the first middle layer interconnection bumps and is formed in first Middle layer continuous surface；First middle layer reroutes structure and is formed on the first middle layer continuous surface, and described the Two external convex blocks are locally embedding to sink into first middle layer and reroutes the dielectric layer of structure and via first middle layer weight cloth The first line of cable architecture is electrically connected to the top surface of the first middle layer interconnection bumps；
Wherein, the hardness of the conducting particles is more than the described second external convex block, when second packaging body presses to described the One packaging body and with first anisotropic conductive film bonding until the described first external convex block and the described second external convex block it Between axial clearance be less than the maximum particle diameter of the conducting particles, the conducting particles is locally embedding, and to sink into described second external convex Block, make the described second external convex block pass through the conducting particles reach with the described first external convex block longitudinal direction be electrically connected.
2. semiconductor package according to claim 1, which is characterized in that the hardness of the conducting particles is also more than institute State the first external convex block.
3. semiconductor package according to claim 1, which is characterized in that the first middle layer interconnection bumps are opposite Deviate the junction of the described first external convex block and the second external convex block.
4. semiconductor package according to claim 1, which is characterized in that the shape of the conducting particles includes ball Shape, the taper bodily form, cube shaped, any one in the polygonal bodily form.
5. semiconductor package according to claim 1, which is characterized in that it is micro- that the grain size of the conducting particles is less than 5 Rice and be metal material.
6. semiconductor package according to claim 1, which is characterized in that second packaging body further includes in second Interbed reroutes structure and is projected on the external convex block of third that second middle layer reroutes structure；Second chip is also Include the second middle layer passivation layer on second back side, and in the second middle layer passivation layer and passes through The second middle layer interconnection bumps that silicon hole is electrically connected with second chip bonding pad, the package surface of second plastic packaging material, The outer surface of the second middle layer passivation layer and the top surface of the second middle layer interconnection bumps are formed in the second middle layer company Continued face；Second middle layer reroutes structure and is formed on the second middle layer continuous surface, and the third is external convex Block is locally embedding to sink into second middle layer and reroutes the dielectric layer of structure and reroute structure via second middle layer Second circuit is electrically connected to the top surface of the second middle layer interconnection bumps.
7. semiconductor package according to claim 1, which is characterized in that first packaging body further includes：First Bottom reroutes structure and the second bottom reroutes structure；
First chip further include be located at first active face on the first bottom passivation layer, be located at first bottom it is blunt Change the first bottom interconnection bumps, the second bottom on first back side being bonded in layer and with first chip bonding pad Passivation layer and be electrically connected with first chip bonding pad in the second bottom passivation layer and by silicon hole second Bottom interconnection bumps；
First plastic packaging material forms surface, the outer surface of the first bottom passivation layer and the first bottom interconnection bumps Top surface be formed in the first bottom continuous surface；First bottom reroutes structure and is formed in the first bottom continuous surface On, first bottom, which reroutes structure, to be had dielectric layer, the terminal pad being formed on the outer surface of dielectric layer and is located at The dielectric layer is interior and is electrically connected the tertiary circuit of the terminal pad and the first bottom interconnection bumps；First encapsulation Body further includes planting the soldered ball for being connected to the terminal pad；
Outer surface and the second bottom interconnection bumps of the package surface of first plastic packaging material, the second bottom passivation layer Top surface be formed in the second bottom continuous surface；Second bottom reroutes structure and is formed in the second bottom continuous surface On, the first external convex block is locally embedding to sink into second bottom and reroutes the dielectric layer of structure and via second bottom The 4th circuit for rerouting structure is electrically connected to the top surface of the second bottom interconnection bumps.
8. semiconductor package according to claim 6, which is characterized in that further include：
Third packaging body, the third packaging body include the third plastic packaging material of third chip, the sealing third chip, and described the It includes positioned at described that three chips, which have third active face and the third back side opposite with the third active face, the third chip, The third chip bonding pad of third active face, the first top layer passivation layer on the third active face are located at first top The first top layer interconnection bumps being bonded in layer passivation layer and with the third chip bonding pad；The formation table of the third plastic packaging material Face, the outer surface of the first top layer passivation layer and the top surface of the first top layer interconnection bumps are formed in the continuous table of the first top layer Face；The third packaging body further includes that the first top layer reroutes structure, is formed on the first top layer continuous surface；
Be projected on the 4th external convex block that first top layer reroutes structure, the 4th external convex block locally it is embedding sink into it is described First top layer reroutes the dielectric layer of structure and is electrically connected to via the 5th circuit of first top layer rewiring structure described The top surface of first top layer interconnection bumps；And
Second anisotropic conductive film, including conducting particles, second anisotropic conductive film are fitted in second middle layer On the outer surface for rerouting structure；
Wherein, the hardness of the conducting particles of second anisotropic conductive film is more than the 4th external convex block, when the third Packaging body press to second packaging body and with second anisotropic conductive film bonding until the external convex block of the third with Axial clearance between the 4th external convex block is less than the maximum particle diameter of the conducting particles of second anisotropic conductive film, should Conducting particles is locally embedding to sink into the 4th external convex block, make the 4th external convex block pass through the conducting particles reach with it is described Longitudinal electrical connection of the external convex block of third.
9. semiconductor package according to claim 8, which is characterized in that second packaging body includes multiple longitudinal directions The packaging body of stacking, two neighboring packaging body are bonded by anisotropic conductive film.
10. a kind of method for manufacturing semiconductor package, which is characterized in that this method includes：
The first packaging body is provided, it includes the first chip, sealing first chip to have the first mounting surface, first packaging body The first plastic packaging material and the first external convex block positioned at first mounting surface, first chip have the first active face and First back side opposite with first active face, first chip include the first chip weldering positioned at first active face Disk；
Anisotropic conductive film is fitted on first mounting surface, the anisotropic conductive film includes conducting particles；
Second packaging body is provided, including the second plastic packaging material of the second chip, sealing second chip, is covered in second modeling First middle layer of envelope material reroutes structure and is projected on the second external convex block that first middle layer reroutes structure, institute It includes being located to state the second chip to have the second active face and second back side opposite with second active face, second chip Second chip bonding pad of second active face, the first middle layer passivation layer on second active face and be located at institute State the first middle layer interconnection bumps being bonded in the first middle layer passivation layer and with second chip bonding pad, second plastic packaging The formation surface of material, the outer surface of the first middle layer passivation layer and the top surface of the first middle layer interconnection bumps are formed in First middle layer continuous surface；First middle layer reroutes structure and is formed on the first middle layer continuous surface, institute State that the second external convex block is locally embedding to sink into first middle layer and reroute the dielectric layer of structure and via first middle layer The first line for rerouting structure is electrically connected to the top surface of the first middle layer interconnection bumps；
Second packaging body is pressed into first packaging body, wherein the hardness of the conducting particles is more than described second External convex block, when second packaging body presses to first packaging body and is bonded until described with the anisotropic conductive film Axial clearance between first external convex block and the second external convex block is less than the maximum particle diameter of the conducting particles, described to lead Charged particle is locally embedding to sink into the described second external convex block, make the described second external convex block pass through the conducting particles reach with it is described Longitudinal electrical connection of first external convex block.
11. according to the method described in claim 10, it is characterized in that, second packaging body further includes the second middle layer weight cloth Cable architecture and the external convex block of third for being projected on the second middle layer rewiring structure, the method further include：
Second anisotropic conductive film is fitted in second middle layer to reroute on the outer surface of structure, second anisotropy Conductive film includes conducting particles；
Third packaging body is provided, the third packaging body include third chip, the sealing third chip third plastic packaging material with And the 4th external convex block, it includes being located at the third active face that the third chip, which has third active face, the third chip, Third chip bonding pad；And
The third packaging body is pressed into second packaging body, wherein the conducting particles of second anisotropic conductive film Hardness be more than the 4th external convex block, when the third packaging body press to second packaging body and with described second it is different The bonding of side's property conductive film is until the axial clearance between the external convex block of the third and the 4th external convex block is less than described the The maximum particle diameter of the conducting particles of two anisotropic conductive films, the conducting particles is locally embedding to sink into the 4th external convex block, makes institute State the 4th external convex block by the conducting particles reach with the external convex block of the third longitudinal direction be electrically connected.
12. according to the method for claim 11, further including：
Multiple second packaging bodies, the multiple second packaging body are pressed between first packaging body and the third packaging body Between be bonded by anisotropic conductive film.
13. according to the method described in claim 10, it is characterized in that, the hardness of the conducting particles is also more than outside described first Connect convex block.
14. according to the method described in claim 10, it is characterized in that, described in the first middle layer interconnection bumps relative depature The junction of first external convex block and the second external convex block.
15. according to the method described in claim 10, it is characterized in that, the grain size of the conducting particles is less than 5 microns and is golden Belong to material.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110619817A (en) * 2019-08-27 2019-12-27 武汉华星光电半导体显示技术有限公司 Anisotropic conductive adhesive, display panel and substrate binding method
CN111095552A (en) * 2019-08-15 2020-05-01 深圳市汇顶科技股份有限公司 Chip interconnection structure, chip and chip interconnection method

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040191955A1 (en) * 2002-11-15 2004-09-30 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same
KR20050079399A (en) * 2004-02-05 2005-08-10 삼성전자주식회사 Anisotropic conductive film and bump, and packaging structure of semiconductor having the same
US20070205520A1 (en) * 2006-03-02 2007-09-06 Megica Corporation Chip package and method for fabricating the same
CN101410973A (en) * 2003-07-11 2009-04-15 快捷韩国半导体有限公司 Wafer-level chip scale package and method for fabricating and using the same
CN102738101A (en) * 2011-04-13 2012-10-17 华东科技股份有限公司 Semiconductor stereoscopic packaging structure
CN106997853A (en) * 2016-01-22 2017-08-01 美光科技公司 Package on package component and its manufacture method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040191955A1 (en) * 2002-11-15 2004-09-30 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same
CN101410973A (en) * 2003-07-11 2009-04-15 快捷韩国半导体有限公司 Wafer-level chip scale package and method for fabricating and using the same
KR20050079399A (en) * 2004-02-05 2005-08-10 삼성전자주식회사 Anisotropic conductive film and bump, and packaging structure of semiconductor having the same
US20070205520A1 (en) * 2006-03-02 2007-09-06 Megica Corporation Chip package and method for fabricating the same
CN102738101A (en) * 2011-04-13 2012-10-17 华东科技股份有限公司 Semiconductor stereoscopic packaging structure
CN106997853A (en) * 2016-01-22 2017-08-01 美光科技公司 Package on package component and its manufacture method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111095552A (en) * 2019-08-15 2020-05-01 深圳市汇顶科技股份有限公司 Chip interconnection structure, chip and chip interconnection method
WO2021026865A1 (en) * 2019-08-15 2021-02-18 深圳市汇顶科技股份有限公司 Chip interconnection structure, chips and chip interconnection method
CN110619817A (en) * 2019-08-27 2019-12-27 武汉华星光电半导体显示技术有限公司 Anisotropic conductive adhesive, display panel and substrate binding method

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