KR101411810B1 - Semiconductor device and fabricating method thereof - Google Patents

Abstract

The present invention relates to a semiconductor device capable of reducing the cost and realizing an ultra-thin semiconductor package and a method of manufacturing the same.
For example, a first encapsulation step of preparing a semiconductor die having a plurality of bond pads formed on a first surface, and encapsulating the semiconductor die with a first encapsulant to expose the first surface to the outside; A first rewiring layer forming step of forming a first rewiring layer on the first surface so as to be electrically connected to the bond pad; A solder ball attaching step of attaching a solder ball to the re-wiring layer; A second encapsulation step of encapsulating the solder ball with a second encapsulant; A first grinding step of grinding a second surface which is an opposite surface of the first surface of the semiconductor die; A second rewiring layer forming step of forming a second rewiring layer on a second surface of the ground semiconductor die so as to be electrically connected to the first rewiring layer; And a second grinding step of grinding the surface to which the solder ball is attached.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor device and a fabrication method thereof.

The present invention relates to a semiconductor device and a manufacturing method thereof.

Recently, portable electronic devices such as mobile phones and PMPs are required to be highly functional, compact, lightweight, and low in price. According to this trend, a semiconductor package mounted on a portable electronic device is being developed as a more innovative and cost competitive 3D package. As a technology of a 3D semiconductor package, a stacking technique of a semiconductor package using a through-mold electrode is used. The stacking technique of the semiconductor package using the penetrating electrode is a technology for vertically stacking a semiconductor die or a semiconductor package, and has been attracting attention as a technique capable of realizing an ultra-small semiconductor package. However, such a TMV package has a problem that it is difficult to realize a thickness of 0.3 mm or less.

The present invention provides a semiconductor device capable of reducing the cost and realizing an ultra-thin semiconductor package and a method of manufacturing the same.

A method of manufacturing a semiconductor device according to the present invention includes the steps of preparing a semiconductor die having a plurality of bond pads formed on a first surface thereof and encapsulating the semiconductor die with a first encapsulant to expose the first surface to the outside, 1 encapsulation phase; A first rewiring layer forming step of forming a first rewiring layer on the first surface so as to be electrically connected to the bond pad; A solder ball attaching step of attaching a solder ball to the re-wiring layer; A second encapsulation step of encapsulating the solder ball with a second encapsulant; A first grinding step of grinding a second surface which is an opposite surface of the first surface of the semiconductor die; A second rewiring layer forming step of forming a second rewiring layer on a second surface of the ground semiconductor die so as to be electrically connected to the first rewiring layer; And a second grinding step of grinding the surface to which the solder ball is attached.

Also, in the first re-distribution layer formation step, a first passivation layer is formed on the first surface of the semiconductor die so as to expose a part of the plurality of bond pads to the outside, and a part of the first re- A second passivation layer may be formed on the first passivation layer.

The first rewiring layer may be formed on an upper surface of the first passivation layer and electrically connected to the bond pad.

In the second encapsulation step, the upper surface of the second passivation layer may be encapsulated with a second encapsulant.

In the first grinding step, the semiconductor die and a part of the first encapsulant may be ground.

In the second rewiring layer forming step, a third passivation layer is formed on a second surface of the ground semiconductor die, and a fourth passivation layer is formed on the third passivation layer to expose a part of the second rewiring layer to the outside. Layer can be formed.

The second redistribution layer may be formed on an upper surface of the third passivation layer and electrically connected to the first redistribution layer.

In addition, in the rewiring layer forming step, a part of the first rewiring layer may be exposed to the outside by etching a part of the third passivation layer, the first encapsulant, and the second passivation layer.

In the second grinding step, a part of the solder ball and the second encapsulant may be ground.

In addition, the present invention is characterized by including a semiconductor device manufactured by the above-described method.

A method of manufacturing a semiconductor device according to the present invention includes the steps of preparing a semiconductor die having a plurality of bond pads formed on a first surface thereof and encapsulating the semiconductor die into an encapsulant so as to expose the first surface to the outside, Encapsulation step; Forming a first passivation layer on a first surface of the semiconductor die and forming a first opening to expose a portion of the bond pad and a first passivation layer to form a via in the first encapsulant; Forming a penetrating electrode by filling the through via with a conductive material; A re-wiring layer forming step of forming a re-wiring layer electrically connecting the bond pad and the penetrating electrode; A second passivation layer forming step of forming a second passivation layer on the first passivation layer so as to cover the redistribution layer and forming a second opening exposing a part of the redistribution layer; Grinding the encapsulant to expose the penetrating electrode to the outside; And a solder ball attaching step of attaching a solder ball to the penetrating electrode.

The height of the penetrating electrode may be higher than the height of the semiconductor die.

Further, the penetrating electrode may be formed on the outer periphery of the semiconductor die.

In the forming of the first passivation layer, the first opening may be formed by etching a first passivation layer formed on the bond pad, the through via may include a first passivation layer formed on the outer periphery of the semiconductor die, As shown in FIG.

In the penetrating electrode forming step, the seed layer may be formed on the first passivation layer before forming the penetrating electrode.

In addition, in the solder ball attaching step, the side surface of the penetrating electrode can be etched.

In the grinding step, the encapsulant may be ground so as to be flush with a second surface of the semiconductor die opposite to the first surface.

In addition, the present invention is characterized by including a semiconductor device manufactured by the above-described method.

The semiconductor device and the method of manufacturing the same according to an embodiment of the present invention can reduce the overall size of the semiconductor device by grinding the semiconductor die and the solder ball, thereby reducing the cost and drastically improving the process yield.

In addition, the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention can improve the warp page performance since a relatively symmetrical structure is possible based on the semiconductor die.

1 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
3 is a flowchart showing a method of manufacturing a semiconductor device according to another embodiment of the present invention.
4A to 4I are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.
5 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention.

1 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. 2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, a method of manufacturing a semiconductor device according to an embodiment of the present invention includes a first encapsulation step S1, a first rewiring layer formation step S2, a solder ball attaching step S3, An encapsulation step S4, a first grinding step S5, a second rewiring layer forming step S6 and a second grinding step S7. Hereinafter, each step of FIG. 1 will be described with reference to FIGS. 2A to 2F.

The first encapsulation step S1 is a step of encapsulating the semiconductor die 110 into the first encapsulant 120.

Referring to FIG. 2A, in the first encapsulation step S1, a semiconductor die 110, which is basically made of a silicon material and in which a plurality of semiconductor elements are formed, is prepared. The semiconductor die 110 has a flat first surface 110a and a second flat surface 110b as a surface opposite to the first surface 110a. The first surface 110a has a plurality of bond pads 111 Is formed. Next, the first surface 110a of the semiconductor die 110 is attached to the adhesive film 10, and the semiconductor die 110 is encapsulated with the first encapsulant 120. Next, Accordingly, the semiconductor die 110 is encapsulated with the first encapsulant 120 in a plane other than the first plane 110a on which the bond pad 111 is formed. The first encapsulant 120 may be formed of an epoxy-based resin.

The first rewiring layer forming step S2 is a step of forming a first rewiring layer 130 on the first surface 110a of the semiconductor die 110. [

Referring to FIG. 2B, in the first rewiring layer forming step S2, the adhesive film 10 is removed and a first passivation layer 131 is formed on the first surface 110a of the semiconductor die 110 . In addition, the first passivation layer 131 may expose a part of the bond pad 111 to the outside. Next, a first redistribution layer 130 is formed on the first passivation layer 131. The first redistribution layer 130 may be electrically connected to the bond pad 111 and extend to the outer periphery of the semiconductor die 110. The first rewiring layer 130 may be formed of any one selected from among copper (Cu), titanium (Ti), nickel (Ni), palladium (Pd), and the like. Finally, a second passivation layer 132 is formed on the first passivation layer 131 to cover the first redistribution layer 130. The second passivation layer 132 may expose a portion of the first rewiring layer 130 extending to the outer periphery of the semiconductor die 110 to the outside. The first passivation layer 131 and the second passivation layer 132 may be formed of conventional polyimide, epoxy, BCB (Benzo Cyclo Butene), PBO (Poly Benz Oxazole), oxide film, Or equivalents thereof.

The solder ball attaching step S3 is a step of attaching the solder ball 140 to the first redistribution layer 130.

Referring to FIG. 2B, in the solder ball attaching step S3, the solder ball 140 is attached to the first rewiring layer 130 exposed to the outside by the second passivation layer 132. FIG. Accordingly, the solder ball 140 is electrically connected to the first redistribution layer 130 and may be formed on the outer periphery of the semiconductor die 110. The solder ball 140 may be formed of any one selected from tin / lead, lead-free tin and its equivalent.

The second encapsulation step S4 is a step of encapsulating the solder ball 140 into the second encapsulant 150.

Referring to FIG. 2C, in the second encapsulation step S4, a solder ball 140 electrically connected to the first rewiring layer 130 formed on the first surface 110a of the semiconductor die 110 is formed in the second Encapsulate 160 with encapsulation 160. Accordingly, the second encapsulant 150 is formed on the second passivation layer 132. Also, the second encapsulant 150 is formed to face the first encapsulant 120. The second encapsulant 150 may be formed of the same material as the first encapsulant 120.

The first grinding step (S5) is a step of grinding the second surface (110b) of the semiconductor die (110).

Referring to FIG. 2D, in the first grinding step S5, a grinding process for mechanically cutting the first encapsulant 120 and the second surface 110b of the semiconductor die 110 is performed. At this time, in the first grinding step (S5), the remaining portion except the active region of the portion where the bond pad 111 is formed on the first surface 110a of the semiconductor die 110 is ground. Accordingly, since the thickness of the semiconductor die 110 'is reduced, the size of the entire semiconductor device can be reduced. The grinding process can be carried out using, for example, a diamond grinder, but the grinding process is not limited thereto.

The second rewiring layer forming step S6 is a step of forming a second rewiring layer 160 on the second surface 110b 'of the ground semiconductor die 110'.

Referring to FIG. 2E, a third passivation layer 161 is formed on the second surface 110b 'of the semiconductor die 110' in the second rewiring layer forming step S6. Also, the third passivation layer 161 may expose a part of the first redistribution layer 130 to the outside. Specifically, a third passivation layer 161 is formed on the second surface 110b 'of the semiconductor die 110', and then a first passivation layer 161 is formed on the upper portion of the portion where the first redistribution layer 130 is formed. The first passivation layer 131, the encapsulant 120 'and the third passivation layer 161 may be etched to expose the first redistribution layer 130 to the outside. Next, a second redistribution layer 160 is formed on the third passivation layer 161. The second redistribution layer 160 is electrically connected to the first redistribution layer 130 and may extend to the outer periphery of the semiconductor die 110 '. The second rewiring layer 160 may be formed of any one selected from copper (Cu), titanium (Ti), nickel (Ni), palladium (Pd), and the like. Finally, a fourth passivation layer 162 is formed on the third passivation layer 161 to cover the second redistribution layer 160. In addition, the fourth passivation layer 162 may expose a part of the second rewiring layer 160 extending to the outer periphery of the semiconductor die 110 'to the outside. The third passivation layer 161 and the fourth passivation layer 162 may be formed of conventional polyimide, epoxy, BCB (Benzo Cyclo Butene), PBO (Poly Benz Oxazole), oxide film, Or equivalents thereof.

The second grinding step S7 is a step of grinding the surface to which the solder ball 140 is attached.

Referring to FIG. 2F, in the second grinding step S7, a grinding process for mechanically cutting the second encapsulant 150 and the solder ball 140 is performed. At this time, in the second grinding step S7, only a part of the solder ball 140 is ground for electrical connection between the semiconductor die 110 'and the external circuit. Further, the degree of grinding can be adjusted according to the size of a desired semiconductor device. Since the size of the solder ball 140 'is reduced, the size of the entire semiconductor device can be reduced. The grinding process can be carried out using, for example, a diamond grinder, but the grinding process is not limited thereto.

The semiconductor device 100 formed in the above-described manner includes a semiconductor die 110 ', a first encapsulant 120' that encapsulates the semiconductor die 110 ', a first encapsulant 120' A first rewiring layer 130 formed on a first surface 110a of the semiconductor die 110 'and a second rewiring layer 130 formed on a second surface 110b' of the semiconductor die 110 'and electrically connected to the first rewiring layer 130 160, a solder ball 140 'attached to the first rewiring layer 130, and a second encapsulant 150' encapsulating the solder ball 140 '.

Since the semiconductor device 100 can reduce the overall size of the semiconductor device 100 by grinding the semiconductor die 110 'and the solder ball 140', the cost can be reduced and the process yield can be dramatically reduced .

In addition, since the semiconductor device 100 has a relatively symmetrical structure with respect to the semiconductor die 100 ', the warpage performance can be improved.

Next, a method of manufacturing a semiconductor device according to another embodiment of the present invention will be described.

3 is a flowchart showing a method of manufacturing a semiconductor device according to another embodiment of the present invention. 4A to 4I are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention. 5 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

3, a method of fabricating a semiconductor device according to another embodiment of the present invention includes an encapsulation step S11, a first passivation layer forming step S12, a penetrating electrode forming step S13, (S14), a second passivation layer forming step (S15), a grinding step (S16), and a solder ball attaching step (S17). Hereinafter, the respective steps of FIG. 3 will be described with reference to FIGS. 4A to 4I.

The encapsulation step S11 is a step of encapsulating the semiconductor die 210 into the encapsulant 220.

Referring to FIG. 4A, in the encapsulation step S11, a semiconductor die 210, which is basically made of a silicon material and in which a plurality of semiconductor elements are formed, is prepared. The semiconductor die 210 has a flat first surface 210a and a second flat surface 210b which is opposite to the first surface 210a and the first surface 210a has a plurality of bond pads 211 Is formed. Next, the first surface 210a of the semiconductor die 210 is attached to the adhesive film 10, and the semiconductor die 210 is encapsulated with encapsulant 220. Therefore, the semiconductor die 210 is encapsulated with the encapsulant 220, except for the first surface 210a on which the bond pad 211 is formed. The encapsulant 220 may be formed of an epoxy-based resin.

The first passivation layer forming step S12 is a step of forming a first passivation layer 230 on the first surface 210a of the semiconductor die 210. [

Referring to FIG. 4B, in the first passivation layer forming step S12, the adhesive film 10 is first removed and a first passivation layer 230 is formed on the first surface 210a of the semiconductor die 210 . The first passivation layer 230 may be formed of any one selected from conventional polyimide, epoxy, BCB (Benzo Cyclo Butene), PBO (Poly Benz Oxazole), oxide film, nitride film, . Next, a part of the first passivation layer 230 is etched to form a first opening 231 and a through-hole via 232. The first opening 231 is formed by etching the first passivation layer 230 formed on the bond pad 211 of the semiconductor die 210 so that the bonding pad 211 is electrically connected to the first opening 231, Is exposed to the outside. The through vias 232 are formed in the encapsulant 220 and are located on the outer periphery of the semiconductor die 210. That is, the through vias 232 are formed by etching the first passivation layer 230 and the encapsulant 220 formed on the outer periphery of the semiconductor die 210. In addition, the height of the through vias 232 is higher than the height of the semiconductor die 210. Here, the through vias 232 may be formed by a method such as laser drilling or plasma etching.

The penetrating electrode forming step S13 is a step of forming the penetrating electrode 250 by filling the penetrating via 232 with a conductive material.

Referring to FIG. 4C, the seed layer 240 is first formed on the first surface 210a of the semiconductor die 210 in the penetrating electrode forming step S13. The seed layer 240 is formed on the first passivation layer 230 and is formed on the first opening 231 and the through vias 232. The seed layer 240 may be formed of any one material selected from among gold, silver, copper, tungsten, and the like. In addition, the seed layer 240 may be formed by a method such as sputtering. Next, a penetrating electrode 250 having the seed layer 240 is filled with a conductive material.

The re-wiring layer forming step S14 is a step of forming a re-wiring layer 260 for electrically connecting the bond pad 211 and the penetrating electrode 250. [

Referring to FIG. 4D, a re-wiring layer 260 is formed in the seed layer 240 in the re-wiring layer forming step S14. The re-distribution layer 260 is also formed on the penetrating electrode 250. The seed layer 240 is formed in the first opening 231 and the through vias 232 so that the seed layer 240 is electrically connected to the bond pad 211 located in the first opening 231 And is also electrically connected to the penetrating electrode 250 formed in the through via 232. Therefore, the re-distribution layer 260 formed on the seed layer 240 is electrically connected to both the penetrating electrode 250 and the bond pad 211.

4E, a photoresist pattern 20 is formed on the redistribution layer 260, and a portion where the photoresist pattern 20 is not formed is etched to form a seed layer 240 ' A part of the second electrode 260 'is removed. Here, the seed layer 240 'and the re-distribution layer 260' may be removed by a method such as dry etching or wet etching, and the first passivation layer 230 is exposed to the outside through the etching. Then, the photoresist pattern 20 is removed. The re-distribution layer 260 'electrically connects the bond pad 211 and the penetrating electrode 250 to each other and extends to the outer periphery of the semiconductor die 210.

The second passivation layer forming step S15 is a step of forming a second passivation layer 270 on the first passivation layer 230 so as to cover the redistribution layer 260 '.

Referring to FIG. 4F, a second passivation layer 270 is formed on the re-routing layer 260 'and the first passivation layer 230 in the second passivation layer forming step S15. Next, a part of the second passivation layer 270 is etched to form an opening 271 exposing a part of the re-distribution layer 260 'to the outside. The opening 271 may be formed on the penetrating electrode 250. Here, the second passivation layer 270 may be formed of the same material as the first passivation layer 230.

The grinding step S16 is a step of grinding the encapsulant 220.

Referring to FIG. 4G, in the grinding step S16, a grinding process for mechanically cutting the encapsulant 220 is performed. At this time, in the grinding step S16, the encapsulant 220 is ground to expose the second surface 210b of the semiconductor die 210 and the penetrating electrode 250 to the outside. That is, the surface of the ground encapsulant 220 'may be the same surface as the second surface 210b of the semiconductor die 210. As such, by grinding the encapsulant 220 ', the size of the entire semiconductor device can be reduced. The grinding process can be carried out using, for example, a diamond grinder, but the grinding process is not limited thereto.

The solder ball attaching step S17 is a step of attaching the solder ball 270 to the penetrating electrode 250 exposed in the grinding step S16.

Referring to FIG. 4H, in the solder ball attaching step S17, the encapsulant 220 'formed on the side of the penetrating electrode 250 is etched to form a groove 221. Referring to FIG.

Next, referring to FIG. 4I, a solder ball 280 is attached to the penetrating electrode 250 to complete the semiconductor device 200. Therefore, the solder ball 280 is electrically connected to the penetrating electrode 250 and may be formed on the outer circumference of the semiconductor die 210. The solder ball 250 may be formed of any one selected from tin / lead, lead-free tin, and the like.

The semiconductor device 200 formed by the above-described method includes a semiconductor die 210 having a plurality of bond pads 211 formed on a first surface 210a, an encapsulant 220 encapsulating the semiconductor die 210 A first passivation layer 230 formed on the first surface 210a of the semiconductor die 210 and a second passivation layer 230 located on the outer periphery of the semiconductor die 210 and formed of the encapsulant 220 ' A through electrode 250 formed through the layer 230 and a rewiring layer 250 formed on the first surface 210a of the semiconductor die 210 and electrically connecting the bond pad 211 and the penetrating electrode 250 A second passivation layer 270 formed on the first passivation layer 230 and a solder ball 280 attached to the penetrating electrode 250 to partially expose the re-distribution layer 260 ' do. The semiconductor device 200 grinds the encapsulant 220 formed on the second surface 210b of the semiconductor die 210 and forms a penetrating electrode 250 formed on the outer periphery of the semiconductor die 210, And the solder ball 280 electrically connected to the penetrating electrode 250, the overall size of the semiconductor device 200 can be reduced.

Also, as shown in FIG. 5, a plurality of the semiconductor devices 200 may be stacked to form one semiconductor device 300.

It is to be understood that the present invention is not limited to the above-described embodiment, but may be embodied in various forms without departing from the spirit and scope of the invention, It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention.

100, 200, 300: semiconductor device 110, 110 ', 210: semiconductor die
120, 120 ': first encapsulant 130: first rewiring layer
140, 140 ', 280: solder ball 150, 150': second encapsulant
160: second re-wiring layer 220, 220 ': encapsulant
230: first passivation layer 240, 240 ': seed layer
250: penetrating electrode 260, 260 ': re-wiring layer
270: second passivation layer

Claims (18)

Preparing a semiconductor die having a plurality of bond pads on a first surface and encapsulating the semiconductor die with a first encapsulant to expose the first surface to the outside;
A first rewiring layer forming step of forming a first rewiring layer on the first surface so as to be electrically connected to the bond pad;
A solder ball attaching step of attaching a solder ball to the first rewiring layer;
A second encapsulation step of encapsulating the solder ball with a second encapsulant;
A first grinding step of grinding a second surface which is an opposite surface of the first surface of the semiconductor die;
A second rewiring layer formation step of forming a second rewiring layer on a second surface of the semiconductor die grounded in the first grinding step so as to be electrically connected to the first rewiring layer; And
And a second grinding step of grinding the surface to which the solder ball is attached. The method according to claim 1,
A first passivation layer is formed on a first surface of the semiconductor die so as to expose a part of the plurality of bond pads to the outside in the first re-wiring layer formation step, and a part of the first re- And forming a second passivation layer on the first passivation layer. 3. The method of claim 2,
Wherein the first rewiring layer is formed on an upper surface of the first passivation layer and is electrically connected to the bond pad. 3. The method of claim 2,
And encapsulating the upper surface of the second passivation layer with a second encapsulant in the second encapsulant step. The method according to claim 1,
And grinding a portion of the semiconductor die and the first encapsulant in the first grinding step. The method according to claim 1,
The third passivation layer is formed on the second surface of the semiconductor die grounded in the first grinding step and the second passivation layer is formed on the third passivation layer so as to expose a part of the second re- And forming a fourth passivation layer on the second passivation layer. The method according to claim 6,
Wherein the second redistribution layer is formed on an upper surface of the third passivation layer and is electrically connected to the first redistribution layer. The method according to claim 6,
Wherein a part of the third passivation layer, the first encapsulant, and the second passivation layer are etched to expose a part of the first rewiring layer to the outside in the second rewiring layer forming step . The method according to claim 1,
And grinding a part of the solder ball and the second encapsulant in the second grinding step. A semiconductor device manufactured by any one of the methods according to any one of claims 1 to 9. Preparing a semiconductor die having a plurality of bond pads formed on a first surface thereof and encapsulating the semiconductor die with an encapsulant to expose the first surface to the outside;
Forming a first passivation layer on a first surface of the semiconductor die, forming a first opening to expose a portion of the bond pad, and a first passivation layer to form a via in the encapsulant;
Forming a penetrating electrode by filling the through via with a conductive material;
A re-wiring layer forming step of forming a re-wiring layer electrically connecting the bond pad and the penetrating electrode;
A second passivation layer forming step of forming a second passivation layer on the first passivation layer so as to cover the redistribution layer and forming a second opening exposing a part of the redistribution layer;
Grinding the encapsulant to expose the penetrating electrode to the outside; And
And attaching a solder ball to the penetrating electrode. 12. The method of claim 11,
Wherein the height of the penetrating electrode is higher than the height of the semiconductor die. 12. The method of claim 11,
Wherein the penetrating electrode is formed on an outer periphery of the semiconductor die. 12. The method of claim 11,
Wherein the first passivation layer is formed by etching a first passivation layer formed on the bond pad, the passivation via including a first passivation layer formed on an outer periphery of the semiconductor die and a first passivation layer formed on the encapsulant by etching And forming a second insulating film on the semiconductor substrate. 12. The method of claim 11,
Wherein the seed layer is formed first in the first passivation layer before forming the penetrating electrode in the penetrating electrode forming step. 12. The method of claim 11,
And etching the side surface of the penetrating electrode in the solder ball attaching step. 12. The method of claim 11,
And grinding the encapsulant so that the encapsulant is flush with the second surface of the semiconductor die opposite to the first surface in the grinding step. A semiconductor device manufactured by the method according to any one of claims 11 to 17.

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