CN117594538A - Chip stacking and packaging structure and forming method thereof - Google Patents

Chip stacking and packaging structure and forming method thereof Download PDF

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Publication number
CN117594538A
CN117594538A CN202410068699.9A CN202410068699A CN117594538A CN 117594538 A CN117594538 A CN 117594538A CN 202410068699 A CN202410068699 A CN 202410068699A CN 117594538 A CN117594538 A CN 117594538A
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Prior art keywords
chip
layer
electrically connected
forming
extraction
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CN202410068699.9A
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CN117594538B (en
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徐虹
成炎炎
魏亨利
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Jiangyin Changdian Advanced Packaging Co Ltd
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Jiangyin Changdian Advanced Packaging Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3178—Coating or filling in grooves made in the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention relates to a chip stacking and packaging structure and a forming method thereof. The chip stack package structure includes: the first chip comprises a through hole penetrating through the first chip along a first direction, and the first chip further comprises a first surface and a second surface which are distributed oppositely along the first direction; a second chip stacked on the first surface of the first chip in a first direction; the extraction structure is arranged on the second surface of the first chip along the first direction, is electrically connected with the first chip, and extends into the through hole and is electrically connected with the second chip. The invention realizes the improvement of the packaging integration level, reduces the size of the packaging structure and reduces the difficulty of the manufacturing process of the packaging structure.

Description

Chip stacking and packaging structure and forming method thereof
Technical Field
The present disclosure relates to integrated circuit manufacturing, and more particularly, to a chip stacking and packaging structure and a method for forming the same.
Background
With the increasing demands of various technical industries for the integration level and electrical performance of semiconductor devices, the packaging technology also needs to be developed and innovated continuously. When a conventional 2D (two-dimensional) packaging technology is used to integrate multiple chips, for example, when a fan-out type packaging structure is used, the size of the packaging structure (for example, the volume of the packaging structure or the surface area of the packaging structure) is increased, and the application of the packaging structure in products with limitation on the size is limited. The 2.5D packaging technology is adopted to integrate the chip through the adapter plate, so that the packaging density can be effectively improved, however, the manufacturing process of the adapter plate is difficult, the cost is high, and the adapter plate is not suitable for the integration of the chip with low cost. In addition, in the 2.5D package integration process, if the package structure is ultrathin, warpage is very likely to occur in the package structure, and excessive warpage can make the package structure not be smoothly implemented in the surface welding (Surface Mounted Technology, SMT) assembly process.
Therefore, how to improve the integration level of the package structure, reduce the size of the package structure, and reduce the probability of warpage of the package structure, so as to improve the performance of the package structure is a technical problem to be solved currently.
Disclosure of Invention
The chip stacking packaging structure and the forming method thereof provided by the invention are used for reducing the size of the packaging structure and improving the performance of the packaging structure while improving the integration level of the packaging structure.
According to some embodiments, the present invention provides a chip stack package structure, including:
the first chip comprises a through hole penetrating through the first chip along a first direction, and the first chip further comprises a first surface and a second surface which are distributed oppositely along the first direction;
a second chip stacked on the first surface of the first chip in a first direction;
the extraction structure is arranged on the second surface of the first chip along the first direction, is electrically connected with the first chip, and extends into the through hole and is electrically connected with the second chip.
In some embodiments, the second chip includes a third surface opposite the first chip and a fourth surface opposite the third surface along the first direction; the chip stack package structure further includes:
and the first rewiring layer is positioned on the first surface of the first chip, and the lead-out structure extending into the through hole is electrically connected with the first rewiring layer.
In some embodiments, further comprising:
a second redistribution layer located on the third surface of the second chip, and the first redistribution layer is electrically connected with the second redistribution layer;
the first conductive bump is positioned on the surface of the first rewiring layer, which is away from the first chip, and is electrically connected with the first rewiring layer;
and the second conductive bump is positioned on the surface of the second redistribution layer, which is away from the second chip, and the first conductive bump is connected with the second conductive bump.
In some embodiments, further comprising:
and a first adhesive layer at least between the first and second redistribution layers and filling up gaps between adjacent first and second conductive bumps.
In some embodiments, the extraction structure comprises:
a lead-out rerouting layer located on the second surface of the first chip and covering an inner wall of the through hole, the lead-out rerouting layer being electrically connected with the first rerouting layer;
and the lead-out conductive bump is positioned on one side of the lead-out rerouting layer, which is away from the first chip, and is electrically connected with the lead-out rerouting layer.
In some embodiments, further comprising:
and the plastic layer is used for coating the first chip and the second chip, filling the through holes and covering the surface of the lead-out rewiring layer.
In some embodiments, further comprising:
and the heat dissipation structure is covered on the fourth surface of the second chip.
In some embodiments, further comprising:
and the third chip is stacked on the first surface of the first chip along the first direction, the third chip and the second chip are arranged along the second direction, the extraction structure is electrically connected with the third chip, and the second direction is intersected with the first direction.
In some embodiments, further comprising:
and a third rewiring layer positioned on the surface of the third chip facing the first chip, and electrically connected with the first rewiring layer.
According to other embodiments, the present invention further provides a method for forming a chip stack package structure, including the following steps:
forming a first chip, wherein the first chip comprises a first surface and a second surface which are distributed oppositely along a first direction;
stacking a second chip on the first surface of the first chip along the first direction;
forming a through hole penetrating the first chip along the first direction;
and forming an extraction structure positioned on the second surface of the first chip along the first direction, wherein the extraction structure is electrically connected with the first chip, and extends into the through hole and is electrically connected with the second chip.
In some embodiments, the first chip has a first redistribution layer on the first surface, the second chip includes a third surface opposite the first chip and a fourth surface opposite the third surface along the first direction, the third surface of the second chip has a second redistribution layer thereon; the specific step of stacking a second chip on the first surface of the first chip along the first direction includes:
and connecting the second chip on the first surface of the first chip in a direction of the third surface of the second chip towards the first chip, and electrically connecting the first rewiring layer and the second rewiring layer.
In some embodiments, the first redistribution layer has a first conductive bump on a surface facing away from the first chip that is electrically connected to the first redistribution layer, and the second redistribution layer has a second conductive bump on a surface facing away from the second chip that is electrically connected to the second redistribution layer; the specific step of connecting the second chip to the first surface of the first chip in a direction in which the third surface of the second chip faces the first chip includes:
connecting the first conductive bump and the second conductive bump;
and filling a first bonding layer between the first rewiring layer and the second rewiring layer, wherein the first bonding layer fills gaps between adjacent first conductive bumps and gaps between adjacent second conductive bumps.
In some embodiments, after stacking a second chip on the first surface of the first chip along the first direction, further comprising the steps of:
a first plastic layer is formed on the first surface of the first chip and encapsulates at least the second chip.
In some embodiments, the specific step of forming a via through the first chip in the first direction includes:
etching the first chip from the second surface of the first chip to form the through hole penetrating the first chip along the first direction.
In some embodiments, the specific step of forming an extraction structure located on the second surface of the first chip along the first direction includes:
forming an extraction re-wiring layer covering the inner wall of the through hole and the second surface of the first chip, wherein the extraction re-wiring layer is electrically connected with the first re-wiring layer;
and forming an outgoing conductive bump on the outgoing re-wiring layer and electrically connected to the outgoing re-wiring layer to form the outgoing structure comprising the outgoing re-wiring layer and the outgoing conductive bump.
In some embodiments, after forming the extraction structures located on the second surface of the first chip along the first direction, the method further comprises the steps of:
and forming a second plastic layer for plastic packaging the first chip, wherein the second plastic layer at least fills the through holes and covers the surface of the lead-out re-wiring layer.
In some embodiments, after forming the extraction structures located on the second surface of the first chip along the first direction, the method further comprises the steps of:
and forming a heat dissipation structure on the fourth surface of the second chip.
According to the chip stacking and packaging structure and the forming method thereof, the second chip is stacked on the first surface of the first chip, and the extraction structure is arranged on the second surface of the first chip, so that signals of the first chip can be extracted by the extraction structure, and signals of the second chip can be extracted by the through holes penetrating through the first chip; on the other hand, the second chip and the lead-out structure are arranged on two opposite sides of the first chip through the through holes, so that the size of the packaging structure is reduced, the miniaturized packaging structure is formed, and the difficulty of the manufacturing process of the packaging structure is reduced. In addition, in some embodiments of the present invention, the plastic layer covering the second surface of the first chip can fill the through hole, so as to realize stress balance on two opposite sides of the first chip, reduce the probability of deformation such as warpage of the first chip, or reduce the warpage of the first chip, thereby further improving the performance of the chip stacking package structure.
Drawings
FIG. 1 is a schematic diagram of a chip stack package structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another chip stack package structure according to an embodiment of the present invention;
FIG. 3 is a flowchart of a method for forming a chip stack package structure according to an embodiment of the present invention;
fig. 4-14 are schematic process structures of the chip stack package structure according to the embodiments of the present invention.
Detailed Description
The following describes in detail the chip stacking package structure and the forming method thereof with reference to the accompanying drawings.
In this embodiment, a chip stack package structure is provided, and fig. 1 is a schematic diagram of a chip stack package structure according to an embodiment of the present invention. As shown in fig. 1, the chip stack package structure includes:
a first chip 10 including a through hole 11 penetrating the first chip 10 along a first direction D1, the first chip 10 further including a first surface and a second surface distributed opposite to each other along the first direction D1;
a second chip 12 stacked on the first surface of the first chip 10 in a first direction D1;
and an extraction structure disposed on the second surface of the first chip 10 along the first direction D1, wherein the extraction structure is electrically connected with the first chip 10, and the extraction structure extends into the through hole 11 and is electrically connected with the second chip 12.
For example, the first chip 10 includes the first surface (i.e., the front surface of the first chip 10) on which the first device structure is formed and the second surface (i.e., the back surface of the first chip 10) opposite to the first surface in the first direction D1. The first direction D1 perpendicularly intersects the first surface. The second chip 12 includes a third surface (i.e., a front surface of the second chip 12) on which a second device structure is formed and a fourth surface (i.e., a back surface of the second chip 12) opposite to the third surface in the first direction D1. In one example, the first chip 10 has the same structure as the second chip 12. In another example, the structure of the first chip 10 is different from the structure of the second chip 12.
The second chip 12 is stacked on the first surface of the first chip 10 along the first direction D1, so that the chip stacking package structure at least includes two chips (i.e., the first chip 10 and the second chip 12) with the same or different functions, thereby contributing to improving the integration level of the package structure, facilitating the integration of chips with different technologies, structures and performances, and contributing to improving the performance of the package structure. The lead-out structure is located on the side of the first chip 10 facing away from the second chip 12. The lead-out structure is electrically connected with the first chip 10, and also electrically connected with the second chip 12 by penetrating through the through hole of the first chip 10 along the first direction D1, so that signals in the first chip 10 and signals in the second chip 12 can be led out through the lead-out structure, or control signals can be transmitted to the first chip 10 and control signals can be transmitted to the second chip 12 through the lead-out structure, the chip signal transmission distance is shortened, the insertion loss is reduced, and the product performance is improved. In an example, electrical connection between the first chip 10 and the second chip 12 may also be achieved by the extraction structures. By providing the through hole 11 in the first chip 10, the lead-out structure can be electrically connected with the second chip 12 through the through hole, so that the size of the package structure is reduced while ensuring that the signal of the second chip 12 can be led out or the control signal can be transmitted to the second chip 12, which contributes to the formation of a miniaturized package structure.
To further reduce the difficulty of manufacturing the chip stack package structure while further ensuring that signals in the first chip 10 and the second chip 12 are extracted, in some embodiments, the second chip 12 includes a third surface opposite the first chip 10 and a fourth surface opposite the third surface along the first direction D1; the chip stack package structure further includes:
a first redistribution layer 15 is located on the first surface of the first chip 10, and the lead-out structure extending into the through hole 11 is electrically connected to the first redistribution layer 15.
To further refine the connection process between the first chip 10 and the second chip 12, in some embodiments the chip stack package structure further comprises:
a second rewiring layer on the third surface of the second chip 12, and the first rewiring layer 15 being electrically connected with the second rewiring layer;
a first conductive bump 23 located on a surface of the first redistribution layer 15 facing away from the first chip 10, and the first conductive bump 23 is electrically connected to the first redistribution layer 15;
and a second conductive bump 24 on a surface of the second redistribution layer facing away from the second chip 12, wherein the first conductive bump 23 is connected to the second conductive bump 24.
To further increase the strength of the connection between the first and second redistribution layers 15, and thereby further improve the stability of the chip stack package structure, in some embodiments, the chip stack package structure further includes:
the first adhesive layer 18 is located at least between the first and second redistribution layers 15 and 24 and fills the gaps between the adjacent first conductive bumps 23 and the gaps between the adjacent second conductive bumps 24.
For example, the first redistribution layer 15 is disposed on the first surface of the first chip 10, and the first redistribution layer 15 is electrically connected to a first internal circuit within the first chip 10. The surface of the first redistribution layer 15 facing away from the first chip 10 is further provided with the first conductive bump 23 and a first solder cap on the first conductive bump 23. The surface of the second chip 12 facing the first chip 10 (i.e., the third surface) is provided with the second redistribution layer (not shown in fig. 1 and 2), and the second redistribution layer is electrically connected to a second internal circuit within the second chip 12. The surface of the second redistribution layer facing away from the second chip 12 is further provided with the second conductive bump 24 and a second solder cap located on the second conductive bump 24, and the second conductive bump 24 is electrically connected with the second redistribution layer. The first solder cap is connected (e.g., bonded or connected by a conductive silver glue layer) to the second solder cap to electrically connect the first redistribution layer 15 to the second redistribution layer, so that signals in the second chip 12 can be transmitted to the lead-out structure sequentially through the second redistribution layer, the second conductive bump 24, the second solder cap, the first conductive bump 23, and the first redistribution layer 15. The first adhesive layer 18 is located at least between the first redistribution layer 15 and the second redistribution layer and fills up the gaps between the adjacent first conductive bumps 23 and the gaps between the adjacent second conductive bumps 24, so that on the one hand, the connection strength between the first conductive bumps 23 and the second conductive bumps 24 can be enhanced; on the other hand, defects such as holes and the like generated in the chip stacking and packaging structure can be avoided, so that the performance of the chip stacking and packaging structure is further improved. In one example, the first adhesive layer 18 is made of an insulating adhesive.
In some embodiments, the extraction structure comprises:
a lead-out re-wiring layer 13 on the second surface of the first chip 10 and covering an inner wall of the through hole 11, the lead-out re-wiring layer 13 being electrically connected to the first re-wiring layer 15;
and an outgoing conductive bump 14 is located at one side of the outgoing rewiring layer 13 away from the first chip 10, and the outgoing conductive bump 14 is electrically connected with the outgoing rewiring layer 13.
For example, as shown in fig. 1, the extraction structure includes the extraction re-wiring layer 13 and the extraction conductive bump 14, the extraction re-wiring layer 13 is located on the second surface of the first chip 10 and covers the inner wall of the through hole 11 (including the side wall of the through hole 11 and the bottom wall of the through hole 11) to be electrically connected with the first re-wiring layer 15 under the through hole 11, so that the extraction structure and the second chip 12 can be electrically connected through the first re-wiring layer 15 and the second re-wiring layer. The first chip 10 may be directly electrically connected to the lead-out redistribution layer 13, or may be electrically connected to the lead-out redistribution layer 13 through the first redistribution layer 15. The outgoing conductive bumps 14 are located on the surface of the outgoing rewiring layer 13 facing away from the first chip 10. In an example, the lead-out structure further includes a lead-out portion on a side of the lead-out conductive bump 14 facing away from the lead-out redistribution layer 13, the lead-out portion being electrically connected to the lead-out conductive bump 14. In one example, the lead-out portion is a solder ball. In another example, the lead-out includes a fourth conductive bump 20 and a fourth solder cap 21 on the fourth conductive bump 20, the fourth conductive bump 20 being electrically connected to the lead-out conductive bump 14.
In an example, the sidewall of the through hole 11 is further covered with an isolation layer 25 for isolating the outgoing re-wiring layer 13 from the first chip 10, so as to avoid crosstalk between the electrical signal in the outgoing re-wiring layer 13 and the electrical signal inside the first chip 10.
In some embodiments, the chip stack package structure further comprises:
and the plastic layer is used for coating the first chip 10 and the second chip 12, filling the through holes 11 and covering the surface of the lead-out rerouting layer 13.
For example, the plastic layer includes a first plastic layer 17 and a second plastic layer 16. The first plastic layer 17 is located on the first surface of the first chip 10 and plastic encapsulates the second chip 12, the first redistribution layer 15, the second redistribution layer, and the first adhesive layer 18. The second molding layer 16 is located on the second surface of the first chip 10 and encapsulates the first chip 10, the lead-out redistribution layer 13 and the lead-out conductive bump 14, and the second molding layer 16 fills the through hole 11. By arranging the first plastic sealing layer 17 and the second plastic sealing layer 16 on two opposite sides of the first chip 10 along the first direction D1, stress inside the chip stacking and packaging structure is balanced, and probability of deformation such as warpage of the chip stacking and packaging structure is reduced, so that product yield and reliability are further improved. In an example, the material of the first plastic layer 17 and the material of the second plastic layer 16 are the same, for example, both are epoxy plastic materials. In an example, the surface of the second molding layer 16 is further covered with a dielectric layer 19, and the fourth conductive bump 20 is electrically connected to the lead conductive bump 14 through the dielectric layer 19.
In some embodiments, the chip stack package structure further comprises:
and the heat dissipation structure 22 is covered on the fourth surface of the second chip 12.
In an example, the heat dissipation structure 22 may be a metal heat dissipation layer covering the fourth surface of the second chip 12, thereby improving the heat dissipation performance of the second chip 12.
Fig. 2 is a schematic diagram of another chip stack package structure according to an embodiment of the invention. In other embodiments, the chip stack package structure further includes:
the third chip 26 is stacked on the first surface of the first chip 10 along the first direction D1, the third chip 26 and the second chip 12 are arranged along the second direction D2, the lead-out structure is electrically connected with the third chip 26, and the second direction D2 intersects with the first direction D1.
In some embodiments, the chip stack package structure further comprises:
a third re-wiring layer is located on a surface of the third chip 26 facing the first chip 10, and the third re-wiring layer is electrically connected to the first re-wiring layer 15.
For example, as shown in fig. 2, the second chip 12 and the third chip 26 are stacked on the first surface of the first chip 10, thereby further improving the integration of the chip stack package structure. The second chip 12 and the third chip 26 are arranged along the second direction D2, and the surface of the third chip 26 facing the first chip 10 has the third redistribution layer thereon, and the third redistribution layer has the third conductive bump 27 thereon. The first redistribution layer 15 has a plurality of first conductive bumps 23 arranged at intervals along the second direction D2, a part of the first conductive bumps 23 is electrically connected to the second conductive bumps 24, and a part of the first conductive bumps 23 is connected to the third conductive bumps 27, so that the lead-out structure can electrically connect the second chip 12 and the third chip 26 through the through holes 11 and the first redistribution layer 15. In an example, the chip stack package structure further includes a second adhesive layer 29 between the first chip 10 and the third chip 26, and filling up a gap between a part of adjacent first conductive bumps 23 and a gap between adjacent third conductive bumps 27. In another example, the first adhesive layer 18 may also continuously fill the gap between the first and second redistribution layers 15, 15 and the gap between the first and third redistribution layers. The first molding layer 17 continuously molds the second chip 12 and the third chip 26.
In other examples, the third chip 26 may be further stacked on a side of the second chip 12 facing away from the first chip 10, and an interconnection structure penetrating the second chip 12 along the first direction D1 is disposed in the second chip 12, and the interconnection structure electrically connects the third chip 26 and the second redistribution layer, so as to electrically connect the lead-out structure and the third chip 26 through the first redistribution layer 15, the second redistribution layer and the interconnection structure.
This embodiment is described taking as an example the stacking of the second chip 12 on the first surface of the first chip 10 or the simultaneous stacking of the second chip 12 and the third chip 26 on the first surface of the first chip 10. In other embodiments, the number of the second chips 12 stacked on the first surface of the first chip 10 may be plural, and the number of the third chips 26 may be plural, so as to further improve the integration level of the chip stack package structure. The plural numbers described in this embodiment mode refer to two or more.
The embodiment also provides a method for forming the chip stack package structure, fig. 3 is a flowchart of a method for forming the chip stack package structure in the embodiment of the invention, and fig. 4 to fig. 14 are schematic process structures of the embodiment of the invention in the process of forming the chip stack package structure. Schematic diagrams of the chip stack package structure formed in this embodiment may be seen in fig. 1 and fig. 2. As shown in fig. 1 to 14, the method for forming the chip stack package structure includes the following steps:
step S31, forming a first chip 10, where the first chip 10 includes a first surface 101 and a second surface 102 that are relatively distributed along a first direction D1, as shown in fig. 4;
step S32, stacking a second chip 12 on the first surface 101 of the first chip 10 along the first direction D1, as shown in fig. 8;
step S33, forming a through hole 11 penetrating the first chip 10 along the first direction D1, as shown in fig. 9;
in step S34, an extraction structure located on the second surface 102 of the first chip 10 along the first direction D1 is formed, the extraction structure is electrically connected to the first chip 10, and the extraction structure extends into the through hole 11 and is electrically connected to the second chip 12, as shown in fig. 10.
In some embodiments, the first surface 101 of the first chip 10 has a first redistribution layer 15 thereon, the second chip 12 includes a third surface 121 opposite the first chip 10 and a fourth surface 122 opposite the third surface 121 along the first direction D1, as shown in fig. 6, the third surface 121 of the second chip 12 has a second redistribution layer thereon; the specific steps of stacking the second chip 12 on the first surface 101 of the first chip 10 along the first direction D1 include:
the second chip 12 is connected to the first surface 101 of the first chip 10 in a direction in which the third surface 121 of the second chip 12 faces the first chip 10, and the first redistribution layer 15 and the second redistribution layer are electrically connected.
In some embodiments, the surface of the first redistribution layer 15 facing away from the first chip 10 has first conductive bumps 23 electrically connected to the first redistribution layer 15 thereon, and the surface of the second redistribution layer facing away from the second chip 12 has second conductive bumps 24 electrically connected to the second redistribution layer thereon; the specific step of connecting the second chip 12 to the first surface 101 of the first chip 10 in the direction of the third surface 121 of the second chip 12 toward the first chip 10 includes:
connecting the first conductive bump 23 and the second conductive bump 24;
a first adhesive layer 18 is filled between the first and second redistribution layers 15 and 18, and the first adhesive layer 18 fills the gaps between adjacent first conductive bumps 23 and the gaps between adjacent second conductive bumps 24.
For example, a first isolation layer 40 and a sacrificial layer 41 located in the first isolation layer 40 are formed on the first surface 101 of the first chip 10, as shown in fig. 4. Wherein the first isolation layer 40 and the sacrificial layer 41 have a high etching selectivity (for example, the etching selectivity is greater than 3), so as to facilitate subsequent selective etching. Next, the first re-wiring layer 15 is formed on the first isolation layer 40 by a re-wiring process, and the first conductive bump 23 on the first re-wiring layer 15 is formed by sputtering, photolithography, electroplating, etc., and the first re-wiring layer 15 is electrically connected to the first internal circuit within the first chip 10. The first redistribution layer 15 includes a first dielectric layer and a first metal trace 50 disposed in the first dielectric layer, as shown in fig. 5. In an example, the first conductive bump 23 is further provided with a first solder cap 51 and a conductive silver paste layer 52 on the first solder cap 51, as shown in fig. 5. A second redistribution layer is formed on the third surface 121 of the second chip 12 using a redistribution process, and the second conductive bump 24 and the second solder cap 70 on the second conductive bump 24 are formed on the second redistribution layer by a sputtering, photolithography, electroplating, or the like process, as shown in fig. 7. Then, the first solder caps 51 and the second solder caps 70 are electrically connected through the conductive silver paste layer 52 in a direction in which the first re-wiring layer 15 faces the second re-wiring layer, so as to achieve electrical connection between the first re-wiring layer 15 and the second re-wiring layer.
In some embodiments, after stacking the second chip 12 on the first surface 101 of the first chip 10 along the first direction D1, the method further includes the following steps:
a first plastic layer 17 is formed on the first surface 101 of the first chip 10 and covers at least the second chip 12, as shown in fig. 8.
For example, after stacking the second chip 12 on the first surface 101 of the first chip 10, a material such as an insulating paste is filled between the first and second redistribution layers 15 and 24 to form a first adhesive layer 18 filling up the gaps between the adjacent first conductive bumps 23 and the gaps between the adjacent second conductive bumps 24. Then, the first plastic layer 17 on the first surface 101 of the first chip 10 and plastic-sealing the second chip 12 and the first adhesive layer 18 is formed by a plastic-sealing process, as shown in fig. 8.
In some embodiments, the specific step of forming the through hole 11 penetrating the first chip 10 along the first direction D1 includes:
the first chip 10 is etched from the second surface 102 of the first chip 10, forming the through hole 11 penetrating the first chip 10 in the first direction D1, as shown in fig. 9.
For example, after the first molding layer 17 is formed, the first chip 10 is etched from the second surface 102 of the first chip 10 with the sacrificial layer 41 as an etching stop layer, and the through hole 11 penetrating the first chip 10 in the first direction D1 is formed as shown in fig. 9. Next, the sacrificial layer 41 is etched away with the first dielectric layer in the first redistribution layer as an etching stop layer, and the via 11 is extended to the surface of the first redistribution layer 15.
In some embodiments, the specific step of forming the extraction structures on the second surface 102 of the first chip 10 along the first direction D1 includes:
forming an extraction re-wiring layer 13 covering an inner wall of the through hole 11 and the second surface 102 of the first chip 10, the extraction re-wiring layer 13 being electrically connected to the first re-wiring layer 15;
an outgoing conductive bump 14 is formed on the outgoing re-wiring layer 13 and electrically connected to the outgoing re-wiring layer 13 to form the outgoing structure including the outgoing re-wiring layer 13 and the outgoing conductive bump 14, as shown in fig. 10.
For example, after the formation of the through-hole 11, a second isolation layer covering the sidewall of the through-hole 11 and the second surface 102 of the first chip 10 is formed, the second isolation layer and the first isolation layer 40 being used together as the isolation layer 25 (see fig. 1). Next, the lead-out re-wiring layer 13 covering the inner wall of the through hole 11 and the second surface 102 of the first chip 10 may be formed using a Plasma Enhanced Chemical Vapor Deposition (PECVD) and re-wiring process, and the lead-out conductive bump 14 may be formed on the surface of the lead-out re-wiring layer 13 by sputtering, photolithography, electroplating, etc., as shown in fig. 10.
In some embodiments, after forming the extraction structures located on the second surface 102 of the first chip 10 along the first direction D1, the method further includes the steps of:
a second molding layer 16 is formed to mold the first chip 10, and the second molding layer 16 at least fills the through hole 11 and covers the surface of the lead-out redistribution layer 13, as shown in fig. 11.
In some embodiments, after forming the extraction structures located on the second surface 102 of the first chip 10 along the first direction D1, the method further includes the steps of:
a heat dissipation structure 22 is formed on the fourth surface 122 of the second chip 12, as shown in fig. 14.
For example, after the lead-out conductive bump 14 is formed, the second plastic layer 16 that is located on the second surface 102 of the first chip 10 and covers the first chip 10, the lead-out redistribution layer 13, and the lead-out conductive bump 14 is formed through a plastic molding process, and the second plastic layer 16 fills the through hole 11, as shown in fig. 11. Next, a dielectric layer 19 is formed to cover the surface of the second molding layer 16, and windows are formed in the dielectric layer 19 by photolithography, so as to form a fourth conductive bump 20 electrically connected to the lead conductive bump 14 and a fourth solder cap 21 on the fourth conductive bump 20, as shown in fig. 12. Thereafter, a portion of the first molding layer 17 is removed by a grinding process or the like, exposing the fourth surface 122 of the second chip 12, as shown in fig. 13. Next, a heat dissipation structure 22 is formed on the fourth surface 122 of the second chip 12, as shown in fig. 14.
In this embodiment, the second molding layer 16 is used to mold the first chip 10, the outgoing rewiring layer 13, and the outgoing conductive bump 14. In other embodiments, the second molding layer 16 may encapsulate the side surface of the first chip 10 and the first molding layer 17 while molding the first chip 10, the outgoing re-wiring layer 13, and the outgoing conductive bump 14, so as to perform two-time molding on the second chip 12.
According to the chip stacking and packaging structure and the forming method thereof, the second chip is stacked on the first surface of the first chip, and the extraction structure is arranged on the second surface of the first chip, so that signals of the first chip can be extracted by the extraction structure, and signals of the second chip can be extracted by the through holes penetrating through the first chip; on the other hand, the second chip and the lead-out structure are arranged on two opposite sides of the first chip through the through holes, so that the size of the packaging structure is reduced, the miniaturized packaging structure is formed, and the difficulty of the manufacturing process of the packaging structure is reduced. In addition, in some embodiments of the present disclosure, the plastic layer covering the second surface of the first chip may fill the through hole, so as to balance stress on two opposite sides of the first chip, reduce the probability of deformation such as warpage of the first chip, or reduce the warpage of the first chip, thereby further improving the performance of the chip stacking package structure.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.

Claims (15)

1. A chip stack package structure, comprising:
the first chip comprises a through hole penetrating through the first chip along a first direction, and further comprises a first surface and a second surface which are distributed oppositely along the first direction, wherein the first surface of the first chip is provided with a first rewiring layer;
a second chip stacked on the first surface of the first chip in a first direction;
an extraction structure disposed on the second surface of the first chip along the first direction, the extraction structure being electrically connected to the first chip, and the extraction structure extending into the through hole and being electrically connected to the second chip to extract signals in the first chip and signals in the second chip through the extraction structure; the extraction structure comprises an extraction re-wiring layer, the extraction re-wiring layer is positioned on the second surface of the first chip and covers the inner wall of the through hole, and the extraction re-wiring layer extending into the through hole is electrically connected with the first re-wiring layer;
and the plastic layer is used for coating the first chip and the second chip, filling the through holes and covering the surface of the lead-out rewiring layer.
2. The chip stack package structure according to claim 1, wherein the second chip includes a third surface opposite to the first chip and a fourth surface opposite to the third surface in the first direction; the chip stack package structure further includes:
a second redistribution layer located on the third surface of the second chip, and the first redistribution layer is electrically connected with the second redistribution layer;
the first conductive bump is positioned on the surface of the first rewiring layer, which is away from the first chip, and is electrically connected with the first rewiring layer;
and the second conductive bump is positioned on the surface of the second redistribution layer, which is away from the second chip, and the first conductive bump is connected with the second conductive bump.
3. The chip stack package structure according to claim 2, further comprising:
and a first adhesive layer at least between the first and second redistribution layers and filling up gaps between adjacent first and second conductive bumps.
4. The chip stack package structure according to claim 2, wherein the lead-out structure includes:
and the lead-out conductive bump is positioned on one side of the lead-out rerouting layer, which is away from the first chip, and is electrically connected with the lead-out rerouting layer.
5. The chip stack package structure according to claim 2, further comprising:
and the heat dissipation structure is covered on the fourth surface of the second chip.
6. The chip stack package structure according to claim 2, further comprising:
and the third chip is stacked on the first surface of the first chip along the first direction, the third chip and the second chip are arranged along the second direction, the extraction structure is electrically connected with the third chip, and the second direction is intersected with the first direction.
7. The chip stack package structure according to claim 6, further comprising:
and a third rewiring layer positioned on the surface of the third chip facing the first chip, and electrically connected with the first rewiring layer.
8. The method for forming the chip stacking and packaging structure is characterized by comprising the following steps:
forming a first chip comprising a first surface and a second surface which are relatively distributed along a first direction, wherein the first surface of the first chip is provided with a first rewiring layer;
stacking a second chip on the first surface of the first chip along the first direction;
forming a through hole penetrating the first chip along the first direction;
forming an extraction structure located on the second surface of the first chip along the first direction, the extraction structure being electrically connected to the first chip, and the extraction structure extending into the through hole and being electrically connected to the second chip to extract signals in the first chip and signals in the second chip through the extraction structure; the extraction structure comprises an extraction re-wiring layer, the extraction re-wiring layer is positioned on the second surface of the first chip and covers the inner wall of the through hole, and the extraction re-wiring layer extending into the through hole is electrically connected with the first re-wiring layer; the chip stacking and packaging structure further comprises a plastic sealing layer, wherein the plastic sealing layer is used for coating the first chip and the second chip, and the plastic sealing layer is filled in the through hole and covers the surface of the lead-out re-wiring layer.
9. The method of forming a chip stack package structure according to claim 8, wherein the second chip includes a third surface opposite to the first chip and a fourth surface opposite to the third surface in the first direction, the third surface of the second chip having a second redistribution layer thereon; the specific step of stacking a second chip on the first surface of the first chip along the first direction includes:
and connecting the second chip on the first surface of the first chip in a direction of the third surface of the second chip towards the first chip, and electrically connecting the first rewiring layer and the second rewiring layer.
10. The method of claim 9, wherein the surface of the first redistribution layer facing away from the first chip has a first conductive bump electrically connected to the first redistribution layer, and the surface of the second redistribution layer facing away from the second chip has a second conductive bump electrically connected to the second redistribution layer; the specific step of connecting the second chip to the first surface of the first chip in a direction in which the third surface of the second chip faces the first chip includes:
connecting the first conductive bump and the second conductive bump;
and filling a first bonding layer between the first rewiring layer and the second rewiring layer, wherein the first bonding layer fills gaps between adjacent first conductive bumps and gaps between adjacent second conductive bumps.
11. The method of forming a chip stack package according to claim 9, further comprising, after stacking a second chip on the first surface of the first chip in the first direction, the steps of:
a first plastic layer is formed on the first surface of the first chip and encapsulates at least the second chip.
12. The method of forming a chip stack package structure according to claim 8, wherein the specific step of forming a through hole penetrating the first chip in the first direction comprises:
etching the first chip from the second surface of the first chip to form the through hole penetrating the first chip along the first direction.
13. The method of forming a chip stack package structure according to claim 9, wherein the specific step of forming the lead-out structure located on the second surface of the first chip in the first direction includes:
forming an extraction re-wiring layer covering the inner wall of the through hole and the second surface of the first chip, wherein the extraction re-wiring layer is electrically connected with the first re-wiring layer;
and forming an outgoing conductive bump on the outgoing re-wiring layer and electrically connected to the outgoing re-wiring layer to form the outgoing structure comprising the outgoing re-wiring layer and the outgoing conductive bump.
14. The method of forming a chip stack package structure according to claim 13, further comprising, after forming the lead-out structure located on the second surface of the first chip in the first direction, the steps of:
and forming a second plastic layer for plastic packaging the first chip, wherein the second plastic layer at least fills the through holes and covers the surface of the lead-out re-wiring layer.
15. The method of forming a chip stack package structure according to claim 9, further comprising, after forming the lead-out structure located on the second surface of the first chip in the first direction, the steps of:
and forming a heat dissipation structure on the fourth surface of the second chip.
CN202410068699.9A 2024-01-17 2024-01-17 Chip stacking and packaging structure and forming method thereof Active CN117594538B (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070194426A1 (en) * 2006-02-21 2007-08-23 Chi-Hsing Hsu Chip package and stacked structure of chip packages
CN104008998A (en) * 2014-06-10 2014-08-27 山东华芯半导体有限公司 Multi-chip stacked packaging method
CN106158691A (en) * 2015-01-27 2016-11-23 精材科技股份有限公司 Stripping device and method for stripping surface cover layer of chip package by using same
CN109962063A (en) * 2017-12-26 2019-07-02 深迪半导体(上海)有限公司 A kind of multichip packaging structure and technique
CN115642142A (en) * 2022-10-19 2023-01-24 深圳市汇顶科技股份有限公司 Chip stacking packaging structure and packaging method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070194426A1 (en) * 2006-02-21 2007-08-23 Chi-Hsing Hsu Chip package and stacked structure of chip packages
CN104008998A (en) * 2014-06-10 2014-08-27 山东华芯半导体有限公司 Multi-chip stacked packaging method
CN106158691A (en) * 2015-01-27 2016-11-23 精材科技股份有限公司 Stripping device and method for stripping surface cover layer of chip package by using same
CN109962063A (en) * 2017-12-26 2019-07-02 深迪半导体(上海)有限公司 A kind of multichip packaging structure and technique
CN115642142A (en) * 2022-10-19 2023-01-24 深圳市汇顶科技股份有限公司 Chip stacking packaging structure and packaging method

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